Tag Archives: letter-ap-tech

By Paula Doe, SEMI

The explosive growth in demand for internet bandwidth and cloud computing capacity brings a new set of technology challenges and opportunities for the semiconductor supply chain. “Azure grew by 2X last year, but we can’t pull more performance out of the existing architecture,” noted Kushagra Vaid, Microsoft’s GM Hardware Engineering, Cloud & Enterprise, at last week’s Linley Cloud Hardware Conference in Santa Clara, Calif.  “We are at a junction point where we have to evolve the architecture of the last 20-30 years.” He stressed that the traditional way of designing chips and systems to optimize for particular workloads isn’t working anymore. “We can’t design for a workload so huge and diverse. It’s not clear what part of it runs on any one machine,” he noted. “How do you know what to optimize? Past benchmarks are completely irrelevant.”

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Roadmap accelerates for networking chips 

Look for accelerating change in the networking chip market. Now that merchant chip suppliers have taken over 75 percent of the networking chip market from the proprietary suppliers, intense competition has meant astonishing improvements in reducing size and power, and two-year technology cycles, reported keynote speaker Andreas Bechtolsheim, Arista Networks Chief Development Officer and Chairman.  “The cloud is accelerating transitions, as the big data centers demand low cost,” he noted, explaining that new technologies no longer see gradual adoption through different applications. They have to start out cheaper to get any traction at all, but then ramp sharply to high volume in six months as high-volume data centers convert.

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Bechtolsheim said the majority of the network link market will convert from 40G to 100G this year, and to 400G in 2019.  For 800G two years later, chip design will have to start this year. Luckily there’s a clear path for scaling on the chip side, from the current generation’s 28nm technology down to 16nm and 7nm.  But it could be a push for some of the ecosystem. “It’s pushing the packaging vendors, as 1.0mm solder balls are about the limit,” said Bechtolsheim. Companies are also forming a group to speed the standards process by making the 800G standard simply 2X that for 400G, as the 400B standard took eight years.

The 40G chips at the server layer are moving to pulse amplitude modulation (PAM4) to send and receive four signals at once, which will require moving to digital signal processing. Moving from analog bipolar to digital CMOS technology also enables significant scaling of chip size and power, with significant reduction in die area (~50 percent) and power (~40 percent) with 16nm FinFET compared to 28nm, noted MACOM’s Chris Collins, director of Marketing. The company plans 7nm 800G devices next year.

New layers and new types of memory

One likely change is new types and new placement for memory, for higher speeds, different levels of non-volatile cache, and designs and accelerator subsystems that limit the need to move large amounts of data back and forth over limited pipelines. “Data is doubling every 2-2.5 years, but DRAM bandwidth is only doubling every 5 years. It’s not keeping up,” noted Steven Woo, Rambus VP, Systems and Solutions. “We’ll see the addition of more tiers of memory over the next few years.” He suggested the emerging challenge would be what data to place where, using what technology, and how to move memory in general closer to the processing. Racks may become the basic unit instead of servers, so each can be optimized with more memory or more processors as needed.

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Specialized accelerators speed particular applications

Another emerging solution is specialized chips or subsystem boards to accelerate particular types of cloud processing by taking over some jobs from the CPU cores, typically with different types of processors and lots of localized memory. Google and Wave Computing have their accelerator chips optimized for neural network processing. Mellanox offers offload adopter cards based on ASICs, FPGAs or RISC, with increasingly complex functions, claiming the potential to offload as much as of 80 percent of the overhead function of the CPU, to get a 2.7X increase in throughput per server.  MoSys proposes replacing conventional content addressable memory with a programmable search engine, based on an FPGA, a lot of SRAM, and software to search and route with different strategies for different types of applications to significantly increase speeds. Chelsio offers a module to handle encryption and decryption off the CPU without having to shuttle information back and forth to memory. Amazon even is renting FPGAs in its cloud so users can design their own accelerators for their particular workloads. But Microsoft’s Vaid remained skeptical that a proliferation of solutions for particular applications would be the best approach for the general use in the cloud.

300mm production and passive fiber alignment improve silicon photonics

Silicon photonics technology continues to make progress, and may find application in the market for very high bandwidth, mid to long haul transmission (30 meters to 80 kilometer), where spectral efficiency is the key driver, suggested Ted Letavic, Global Foundries, Senior Fellow. “4.5 and 5G communications will use photonics solutions similar to those needed in the data center, for volume that will drive down cost,” he noted. The foundry has now transferred its monolithic process to 300mm wafers, where the immersion lithography enables better overlay and line edge roughness, to reduce losses by 3X.  The company has an automated, passive solution to attach the optical fiber to the edge of the chip, pushing ribbons of multiple fibers into MEMS groves in the chip with an automated pick and place tool.  Letavic said the edge coupling process was in production for a telecommunications application.

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

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Ultratech, Inc. (Nasdaq:  UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received a repeat, multiple-system order from a leading semiconductor manufacturer for its advanced packaging AP300 lithography systems. The AP300 systems will be utilized for high-volume, leading-edge, fan-out wafer-level packaging (FOWLP) applications used to manufacture application processors. Ultratech will begin shipping the AP300 systems in the first two quarters of this year to the customer’s facility in Asia.

Ultratech General Manager and Vice President of Lithography Products Rezwan Lateef stated, “Ultratech has maintained its leadership position in the advanced packaging market segment by consistently delivering superior on-wafer results, cost-of-ownership and reliability performance for high-volume manufacturing (HVM) environments. Fan-out technologies continue to be the optimal solution for the highly-demanding mobile and wireless markets by offering improved performance in a reduced form factor. The AP300 is ideally suited to address this market with HVM -proven extendibility well below 2 microns. This substantial repeat order again confirms our technology leadership and the value proposition of Ultratech’s AP300 systems over full-field 1X scanners and reduction steppers. We are pleased to expand our photolithography-tool-of-record position at this valued customer. We look forward to working with them to meet their volume production and technology roadmaps.”

Ultratech’s AP300 Family of Lithography Steppers 

The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance and enabling highly-automated and cost-effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.

Toshiba America Electronic Components, Inc. (TAEC) has added a new photorelay to its extensive lineup of photocouplers. Housed in the Toshiba-developed S-VSON4, the industry’s smallest package, the new TLP3406S is suited for use in automatic test equipment, measuring instruments, high-speed logic IC testers, high-speed memory testers, and probe cards.

Semiconductor testers and other applications are pushing photorelays to support higher temperatures in a smaller package size. Toshiba has answered the call with its new TLP3406S. The upper end of the TLP3406S’s operating range is 110°C (max.), which is up from 85°C (max.) in previous offerings.  In spite of its small package size, the TLP3406S features a very small on-resistance and on/off switching of currents as high as 1.5A, enabling it to be used for switching applications in high-speed testers.

The use of Toshiba’s S-VSON4 package reduces the mounting area by approximately 22.5 percent when compared to larger VSON4 packages. This reduction in size will enable the development of smaller test boards, and can increase density by allowing for the inclusion of more photorelays on a board.

Most batteries are composed of two solid, electrochemically active layers called electrodes, separated by a polymer membrane infused with a liquid or gel electrolyte. But recent research has explored the possibility of all-solid-state batteries, in which the liquid (and potentially flammable) electrolyte would be replaced by a solid electrolyte, which could enhance the batteries’ energy density and safety.

Now, for the first time, a team at MIT has probed the mechanical properties of a sulfide-based solid electrolyte material, to determine its mechanical performance when incorporated into batteries.

The new findings were published this week in the journal Advanced Energy Materials, in a paper by Frank McGrogan and Tushar Swamy, both MIT graduate students; Krystyn Van Vliet, the Michael (1949) and Sonja Koerner Professor of Materials Science and Engineering; Yet-Ming Chiang, a professor of materials science and engineering; and four others including an undergraduate participant in the National Science Foundation Research Experience for Undergraduate (REU) program administered by MIT’s Center for Materials Science and Engineering and its Materials Processing Center.

Lithium-ion batteries have provided a lightweight energy-storage solution that has enabled many of today’s high-tech devices, from smartphones to electric cars. But substituting the conventional liquid electrolyte with a solid electrolyte in such batteries could have significant advantages. Such all-solid-state lithium-ion batteries could provide even greater energy storage ability, pound for pound, at the battery pack level. They may also virtually eliminate the risk of tiny, fingerlike metallic projections called dendrites that can grow through the electrolyte layer and lead to short-circuits.

“Batteries with components that are all solid are attractive options for performance and safety, but several challenges remain,” Van Vliet says. In the lithium-ion batteries that dominate the market today, lithium ions pass through a liquid electrolyte to get from one electrode to the other while the battery is being charged, and then flow through in the opposite direction as it is being used. These batteries are very efficient, but “the liquid electrolytes tend to be chemically unstable, and can even be flammable,” she says. “So if the electrolyte was solid, it could be safer, as well as smaller and lighter.”

But the big question regarding the use of such all-solid batteries is what kinds of mechanical stresses might occur within the electrolyte material as the electrodes charge and discharge repeatedly. This cycling causes the electrodes to swell and contract as the lithium ions pass in and out of their crystal structure. In a stiff electrolyte, those dimensional changes can lead to high stresses. If the electrolyte is also brittle, that constant changing of dimensions can lead to cracks that rapidly degrade battery performance, and could even provide channels for damaging dendrites to form, as they do in liquid-electrolyte batteries. But if the material is resistant to fracture, those stresses could be accommodated without rapid cracking.

Until now, though, the sulfide’s extreme sensitivity to normal lab air has posed a challenge to measuring mechanical properties including its fracture toughness. To circumvent this problem, members of the research team conducted the mechanical testing in a bath of mineral oil, protecting the sample from any chemical interactions with air or moisture. Using that technique, they were able to obtain detailed measurements of the mechanical properties of the lithium-conducting sulfide, which is considered a promising candidate for electrolytes in all-solid-state batteries.

“There are a lot of different candidates for solid electrolytes out there,” McGrogan says. Other groups have studied the mechanical properties of lithium-ion conducting oxides, but there had been little work so far on sulfides, even though those are especially promising because of their ability to conduct lithium ions easily and quickly.

Previous researchers used acoustic measurement techniques, passing sound waves through the material to probe its mechanical behavior, but that method does not quantify the resistance to fracture. But the new study, which used a fine-tipped probe to poke into the material and monitor its responses, gives a more complete picture of the important properties, including hardness, fracture toughness, and Young’s modulus (a measure of a material’s capacity to stretch reversibly under an applied stress).

“Research groups have measured the elastic properties of the sulfide-based solid electrolytes, but not fracture properties,” Van Vliet says. The latter are crucial for predicting whether the material might crack or shatter when used in a battery application.

The researchers found that the material has a combination of properties somewhat similar to silly putty or salt water taffy: When subjected to stress, it can deform easily, but at sufficiently high stress it can crack like a brittle piece of glass.

By knowing those properties in detail, “you can calculate how much stress the material can tolerate before it fractures,” and design battery systems with that information in mind, Van Vliet says.

The material turns out to be more brittle than would be ideal for battery use, but as long as its properties are known and systems designed accordingly, it could still have potential for such uses, McGrogan says. “You have to design around that knowledge.”

At next week’s SPIE Photonics West in San Francisco, imec, a research and innovation hub in nano-electronics and digital technologies, will introduce a new image sensor with integrated color (Red Green Blue, RGB) and narrow-band near-infrared (NIR) filters. This breakthrough optical filter integration platform will enable many different application fields from medical, industrial, security surveillance, automotive to virtual and augmented reality, where near-infrared signals need to be extracted and overlaid on top of color images.

Imec’s RGB-NIR multispectral platform demonstrates for the very first time the possibility to integrate together standard RGB color filters, NIR-cut filter, NIR narrow band-pass filters and on-chip microlenses technology, down to small pixels as small as 5µm today. The NIR band-pass filter and design pattern implementation can be tuned to match requirements of a specific application case, e.g. the wavelength of a particular laser or LED light.

“An affordable, high resolution and high speed solution for integrating true RGB color combined with narrow-band NIR detection was essential to develop for future applications that need to detect or track near infra-red signals that should not be visible to human eyes,” explains Andy Lambrechts, program manager for imec’s integrated imaging activities. “This capability to integrate a color view with one or several near-infrared narrow bands will be a key enabler for next-generation 3D, virtual reality (VR) & augmented reality (AR) imaging platforms. As well as in machine vision, medical, automotive and security surveillance applications.”

Leveraging imec’s background in CMOS scaling, its semiconductor fab, equipment and process technology, imec designs and manufactures interference based optical filters at wafer level, deposited and patterned directly on top of the CMOS image sensor pixels. Imec’s unique infrastructure provides very integrated, clean (class 1 – particle free) and high yield optical filter integration with strong potential for scalability in high-volume.

The first image sensor and camera prototypes will be demonstrated at SPIE Photonics West in San-Francisco on booth 4333 (North Hall of Moscone center). They are already available for early sampling and evaluation by strategic partners.

image005

STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has been ranked among the world’s top 10 semiconductor equipment manufacturing companies in the 2016 Patent Power Scorecards published by the Institute of Electrical and Electronics Engineers (IEEE), the world’s largest professional association for the advancement of technology. This is the seventh consecutive year that STATS ChipPAC has been recognized in the annual scorecards.

The 2016 Patent Power Scorecards are based on objective, quantitative benchmarking of U.S. Patent and Trademark Office records by 1790 Analytics, an Intellectual Property (IP) evaluation firm. The patent portfolios of more than 6,500 leading commercial enterprises, academic institutions, nonprofit organizations, and government agencies worldwide were reviewed through the end of 2015.  The scorecards rate the most valuable IP portfolios based on several factors including the size of an organization’s patent portfolio, quality, impact, originality and general applicability.

STATS ChipPAC was ranked eighth in the Semiconductor Equipment Manufacturing scorecard, the highest ranking received by an Outsourced Semiconductor Assembly and Test (OSAT) provider for the year. As of the end of 2015, STATS ChipPAC had been granted more than 1,500 patents by the U.S. Patent and Trademark Office (USPTO). STATS ChipPAC has been the leading U.S. patent holder among OSAT providers worldwide since 2011 and has built up a patent portfolio in which advanced or future technologies comprise more than 65% of its IP, significantly higher than other OSATs in the industry.

“Year after year we have continued to focus on technology innovation and prioritized our investments in key areas such as wafer level packaging, flip chip interconnection, System-in-Package (SiP), 2.5D and 3D integration. By driving technology development in these areas, we are able to provide innovative integration solutions that enable our customers to differentiate their products in the marketplace,” said Shim Il Kwon, Chief Technology Officer, STATS ChipPAC. “With the combined strength of the JCET Group, we offer our customers an IP portfolio that is unmatched in the OSAT industry.”

At the 2017 European 3D Summit in Grenoble (France, Jan 23-25), research and innovation hub for nano-electronics and digital technology imec and supplier of wafer-bonding equipment EV Group (EVG) announce an extension to their successful collaboration, achieving excellent wafer-to-wafer overlay accuracy results in both hybrid bonding and dielectric bonding. Expanding this collaboration, EVG will become a partner in imec’s 3D integration program through a joint development agreement to further improve overlay accuracy in wafer-to-wafer bonding.

Wafer-to-wafer bonding is a promising technique for enabling high-density integration of future ICs through three-dimensional (3D) integration. This is achieved by aligning top and bottom wafers that are then bonded, thus creating a stacked IC. An important advantage is that wafers/ICs with different technologies can be stacked, e.g. memory and processor ICs.

Many of the alignment techniques and bonding methods for 3D integration have evolved from microelectromechanical system (MEMS) fabrication methods. The fundamental difference between MEMS and 3D integration is that the alignment or overlay accuracy has to be improved by 5–10 times. Accurate overlay is needed to align the bonding pads of the stacked wafers and it is essential to achieving a high yield with wafer-to-wafer bonding. Imec and EVG have realized excellent results on overlay accuracy.

Firstly, the hybrid (via-middle) wafer-to-wafer bonding technique was improved by using EVG’s high quality bonding system with integration definition of bonding pads, resulting in a high yield and a 1.8µm pitch, which is significantly better compared to recently published results at recognized conferences such as ECTC and 3DIC reporting 3.6µm pad size,.

Secondly, the dielectric (via-last) wafer-to-wafer bonding technique was tackled. This technique requires extremely good overlay accuracy to align the copper pads from both wafers, which are then contacted by through-silicon vias (TSVs). In this case, 300nm overlay across the wafer was achieved.

“By joining forces, we achieved these excellent results on overlay accuracy,” explains Eric Beyne, fellow at imec. “We are excited that we can expand our collaboration with EVG with a JDP and the installation of EVG’s GEMINI FB XT wafer bonder in our cleanroom. The GEMINI FB XT has the potential to further reduce the wafer-to-wafer overlay errors and therefore allow for the development of sub-micron wafer-to-wafer interconnects technologies.”

“Further improving the overlay accuracy for wafer-to-wafer bonding into the sub-200nm range requires optimization of the interaction between the wafer bonding tool and processes as well as pre-and post-processing and the wafer material,” explains Markus Wimplinger, corporate technology development & IP director at EVG. “We are excited to partner with imec in an effort to advance overlay accuracies for wafer-to-wafer bonding to meet the needs of future 3D IC designs that rely on high density interconnects”

Imec’s 3D integration program explores technology options to define innovative solutions for cost-effective realization of 3D interconnect with TSVs. Imec’s 3D integration processes are completely executed on 300mm. Imec also explores 3D design to propose methodologies for critical design issues, enabling effective use of 3D interconnection on system level.

imec wafer to wafer

AGC Asahi Glass (AGC), a manufacturer of glass, chemicals and high-tech materials, today announced it has developed a diverse line of glass substrates specifically designed for semiconductor packaging applications and semiconductor manufacturing process support. The company is demonstrating the new substrates at NEPCON JAPAN 2017, opening today at Tokyo Big Sight and running through Friday, January 20. AGC’s exhibit can be found at booth W3-6 in the West Hall (1F).

Key advanced packaging technologies are poised to benefit from the AGC products. Wafer-level packaging (WLP) technology – in which the IC is packaged while still part of the wafer – has made remarkable progress with next-generation semiconductor and MEMS devices. This has resulted in a growing need for glass wafers – in particular, those that can match silicon’s coefficient of thermal expansion (CTE), thus eliminating the warping that occurs when attempting to directly laminate silicon and glass wafers whose CTE values differ.

Another target technology for the new substrates is fan-out wafer-level packaging (FOWLP), which enhances standard WLP technology to provide a smaller package footprint with improved thermal and electrical performance. It involves joining materials with different CTEs, including silicon wafers, rewiring layers and resin. As combinations and patterns vary from device to device, glass substrates that can provide the optimal CTE for each element are needed. Also, since the alkaline component of ordinary glass can cause contamination in production processes and devices, alkali-free glass is desirable in certain applications.

Designed to satisfy a wide range of customer needs, the new AGC glass substrates can be provided in rectangular and square shapes, as well as traditional round wafers, with thicknesses ranging from 0.2 mm to 2 mm. The lineup includes:

  • Glass without alkali
  • Glass products that maintain the exact same CTE as silicon through temperatures ranging from ambient air temperature to roughly 250°C
  • Glass products covering a wide range of CTE values from 3 ppm/°C to 8 ppm/°C
  • Glass with alkali
  • Glass products covering higher ranges of up to CTE 12 ppm/°C

Dow Corning significantly expanded the design flexibilities for LED packaging manufacturers today with the addition of three new highly reflective silicone coatings to its fast-growing portfolio of advanced LED solutions. Offering targeted solutions for cutting-edge LED designs – such as chip scale (CSP) and chip on-board (COB) packaging – the three new products also deliver versatile processing options ranging from conventional dispensing to emerging printing methods.

All introduced under the Dow Corning label, the three new products include WR-3001 Die Edge Coat, WR-3100 Die Edge Coat and WR-3120 Reflective Coating. In the future, products are planned to be added to match customer required processes.

“Manufacturers are aggressively seeking to design smaller, more efficient and cost-effective LED packages, which is driving demand for advanced new reflective materials that enable evolving application processes such as printing, and withstand increasingly stringent operating conditions,” said Takuhiro Tsuchiya, global marketing manager at Dow Corning. “These three cutting-edge coatings are only the first of a range of new products that we have in store for the industry. A proactive and collaborative innovator, Dow Corning formulated these three reflective silicone coatings specifically to help customers overcome today’s greatest design challenges and deliver highly reliable and differentiated products in the fiercely competitive LED market.”

As with all of Dow Corning reflective materials, the three new grades maintain high reflectivity at low thicknesses and retain their performance at sustained temperatures of 150°C – a temperature at which many organic coatings crack and yellow. Listed in order of increasing hardness, the new products include:

  • WR-3001 Die Edge Coat targets high-power CSP applications that demand LED materials with high thermal- and photostability. It is compatible with conventional dispensing processes.
  • WR-3100 Die Edge Coat is formulated for CSP applications and low- to middle-power LED package designs. Compatible with conventional dispensing equipment, it delivers comparatively high hardness of Shore D 65 after cure, making it suitable with chip dicing processes.
  • WR-3120 Reflective Coating also provides high thermal- and photostability suitable for high-power LED packaging applications, as well as the highest hardness of Dow Corning’s three new products. Suitable for printing processes, this advanced silicone further offers the highest reflectivity for enhanced LED performance.

A market leader in materials, expertise and collaborative innovation for LED lighting concepts, Dow Corning offers solutions that span the entire LED value chain, adding reliability and efficiency for sealing, protecting, adhering, cooling and shaping light across all lighting applications.

Researchers have developed a new type of optomechanical device that uses a microscopic silicon disk to confine optical and mechanical waves. The new device is highly customizable and compatible with commercial manufacturing processes, making it a practical solution for improving sensors that detect force and movement.

Researchers created an optomechanical silicon bullseye disk that traps optical waves in the outermost ring via total internal reflection while the radial groves confine the mechanical waves to the same area. Credit: Thiago P. Mayer Alegre, University of Campinas

Researchers created an optomechanical silicon bullseye disk that traps optical waves in the outermost ring via total internal reflection while the radial groves confine the mechanical waves to the same area. Credit: Thiago P. Mayer Alegre, University of Campinas

Optomechanical devices use light to detect movement. They can be used as low-power, efficient building blocks for the accelerometers that detect the orientation and movement of a smart phone or that trigger a car’s airbag to deploy split seconds after an accident. Scientists are working to make these devices smaller and even more sensitive to movement, forces and vibrations.

Identifying the smallest movements requires extremely high levels of interaction, or coupling, between light waves, which are used for detection, and the mechanical waves that are tied to movement. In The Optical Society journal Optics Express, researchers from the University of Campinas, Brazil, report that their new bullseye disk design achieves coupling rates that match those of the best lab-based optomechanical devices reported.

While most state-of-the-art optomechanical devices are made using equipment that isn’t widely available, the new bullseye disk device was fabricated in a standard commercial foundry with the same processes used to manufacture complementary metal-oxide-semiconductor (CMOS) chips, such as the ones used in most digital cameras.

“Because the device was made at a commercial CMOS foundry, any group in the world could reproduce it,” said Thiago P. Mayer Alegre, leader of the research group. “If thousands were made, they would all perform in the same manner because we made them resilient to the foundry’s fabrication processes. It is also much cheaper and faster to make these types of devices at a CMOS foundry rather than using specialized in-house fabrication techniques.”

Bringing light and motion together

Most optomechanical devices use the same mechanism to confine both the light and mechanical waves inside a material, where the waves can interact. However, this approach can limit the performance of optomechanical devices because only certain materials work well for confining both light and mechanical motion.

“Once you decouple the confinement rules for the light and mechanics, you can use any type of material,” said Alegre. “It is also makes it possible to independently tailor the device to work with certain light frequencies or mechanical wave frequencies.”

The researchers created a silicon disk 24 microns wide that confines the light and mechanical waves using separate mechanisms. The light is confined with total internal reflection, which causes the light to bounce off the edge of the disk and travel around the outer portion in a circular ring. The researchers added circular groves to the disc, giving it the appearance of a bullseye, to localize mechanical motion to the outer ring, where it can interact with the light. The disk is supported by a central pedestal that allows the disk to move.

“Radial groves have been used to confine light waves in other devices, but we took this idea and applied it to mechanical waves,” said Alegre. “Our optomechanical device is the first one to use radial groves to couple mechanical and optical waves.”

The versatility of the bullseye disk design means it could be used for more than sensing movement. For example, making the disk out of a lasing material could create a laser with pulses or power levels that are controlled by motion. The device could also be used to make very small and high frequency optical modulator for telecommunication applications.

The researchers are now working to further refine their device’s design to work even better with CMOS foundry fabrication processes. This should lessen the amount of light that is lost by the disk and thus improve overall performance. They also want to make the device even more practical by combining the optomechanical disk with an integrated optical waveguide that would bring light to and from the device, all in one package.