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Imagine a dim light which is insufficiently bright enough to illuminate a room. An amplifier for such a light would increase the brightness by increasing the number of photons emitted. Photonics researchers have created such a high gain optical amplifier that is compact enough to be placed on a chip. The developed amplifier, when used within an optical interconnect such as a transceiver or fiber optic network, would help to efficiently increase the power of the transmitted light before it is completely depleted through optical losses.

Singapore University of Technology and Design Assistant Professor Dawn Tan and the newly developed amplifier on a chip. Credit: Courtesy of Dr. Dawn Tan

Singapore University of Technology and Design Assistant Professor Dawn Tan and the newly developed amplifier on a chip. Credit: Courtesy of Dr. Dawn Tan

Besides having the potential to replace bulky, expensive amplifiers used today for the study of attosecond science and ultrafast optical information processing, the newly developed nanoscale-amplifier also provides a critical element to the optical interconnects toolkit, potentially providing regenerative amplification in short to long range interconnects. This work was a collaborative effort between researchers at the Singapore University of Technology and Design (SUTD), A*STAR Data Storage Institute and the Massachusetts Institute of Technology. Details appeared in Nature Communications on January 4th 2017.

“We have developed an optical amplifier which is able to amplify light by 17,000 times at the telecommunications wavelength,” said Assistant Professor Dawn Tan at SUTD who led the development of the amplifier. “We use a proprietary platform called ultra-silicon-rich nitride, with a material composition of seven parts silicon, three parts nitrogen, with the large nonlinearity and photon efficiency needed for high gain amplification, through the efficient transfer of photons from a pump to the signal. To give a sense of the scale, a conventional optical parametric amplifier costs several hundred thousand dollars, and occupies an entire optical table, while the newly developed amplifier is much smaller than a paper clip, and costs a fraction of the former.”

Providing high gain on such a small footprint could enable new opportunities in low cost broadband spectroscopy, precision manufacturing and hyperspectral imaging. The device’s efficiency is also revealed through cascaded four wave mixing, which is a higher order mixing of the amplified and converted photons. This phenomenon also allows the amplifier to operate as a tunable broadband light source, enabling cheaper and more efficient spectroscopic sensing and molecular fingerprinting than what is available today.

“The inefficiencies in highly nonlinear photonic devices are overcome here, by photonic device engineering for maximum nonlinearity, while still maintaining a sufficiently large bandgap to eliminate two-photon absorption at the telecommunications wavelength. We believe this is one of the highest gains demonstrated at the telecommunications wavelength to date on a CMOS chip” said Prof Tan.

Achieving ultra-large amplification while maintaining high compactness was possible because the researchers managed to design and implement an amplifier which operates simultaneously with a high nonlinearity and photon efficiency. In other platforms which are compatible with processes used in the electronics industry today, either the nonlinearity or photon efficiency is low.

“The results demonstrate the ultra-silicon-rich nitride platform to be extremely promising for highly efficient nonlinear optics applications, particularly in the field of CMOS photonics leveraging existing electronics infrastructure,” says Dr. Doris Ng, Scientist III at the A*STAR Data Storage Institute.

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 – 8, 2017. In a departure from previous years, both Symposia (VLSI Technology and VLSI Circuits) will be held on a fully overlapping schedule from June 6 – 8, preceded by Short Courses on June 5.

The deadline for paper submissions to both Symposia is January 23, 2017. Complete details for paper submission can be found online at: http://vlsisymposium.org/authors.html

For the past 30 years, the combined annual Symposia on VLSI Technology and Circuits have provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees. A single registration enables participants to attend both Symposia.

Papers sought for “big integration”
This year’s Symposia theme is “Harmonious Integration Toward Next Dimensions.” Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module level, with co-optimization of device technology and circuit/system design, including focus areas in the Internet of Things (IoT), industrial electronics, ‘big data’ management, artificial intelligence (AI), biomedical applications, virtual reality (VR) / augmented reality (AR), robotics and smart cars. These topics will be featured in focus sessions as part of the program.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

  • IoT systems & technologies, including ultra-low power, heterogeneous integration, wearable devices, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
  • Stand-alone & embedded memories, including technology & reliability for DRAM, SRAM, (3D-)NAND, MRAM, PCRAM, ReRAM and emerging memory technologies
  • CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
  • RF / analog / digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
  • Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
  • Packaging technologies & System-in-Package (SiP), including through-silicon vias (TSVs), power & thermal management, inter-chip communication, 3D-system integration, as well as yield & test issues
  • Photonics Technology & ‘Beyond CMOS’ devices

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

  • Digital circuits, processors and architectures, including circuits and techniques for standalone and embedded processors
  • Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
  • Frequency generation and clock circuits for high-speed digital and mixed-signal applications
  • Analog and mixed-signal circuits, including amplifiers, filters and data converters
  • Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
  • Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
  • Power conversion circuits, including battery management, voltage regulation, and energy harvesting
  • Imagers, displays, sensors, VLSI circuits & systems for biomedical, healthcare and wearable applications

Joint Technology & Circuits focus sessions feature invited and contributed papers highlighting innovations and advances in the following areas of joint interest:

  • IoT /ULP (Internet of Things / Ultra Low Power) devices: Advanced CMOS processes for ULP, design enablement, design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
  • New Computing: Artificial intelligence, ‘beyond von Neumann’ computing, machine learning, neuromorphic & in-memory / in-sensor computing
  • 2D MOSFETs / New concepts for channel & gate materials: Graphene, MoS2, α-Si / poly-Si or flexible organic materials for ‘More than Moore’ devices
  • Emerging memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, and MRAM, Memristor, 3D Xpoint memory technologies
  • Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
  • 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and applications

Best Student Paper Award
Awards for best student paper at each Symposia are chosen based on the quality of the papers and presentations. The recipients will receive a monetary award, travel cost support and a certificate at the opening session of the 2018 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

Sponsoring Organizations
The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society.

Further Information, Registration and Official Call for Papers
Visit: http://www.vlsisymposium.org.

Toshiba Corporation’s (TOKYO: 6502) Storage & Electronic Devices Solutions Company today announced the launch of JEDEC e∙MMCTM Version 5.1[1] compliant embedded NAND flash memory products supporting AEC-Q100 Grade2 [2] requirements. The line-up offers densities of 8GB, 16GB, 32GB and 64GB. Sample shipments start from today with mass production scheduled for the second quarter (April to June) of 2017.

The new products integrate NAND chips fabricated with 15nm process technology with a controller to manage basic control functions for NAND applications in a single package. As a complement to Toshiba’s previous product group of e∙MMC, which deliver the operating temperature range of -40 to +85°C required by car infotainment applications, the new products support applications such as instrument clusters that require e∙MMC storage solutions to operate at higher temperatures up to +105°C.

In the automotive market, demand for NAND flash memory is continuing to grow alongside advances in car infotainment, ADAS [3] and autonomous driving systems. Toshiba is meeting this demand by reinforcing its line-up of high performance and high density memory products and will continue to take leadership in the market.

Toshiba is also developing automotive UFS [4] products that support AEC-Q100.

Amkor Technology, Inc. (Nasdaq: AMKR) today announced completion of product qualification for its innovative new Silicon Wafer Integrated Fan-Out Technology (SWIFT). SWIFT is designed to handle the demanding requirements of today’s advanced mobile, networking and system-in-package (SiP) applications.

With its fine-feature photolithography and thin film dielectrics, SWIFT bridges the gap between through silicon via (TSV) and traditional wafer level fan-out (WLFO) packages. Compared to laminate-based substrate technologies, SWIFT offers dramatic improvements in form factor, signal integrity, power distribution and thermal performance. SWIFT incorporates an “RDL first” process that allows SWIFT wafers to be built and yielded ahead of the assembly process – accelerating production cycles and optimizing overall assembly yield.

“The semiconductor industry requires much higher levels of integration in a significantly reduced form factor,” said Ron Huemoeller, Amkor’s corporate vice president, Research & Development. “Completing the product qualification stage of SWIFT is an important milestone. We achieved success by leveraging our significant fan-out development experience and using our existing cutting-edge equipment. Our package and board-level reliability results demonstrate that SWIFT is ready for sampling by customers.”

SWIFT was named the “Device of the Year” at the 3D InCites Awards ceremony earlier this year. It was recognized for being “uniquely developed to deliver a high yielding, high-performance package with the thinnest profile in the industry.” SWIFT was also noted for its ability to deliver 2µm line/space lithography (with up to four layers of RDL) and a very dense network of memory interface vias at a very competitive price.

SWIFT is targeted for production in the second half of 2017 at K5, Amkor’s manufacturing, research and development center in Incheon, South Korea.

Scientists often discover interesting things without completely understanding how they work. That has been the case with an experimental memory technology in which temperature and voltage work together to create the conditions for data storage. But precisely how was unknown.

But when a Stanford team found a way to untangle the chip’s energy and heat requirements, their tentative findings revealed a pleasant surprise: The process may be more energy efficient than was previously supposed. That’s good news for next-generation mobile devices whose batteries would last longer if they were powering lower energy chips.

The group that made this discovery, led by Stanford electrical engineer H.-S. Philip Wong, is presenting the paper when the IEEE International Electron Devices Meeting (IEDM) brings leading researchers to San Francisco Dec. 5.

The new technology the team investigated is called resistive random-access memory, or RRAM for short. RRAM is based on a new type of semiconductor material that forms digital zeros and ones by resisting or permitting the flow of electrons. RRAM has the potential to do things that aren’t possible with silicon: for instance, being layered on top of computer transistors in new three-dimensional, high-rise chips that would be faster and more energy efficient than current electronics, which is ideal for smartphones and other mobile devices where energy efficiency is a vital feature.

But while engineers can observe that RRAM does store data, they don’t know exactly how these new materials work. “We need much more precise information about the fundamental behavior of RRAM before we can hope to produce reliable devices,” Wong said.

Jolting memory

So to help engineers understand some of the unknowns, Wong’s team built a tool to measure the basic forces that make RRAM chips work.

Graduate student Zizhen Jiang of the Stanford team explained the basics: RRAM materials are insulators, which normally do not allow electricity to flow, she said. But under certain circumstances, insulators can be induced to let electrons flow. Past research had shown how: Jolting RRAM materials with an electric field causes a pathway to form that permitted electron flows. This pathway is called a filament. To break the filament, researchers apply another jolt and the material becomes an insulator again. So each jolt switched the RRAM from zero to one or back, which is what makes the material useful for data storage.

But electricity is not the only force at play in RRAM switching. Pumping electrons into any material raises its temperature. That’s the principle behind electric stoves. In the case of RRAM, it was the elevated temperature caused by introducing voltage that induced filaments to form or break. The question was what voltage-induced temperature was needed to cause the switching. No one knew.

Before the new Stanford study researchers thought short bursts of voltage, sufficient to generate temperatures of about 1,160 degrees Fahrenheit – hot enough to melt aluminum – was the switching point. But those were estimates because there was no way to measure the heat generated by an electric jolt.

“In order to begin to answer our questions, we had to decouple the effects of voltage and temperature on filament formation,” said Ziwen Wang, another graduate student on the team.

Dissecting the heat needs

Essentially, the Stanford researchers had to heat the RRAM material without using an electric field. So they put an RRAM chip on a micro thermal stage (MTS) device – a sophisticated hot plate capable of generating a wide range of temperatures inside the material. Of course the objective was not merely to heat the material, but also to measure how filaments formed. Here they took advantage of the fact that RRAM materials are insulators in their natural state. That makes them digital zeros. As soon as a filament formed electrons would flow. The digital zero would become a digital one, which the researchers could detect.

Using this experimental model, the team put RRAM chips on the burner and cranked up the heat, starting at about 80 F – roughly the temperature of a warm room – all the way up to 1,520 F, hot enough to melt a silver coin. Heating the RRAM to various temperatures in between these extremes, the researchers measured precisely if and how RRAM switched from its native zero to a digital one.

To their pleasant surprise, the researchers observed that filaments could form more efficiently at ambient temperatures between 80 F and 260 F, which is hotter than boiling water – contrary to prior expectation that hotter was better.

If confirmed by subsequent research, this would be good news because in a working chip the switching temperature would be created by the voltage and duration of the electric jolt. Efficient switching at lower temperatures would require less electricity and make RRAM more energy efficient and extend battery life when used as the memory in mobile devices.

Much work remains to be done to make RRAM memory practical but this research provides the test bed to vary conditions systematically instead of relying on hit-and-miss hunches.

“Now we can use voltage and temperature as design inputs in a predictive manner and that is going to enable us to design a better memory device,” Wang said.

Henry Chen, a Stanford alumnus who earned his PhD in Wang’s lab, gave this research a big assist and was a co-author on the paper. Chen, now with the Chinese memory chip-manufacturing firm GigaDevices Semiconductor Inc., helped develop the concepts and instruments that enabled the researchers to make the measurements being reported at IEDM.

Leti CEO Marie Semeria today delivered a sweeping, optimistic assessment of a rapidly evolving world where “hyperconnectivity” and the Internet of Things – guided by a “human-centered research approach and symbiotic development strategies” – herald profound changes in the way individuals relate to each other and to the physical world.

Her keynote presentation during the opening session of IEDM 2016, one of the high-tech industry’s most prestigious annual events, was based on her invited paper, “Symbiotic Low-Power, Smart and Secure Technologies in the Age of Hyperconnectivity”.

Marie Semeria, Leti CEO

Marie Semeria, Leti CEO

Semeria presented a comprehensive view of ubiquitous connectivity’s vast potential to bring positive change for individuals, society, companies and governments. She envisions a world in which a human-centered research approach combined with symbiotic development strategies “along different technological axes will foster key innovations that address societal challenges with strong impact.”

IoT at ‘Epicenter of the Revolution’

“The vertiginous pace of technological progress has made civilization enter the age of hyperconnectivity, dramatically changing the way people live, interact, share information, work, travel, take care of their health (and) purchase goods,” she notes. “Enabled by the convergence of miniaturization, wireless connectivity, increased data-storage capacity and data analytics, the Internet of Things (IoT) has become the epicenter of a profound social, business and political revolution.”

The IoT, with billions of easy-access and low-cost connected devices, “has transformed the world into a truly global village, enabling people and machines to interact in a symbiotic way – anytime, anywhere – with both the physical and cyber worlds,” she notes. “A new economy has emerged, as new product-as-a-service business models have been enabled by smart, connected products, creating substitutes for product ownership.”

In R&D strategies where technologies are developed symbiotically, the technologies’ associated innovation potential strongly increases. “Leti masters hardware and software technologies that gather, filter, process, store, transfer and analyze information in an efficient way. What is crucial today is not to consider these technologies as independent from one another,” Semeria says.

In her paper, Semeria also addresses the many global challenges that predate the hyperconnectivity era, such as climate change, poverty, diminishing natural resources and pollution, and the major challenges that rapid technological advancements have enabled. These include the negative side effects of cyber-technologies, ranging from “digital addiction” of some young people to cyber attacks on systems and threats to personal data and privacy.

Security Is a Crucial Component

“The hyperconnected society presents challenges which will require collective learning and adaptation, by both the main actors and the users, to develop the literacy and regulatory frameworks that will recreate and sustain the right balance between accountability and freedom for all agents, people and corporations,” Semeria says.

“Hypersecurity is a crucial component needed to counteract the surge in cyber attacks, which affect our modern societies, critically dependent on cyber-infrastructures (banking, communication, business, etc.). Security and unobtrusive surveillance technologies are being developed to provide and maintain peaceful everyday lives.”

Citizen Concerns

Data breaches and unapproved use of private information have raised widespread concerns about privacy. “Information is sometimes exchanged for commercial or national security purposes, leading citizens to perceive a loss of control, freedom and privacy,” Semeria notes. “The hyperconnected society presents challenges which will require collective learning and adaptation, by both the main actors and the users, to develop the literacy and regulatory frameworks that will recreate and sustain the right balance between accountability and freedom for all agents, people and corporations.”

The hyperconnectivity value chain, which includes sensing, communication, computing and storage, energy harvesting, security and services, depends on key building blocks ranging from sensors to communication networks, including 5G, which is expected to provide a full-scale IoT that offers immersive services regardless of geography and time zones. Leti has strategic programs in each of the value chain fields and participates in the core of Europe’s 5G innovation initiatives.

A Major Role for RTOs

Semeria points out that research and technology organizations (RTOs) like Leti are playing a vital role in the twin pursuits of making the IoT and networks both more efficient and more secure. In the 50 years since its founding, Leti has shaped its strategy to tackle the main challenges presented by the evolution of society and the economic and industrial sectors.

RTOs “are ideally positioned to address and harmonize growing individual, private needs and global societal challenges, because they are neither embedded public administration organizations nor industrial corporate labs guided by private interests,” Semeria notes.

Biomimicry’s Natural Role

In addition to partnerships with companies on specific solutions to make them more competitive and its participation in EU research programs with broader strategic impact, Leti pursues multiple lines of inquiry with an eye on technologies for the future. These include bio-mimicry, which aims to adapt for commercial use the sensing efficiencies that insects have developed over billions of years of evolution.

“Bio-inspired ideas, which are currently experiencing an exponential growth, represent an area with very high hopes,” Semeria says.

The Electronic Components and Systems for European Leadership (ECSEL) Joint Undertaking announced the Lab4MEMS project as the winner of its 2016 Innovation Award during the European Nanoelectronics Forum, in Rome, Italy.

At its launch in January 2014, Lab4MEMS was identified as a Key Enabling Technology Pilot-Line project for next-generation Micro-Electro-Mechanical Systems (MEMS) devices augmented with advanced technologies such as piezoelectric or magnetic materials and 3D packaging to enhance the next generation of smart sensors, actuators, micro-pumps, and energy harvesters. These technologies were recognized as important contributors to future data-storage, printing, healthcare, automotive, industrial-control, and smart-building applications, as well as consumer applications such as smartphones and navigation devices.

In accepting the award, Roberto Zafalon, General Project Coordinator of Lab4MEMS and the European Programs Manager in R&D and Public Affairs for STMicroelectronics Italy said, “The ECSEL Innovation Award highlights the excellent results the Lab4MEMS team achieved through the project’s execution and the high impact of its successes. In particular, Lab4MEMS developed innovative MEMS solutions with advanced piezoelectric and magnetic materials, including advanced 3D Packaging technologies.”

In coordinating the €28m[1], 36-month Lab4MEMS project, ST led the team of twenty partners, which included universities, research institutions, and technology businesses across ten European countries. ST’s MEMS facilities in Italy and Malta contributed their complete set of manufacturing competencies for next-generation devices, spanning design and fabrication to test and packaging to the project.

Lab4MEMS’ devices, technologies, and application improvements emphasized:

  • Micro-actuators, micro-pumps, sensors, and energy scavengers integrated on silicon-based MEMS using piezoelectric thin-films (PZT), for applications in Data Storage, Printing, Health Care, Automotive, Energy Scavenging, and Autofocus Lenses.
  • Magnetic-field sensors, for applications in consumer applications such as GPS positioning, indoor navigation, and mobile phones.
  • Advanced packaging technologies and vertical interconnections, including flip chip, Through Silicon Via (TSV) or Through Mold Via (TMV) for full 3D integration, which could be used in Consumer and Healthcare applications such as body-area sensors and remote monitoring.

All of these successes contributed to the Lab4MEMS project and are available to benefit the contributors. These participants were Politecnico di Torino (Italy); Fondazione Istituto Italiano di Tecnologia (Italy); Politecnico di Milano (Italy); Consorzio Nazionale Interuniversitario per la Nanoelettronica (Italy); Commissariat à l’Energie Atomique et aux énergies alternatives (France); SERMA Technologies SA (France); STMicroelectronics Ltd. (Malta); Universita ta Malta (Malta); Solmates BV (Netherlands); Cavendish Kinetics BV (Netherlands); Okmetic OYJ (Finland); VTT (Finland); Picosun OY (Finland); KLA-Tencor ICOS (Belgium); Universitatea Politehnica din Bucuresti (Romania); Instytut Technologii Elektronowej (Poland); Stiftelsen SINTEF (Norway); Sonitor Technologies AS (Norway); BESI GmbH (Austria).

Synopsys, Inc. (Nasdaq:  SNPS) today announced it expanded its test and yield analysis solution targeting FinFET-specific defects to enable higher quality testing, repair, diagnostics and yield analysis of advanced 7-nanometer (nm) SoCs. To improve defect coverage, Synopsys has been collaborating with several semiconductor companies to advance testing and diagnostics methods for logic, memory and high-speed mixed-signal circuits targeted for manufacture with 7nm processes. These collaborations are enabling rapid deployment of new functionality within Synopsys’ synthesis-based test solution, featuring TetraMAX II ATPG, DesignWare STAR Memory System, and DesignWare STAR Hierarchical System.

Leading semiconductor companies ramping up design capabilities for emerging 7nm processes are facing increasing test quality and yield management challenges. To address these challenges, Synopsys’ test solution delivers several innovative technologies that target defects occurring more frequently at emerging process nodes. For logic circuits, new modeling techniques, such as resistance sweeping, improve the ability of slack-based cell-aware tests to detect defects such as intra-cell partial bridges that are more prevalent with advanced FinFET processes. For embedded memory test and repair, the STAR Memory System solution incorporates custom algorithms based on silicon learning at the industry’s top silicon foundries to detect and repair defects exemplified by resistive fin shorts, fin opens and gate-fin shorts. Furthermore, the DesignWare STAR Hierarchical System enables high coverage manufacturing and characterization test patterns for the 7nm DesignWare PHY IP to be efficiently applied through the SoC hierarchy.

To accelerate diagnosis of 7nm yield issues, defect isolation to specific areas within design cells is possible through new support of cell-aware descriptions in the database shared between TetraMAX II ATPG and Yield Explorer solutions. The combination of test and diagnostic advances increase 7nm defect detection and speed up failure analysis and yield ramp in production manufacturing environments.

“The growing complexity and process variation found with advanced 7nm FinFET processes requires improved test and yield technologies,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys.  “Our IP design teams are leveraging TetraMAX ATPG as well as STAR Memory System and STAR Hierarchical System test, repair and diagnostic solutions to help multiple customers designing with 7nm IP improve their product quality and yield, while accelerating their time to market.”

“As a leading provider of comprehensive test and yield solutions, Synopsys is committed to helping designers meet their growing challenges of higher quality and faster yield ramp,” said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. “Through our on-going collaborations with leading semiconductor companies worldwide, we are delivering innovative solutions to address the specific requirements for advanced FinFET processes. These innovations will enable our customers to rapidly adopt 7nm technologies to meet their goals for high-performance SoC products.”

Researchers at the Fraunhofer Institute for Solar Energy Systems ISE together with the Austrian company EV Group (EVG) have successfully manufactured a silicon-based multi-junction solar cell with two contacts and an efficiency exceeding the theoretical limit of silicon solar cells. For this achievement, the researchers used a “direct wafer bonding” process to transfer a few micrometers of III-V semiconductor material to silicon, a well-known process in the microelectronics industry. After plasma activation, the subcell surfaces are bonded together in vacuum by applying pressure. The atoms on the surface of the III-V subcell form bonds with the silicon atoms, creating a monolithic device. The efficiency achieved by the researchers presents a first-time result for this type of fully integrated silicon-based multi-junction solar cell. The complexity of its inner structure is not evident from its outer appearance: the cell has a simple front and rear contact just as a conventional silicon solar cell and therefore can be integrated into photovoltaic modules in the same manner.

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

“We are working on methods to surpass the theoretical limits of silicon solar cells,” says Dr. Frank Dimroth, department head at Fraunhofer ISE. “It is our long-standing experience with silicon and III-V technologies that has enabled us to reach this milestone today.” A conversion efficiency of 30.2 percent for the III-V / Si multi-junction solar cell of 4 cm² was measured at Fraunhofer ISE’s calibration laboratory. In comparison, the highest efficiency measured to date for a pure silicon solar cell is 26.3 percent, and the theoretical efficiency limit is 29.4 percent.

The III-V / Si multi-junction solar cell consists of a sequence of subcells stacked on top of each other. So-called “tunnel diodes” internally connect the three subcells made of gallium-indium-phosphide (GaInP), gallium-arsenide (GaAs) and silicon (Si), which span the absorption range of the sun’s spectrum. The GaInP top cell absorbs radiation between 300 and 670 nm. The middle GaAs subcell absorbs radiation between 500 and 890 nm and the bottom Si subcell between 650 and 1180 nm, respectively. The III-V layers are first epitaxially deposited on a GaAs substrate and then bonded to a silicon solar cell structure. Subsequently the GaAs substrate is removed, and a front and rear contact as well as an antireflection coating are applied.

“Key to the success was to find a manufacturing process for silicon solar cells that produces a smooth and highly doped surface which is suitable for wafer bonding as well as accounts for the different needs of silicon and the applied III-V semiconductors,” explains Dr. Jan Benick, team leader at Fraunhofer ISE.

“In developing the process, we relied on our decades of research experience in the development of highest efficiency silicon solar cells.” Institute Director Prof. Eicke Weber expresses his delight: “I am pleased that Fraunhofer ISE has so convincingly succeeded in breaking through the glass ceiling of 30 percent efficiency with its fully integrated silicon-based solar cell with two contacts. With this achievement, we have opened the door for further efficiency improvements for cells based on the long-proven silicon material.”

“The III-V / Si multi-junction solar cell is an impressive demonstration of the possibilities of our ComBond® cluster for resistance-free bonding of different semiconductors without the use of adhesives,” says Markus Wimplinger, Corporate Technology Development and IP Director at EV Group. “Since 2012, we have been working closely with Fraunhofer ISE on this development and today are proud of our team’s excellent achievements.” The direct wafer-bonding process is already used in the microelectronics industry to manufacture computer chips.

On the way to the industrial manufacturing of III-V / Si multi-junction solar cells, the costs of the III-V epitaxy and the connecting technology with silicon must be reduced. There are still great challenges to overcome in this area, which the Fraunhofer ISE researchers intend to solve through future investigations. Fraunhofer ISE’s new Center for High Efficiency Solar Cells, presently being constructed in Freiburg, will provide them with the perfect setting for developing next-generation III-V and silicon solar cell technologies. The ultimate objective is to make high efficiency solar PV modules with efficiencies of over 30 percent possible in the future.

The young researcher Dr. Romain Cariou carried out research on this project at Fraunhofer ISE with the support of a Marie Curie Postdoctoral Fellowship. Funding was provided by the EU project HISTORIC. The work at EVG was supported by the Austrian Ministry for Technology.

Leti, an institute of CEA Tech, and PYXALIS, a French SME specializing in high-performance image sensors, today announced a new technology that lowers readout noise for image sensors down to 0.5 electron noise and dramatically improves low-light image sensing capabilities.

The new technology, called Owly-eyed, is based on a patented electrical architecture of the pixel readout that can be integrated in image sensors. Designed to meet growing demand for more sensitive CMOS image sensors, it has been adapted for PYXALIS, which will offer it in its next-generation image sensors.

“In this common lab with PYXALIS, we’ve developed a low-noise image technology that provides state-of-the-art advanced imaging for next-generation applications in a wide range of markets and industries,” said Marie Semeria, Leti’s CEO. “This CMOS-based device, which can be adapted for multiple uses, is another strong example of how Leti’s broad technology innovations make our partners more competitive in their industries.”

“Leti’s Owly-eyed technology is a major improvement in low-noise imaging,” said PYXALIS CEO Philippe Rommeveaux. “Combined with our capacity to offer advanced sensors with high digital integration and high dynamic range, it will allow us to establish a new performance standard in image sensors that address the growing demand for low-light applications in the surveillance, biomedical, science, defense and aerospace markets.”

In the Owly-eyed technology demonstrator, a sub-0.5 e−rms temporal read noise has been achieved on a VGA format CMOS image sensor implemented in a standard CMOS process. The low-noise performance is achieved exclusively through circuit optimization without any process refinements.

Leti also is developing many other technologies for innovative sensors and image processing that perform in low-power and low-latency operating modes.

Leti will demonstrate the Owly-eyed technology and a set of advanced smart-image-processing solutions at Vision 2016, Nov. 8-10 in Stuttgart, Germany, inHall 1, booth H01. The PYXALIS team will be available in Hall 1, booth D41.