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Gallium nitride (GaN) has emerged as one of the most important and widely used semiconducting materials. Its optoelectronic and mechanical properties make it ideal for a variety of applications, including light-emitting diodes (LEDs), high-temperature transistors, sensors and biocompatible electronic implants in humans.

In 2014, three Japanese scientists won the Nobel Prize in physics for discovering GaN’s critical role in generating blue LED light, which is required, in combination with red and green light, to produce white LED light sources.

Now, four Lehigh engineers have reported a previously unknown property for GaN: Its wear resistance approaches that of diamonds and promises to open up applications in touch screens, space vehicles and radio-frequency microelectromechanical systems (RF MEMS), all of which require high-speed, high-vibration technology.

The researchers reported their findings in August in Applied Physics Letters (APL) in an article titled “Ultralow wear of gallium nitride.” The article’s authors are Guosong Zeng, a Ph.D. candidate in mechanical engineering; Nelson Tansu, Daniel E. ’39 and Patricia M. Smith Endowed Chair Professor in the Electrical and Computer Engineering department, and Director of the Center for Photonics and Nanoelectronics (CPN); Brandon A. Krick, assistant professor of mechanical engineering and mechanics; and Chee-Keong Tan ’16 Ph.D., now assistant professor of electrical and computer engineering at Clarkson University.

GaN’s electronic and optical properties have been studied extensively for several decades, said Zeng, the lead author of the APL article, but virtually no studies have been done of its tribological properties, that is, its resistance to the mechanical wear imposed by reciprocated sliding.

“Our group is the first to investigate the wear performance of GaN,” said Zeng. “We have found that its wear rate approaches that of diamonds, the hardest material known.”

Wear rate is expressed in negative cubic millimeters of Newton meters (Nm). The rate for chalk, which has virtually no wear resistance, is on the order of 10 2 mm3/Nm, while that of diamonds is between 10-9 and 10-10, making diamonds eight orders of magnitude more wear resistant than chalk. The rate for GaN ranges from 10¬-7 to 10-9, approaching the wear resistance of diamonds and three to five orders of magnitude more wear resistant than silicon (10-4).

The Lehigh researchers measured the wear rate and friction coefficients of GaN using a custom microtribometer to perform dry sliding wear experiments. They were surprised by the results.

“When performing wear measurements of unknown materials,” they wrote in APL, “we typically slide for 1,000 cycles, then measure the wear scars; [these] experiments had to be increased to 30,000 reciprocating cycles to be measurable with our optical profilometer.

“The large range in wear rates (about two orders of magnitude)…can provide insight into the wear mechanisms of GaN.”

That range in wear resistance, the researchers said, is caused by several factors, including environment, crystallographic direction and, especially, humidity.

“The first time we observed the ultralow wear rate of GaN was in winter,” said Zeng. “These results could not be replicated in summer, when the material’s wear rate increased by two orders of magnitude.”

To determine how the higher summer humidity was affecting GaN’s wear performance, the researchers put their tribometer in a glove box that can be backfilled with either nitrogen or humid air.

“We observed that as we increased the humidity inside the glove box, we also increased the wear rate of GaN,” said Zeng.

Zeng gave a presentation about the Lehigh project in October at the International Workshop on Nitride Semiconductors (IWN 2016) in Orlando, Florida. The session at which he spoke was titled “Wear of Nitride Materials and Properties of GaN-based structures.” Zeng was one of seven presenters at the session and the only one to discuss the wear properties of GaN and other III-Nitride materials.

Tansu, who has studied GaN for more than a decade, and Krick, a tribology expert, became curious about GaN’s wear performance several years ago when they discussed their research projects after a Lehigh faculty meeting.

“Nelson asked me if anyone had ever investigated the friction and wear properties of gallium nitride,” said Krick, “and I said I didn’t know. We checked later and found a wide-open field.”

Tansu said the group’s discovery of GaN’s hardness and wear performance could have a dramatic effect on the electronic and digital device industries. In a device such as a smartphone, he said, the electronic components are housed underneath a protective coating of glass or sapphire. This poses potential compatibility problems which could be avoided by using GaN.

“The wear resistance of GaN,” said Tansu, “gives us the opportunity to replace the multiple layers in a typical semiconductor device with one layer made of a material that has excellent optical and electrical properties and is wear-resistant as well.

“Using GaN, you can build an entire device in a platform without multiple layers of technologies. You can integrate electronics, light sensors and light emitters and still have a mechanically robust device. This will open up a new paradigm for designing devices. And because GaN can be made very thin and still strong, it will accelerate the move to flexible electronics.”

In addition to its unexpectedly good wear performance, said Zeng, GaN also has a favorable radiation hardness, which is an important property for the solar cells that power space vehicles. In outer space, these solar cells encounter large quantities of very fine cosmic dust, along with x-rays and gamma rays, and thus require a wear-resistant coating, which in turn needs to be compatible with the cell’s electronic circuitry. GaN provides the necessary hardness without introducing compatibility issues with the circuitry.

The Lehigh group has begun collaborating with Bruce E. Koel, a surface chemistry expert and professor of chemical and biological engineering at Princeton University, to gain a better understanding of the interaction of GaN and water under contact. Koel was formerly a chemistry professor and vice president for research and graduate studies at Lehigh.

To determine the evolution of wear with GaN, the group has subjected GaN to stresses by running slide tests in which the slide distance and the corresponding number of cycles are varied. The group then uses an x-ray photoelectron spectrometer (XPS), which can identify the elemental composition of the first 12 nanometers of a surface, to scan the unworn surface of the GaN, the scar created by the slide machine, and the wear particles deposited by the slide machine on either side of the scar.

The group plans next to use aberration-corrected transmission electron microscopy to examine the lattice of atoms beneath the scar. Meanwhile, they will simulate a test in which the lattice is strained with water in order to observe the variations caused by deforming energy.

“This is a very new experiment,” said Zeng. “It will enable us to see dynamic surface chemistry by watching the chemical reaction that results when you apply shear, tensile or compressive pressure to the surface of GaN.”

A newly-developed form of transistor opens up a range of new electronic applications including wearable or implantable devices by drastically reducing the amount of power used. Devices based on this type of ultralow power transistor, developed by engineers at the University of Cambridge, could function for months or even years without a battery by ‘scavenging’ energy from their environment.

Using a similar principle to a computer in sleep mode, the new transistor harnesses a tiny ‘leakage’ of electrical current, known as a near-off-state current, for its operations. This leak, like water dripping from a faulty tap, is a characteristic of all transistors, but this is the first time that it has been effectively captured and used functionally. The results, reported in the journal Science, open up new avenues for system design for the Internet of Things, in which most of the things we interact with every day are connected to the Internet.

The transistors can be produced at low temperatures and can be printed on almost any material, from glass and plastic to polyester and paper. They are based on a unique geometry which uses a ‘non-desirable’ characteristic, namely the point of contact between the metal and semiconducting components of a transistor, a so-called ‘Schottky barrier.’

“We’re challenging conventional perception of how a transistor should be,” said Professor Arokia Nathan of Cambridge’s Department of Engineering, the paper’s co-author. “We’ve found that these Schottky barriers, which most engineers try to avoid, actually have the ideal characteristics for the type of ultralow power applications we’re looking at, such as wearable or implantable electronics for health monitoring.”

The new design gets around one of the main issues preventing the development of ultralow power transistors, namely the ability to produce them at very small sizes. As transistors get smaller, their two electrodes start to influence the behaviour of one another, and the voltages spread, meaning that below a certain size, transistors fail to function as desired. By changing the design of the transistors, the Cambridge researchers were able to use the Schottky barriers to keep the electrodes independent from one another, so that the transistors can be scaled down to very small geometries.

The design also achieves a very high level of gain, or signal amplification. The transistor’s operating voltage is less than a volt, with power consumption below a billionth of a watt. This ultralow power consumption makes them most suitable for applications where function is more important than speed, which is the essence of the Internet of Things.

“If we were to draw energy from a typical AA battery based on this design, it would last for a billion years,” said Dr Sungsik Lee, the paper’s first author, also from the Department of Engineering. “Using the Schottky barrier allows us to keep the electrodes from interfering with each other in order to amplify the amplitude of the signal even at the state where the transistor is almost switched off.”

“This will bring about a new design model for ultralow power sensor interfaces and analogue signal processing in wearable and implantable devices, all of which are critical for the Internet of Things,” said Nathan.

“This is an ingenious transistor concept,” said Professor Gehan Amaratunga, Head of the Electronics, Power and Energy Conversion Group at Cambridge’s Engineering Department. “This type of ultra-low power operation is a pre-requisite for many of the new ubiquitous electronics applications, where what matters is function – in essence ‘intelligence’ – without the demand for speed. In such applications the possibility of having totally autonomous electronics now becomes a possibility. The system can rely on harvesting background energy from the environment for very long term operation, which is akin to organisms such as bacteria in biology.”

A new design for solar cells that uses inexpensive, commonly available materials could rival and even outperform conventional cells made of silicon.

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

Writing in the Oct. 21 edition of Science, researchers from Stanford and Oxford describe using tin and other abundant elements to create novel forms of perovskite – a photovoltaic crystalline material that’s thinner, more flexible and easier to manufacture than silicon crystals.

“Perovskite semiconductors have shown great promise for making high-efficiency solar cells at low cost,” said study co-author Michael McGehee, a professor of materials science and engineering at Stanford. “We have designed a robust, all-perovskite device that converts sunlight into electricity with an efficiency of 20.3 percent, a rate comparable to silicon solar cells on the market today.”

The new device consists of two perovskite solar cells stacked in tandem. Each cell is printed on glass, but the same technology could be used to print the cells on plastic, McGehee added.

“The all-perovskite tandem cells we have demonstrated clearly outline a roadmap for thin-film solar cells to deliver over 30 percent efficiency,” said co-author Henry Snaith, a professor of physics at Oxford. “This is just the beginning.”

Tandem technology

Previous studies showed that adding a layer of perovskite can improve the efficiency of silicon solar cells. But a tandem device consisting of two all-perovskite cells would be cheaper and less energy-intensive to build, the authors said.

“A silicon solar panel begins by converting silica rock into silicon crystals through a process that involves temperatures above 3,000 degrees Fahrenheit (1,600 degrees Celsius),” said co-lead author Tomas Leijtens, a postdoctoral scholar at Stanford. “Perovskite cells can be processed in a laboratory from common materials like lead, tin and bromine, then printed on glass at room temperature.”

But building an all-perovskite tandem device has been a difficult challenge. The main problem is creating stable perovskite materials capable of capturing enough energy from the sun to produce a decent voltage.

A typical perovskite cell harvests photons from the visible part of the solar spectrum. Higher-energy photons can cause electrons in the perovskite crystal to jump across an “energy gap” and create an electric current.

A solar cell with a small energy gap can absorb most photons but produces a very low voltage. A cell with a larger energy gap generates a higher voltage, but lower-energy photons pass right through it.

An efficient tandem device would consist of two ideally matched cells, said co-lead author Giles Eperon, an Oxford postdoctoral scholar currently at the University of Washington.

“The cell with the larger energy gap would absorb higher-energy photons and generate an additional voltage,” Eperon said. “The cell with the smaller energy gap can harvest photons that aren’t collected by the first cell and still produce a voltage.”

The smaller gap has proven to be the bigger challenge for scientists. Working together, Eperon and Leijtens used a unique combination of tin, lead, cesium, iodine and organic materials to create an efficient cell with a small energy gap.

“We developed a novel perovskite that absorbs lower-energy infrared light and delivers a 14.8 percent conversion efficiency,” Eperon said. “We then combined it with a perovskite cell composed of similar materials but with a larger energy gap.”

The result: A tandem device consisting of two perovskite cells with a combined efficiency of 20.3 percent.

“There are thousands of possible compounds for perovskites,” Leijtens added, “but this one works very well, quite a bit better than anything before it.”

Seeking stability

One concern with perovskites is stability. Rooftop solar panels made of silicon typically last 25 years or more. But some perovskites degrade quickly when exposed to moisture or light. In previous experiments, perovskites made with tin were found to be particularly unstable.

To assess stability, the research team subjected both experimental cells to temperatures of 212 degrees Fahrenheit (100 degrees Celsius) for four days.

“Crucially, we found that our cells exhibit excellent thermal and atmospheric stability, unprecedented for tin-based perovskites,” the authors wrote.

“The efficiency of our tandem device is already far in excess of the best tandem solar cells made with other low-cost semiconductors, such as organic small molecules and microcrystalline silicon,” McGehee said. “Those who see the potential realize that these results are amazing.”

The next step is to optimize the composition of the materials to absorb more light and generate an even higher current, Snaith said.

“The versatility of perovskites, the low cost of materials and manufacturing, now coupled with the potential to achieve very high efficiencies, will be transformative to the photovoltaic industry once manufacturability and acceptable stability are also proven,” he said.

Researchers at Tokyo Institute of Technology in collaboration with the University of Cambridge have studied the interaction between microwave fields and electronic defect states inside the oxide layer of field-effect transistors at cryogenic temperatures. It has been found that the physics of such defect states are consistent with driven two-level systems possessing long coherence times, and that their induced dynamics can be coherently and independently controlled.

Due to the nature of this work, it is hoped that such results will contribute to the field of correlated electronic glassy dynamics in condensed matter physics; give a better understanding of charge noise effects in mesoscopic devices; and enable new studies for developing novel technologies in the important field of semiconductor-based quantum information processing.

(a) Schematic representation of the FET device used in this work. (b) Schematic diagram of the interaction between the trapped electron and the percolation pathways mediated by the MW field (top). Multilevel RTN events recorded in the FET current measured at 80 K (bottom). (c) Wideband CW microwave spectroscopy of the FET channel current performed at 4.2 K. Each narrow spike is a separate resonance that is resolved into a Fano or Lorentzian shape at higher resolution (inset). (d) Density of states (red), amplitude change (blue) and coherence times (inset) histograms. Credit: Nature Materials

(a) Schematic representation of the FET device used in this work. (b) Schematic diagram of the interaction between the trapped electron and the percolation pathways mediated by the MW field (top). Multilevel RTN events recorded in the FET current measured at 80 K (bottom). (c) Wideband CW microwave spectroscopy of the FET channel current performed at 4.2 K. Each narrow spike is a separate resonance that is resolved into a Fano or Lorentzian shape at higher resolution (inset). (d) Density of states (red), amplitude change (blue) and coherence times (inset) histograms. Credit: Nature Materials

Defect states acting as electron traps in oxide-semiconductor interfaces usually are sources of noise and tend to reduce the performance of nanoscale devices. Such defect states can modify the electrostatic environment experienced by conducting electrons, forcing them to percolate through nanowire-like pathways at low enough temperatures. This effectively allows a detection mechanism of the occupation of such trap sites by the current measured in the conduction channel. Such effect is normally observed as random telegraph noise (RTN), which corresponds to the incoherent emission and capture of electrons in the trap states, mediated by the thermal background.

Motivated by the big changes in the conductivity caused by RTN in field-effect transistors (FET), scientists at the Quantum Nanoelectronics Research Center, Institute of Innovative Research (Tokyo Tech), the Center for Advanced Photonics and Electronics (University of Cambridge), and Cavendish Laboratory (University of Cambridge) investigated possible mechanisms in which the occupation of defects states could be both observed and dynamically mediated by means of coherent microwave fields. Working at cryogenic temperatures, it was found that the dynamics of such trap states are consistent with two-level systems (TLS), in which the energy levels are discrete and only the two lowest are accessible within the energy of the excitation signal. A TLS can represent the basis for a quantum bit implementation.

From the microwave spectroscopic signature of the response of the FET used in this work, displaying a great number of high-quality factor resonances (Q > 10000), the extracted coherence times observed in this study are considerably longer, by almost three orders of magnitude, than other defect-based implementations of TLS. Performing single-pulse experiments gives the possibility to study the dynamics of the trapped electrons, which have been found not to depend on the chemistry of the dielectric used. And using a standard Ramsey protocol, coherent control was achieved. Furthermore, employing an optical master equation that captures the dynamics of the trapped electrons and a physical model based on linear response theory, it was possible to reproduce the experimental behavior observed in the experiments.

Furthermore, it was found that the defect states are relatively well protected against phonons, explaining the long decoherence times measured, and that the main source of back-action could be related to long-range Coulombic interactions with other charges. Finally, since each resonance can be addressed independently in frequency space, the wide distribution of long coherence times observed, and the quasi-uniform density of states measured, it is hoped that this work could motivate the possibility to use such systems as quantum memories or quantum bits in future quantum information processing implementations.

Samsung Electronics Co., Ltd. today announced that it has commenced mass production of System-on-Chip (SoC) products with 10-nanometer (nm) FinFET technology for which would make it first in the industry.

Following the successful mass production of the industry’s first FinFET mobile application processor (AP) in January, 2015, Samsung extends its leadership in delivering leading-edge process technology to the mass market with the latest offering.

“The industry’s first mass production of 10nm FinFET technology demonstrates our leadership in advanced process technology,” said Jong Shik Yoon, Executive Vice President, Head of Foundry Business at Samsung Electronics. “We will continue our efforts to innovate scaling technologies and provide differentiated total solutions to our customers.”

Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption. In order to overcome scaling limitations, cutting edge techniques such as triple-patterning to allow bi-directional routing are also used to retain design and routing flexibility from prior nodes.

Following the introduction of Samsung’s first-generation 10nm process (10LPE), its second generation process (10LPP) with performance boost is targeted for mass production in the second half of 2017. The company plans to continue its leadership with a variety of derivative processes to meet the needs of a wide range of applications.

Through close collaboration with customers and partners, Samsung also aims to cultivate a robust 10nm foundry ecosystem that includes reference flow verification, IPs and libraries.

Production level process design kits (PDK) and IP design kits are currently available for design starts.

SoCs with 10nm process technology will be used in digital devices launching early next year and are expected to become more widely available throughout 2017.

Peregrine Semiconductor Corp., founder of RF SOI (silicon on insulator), announces that the UltraCMOS PE42723 high linearity RF switch has won an ECN IMPACT Award in the market disruptor category. In addition, the PE42723 switch was named a finalist in the microwaves & RF category, and the PE29100 gallium nitride (GaN) field-effect transistor (FET) driver was recognized as a finalist in the power sources & conditioning devices category. Winners were announced today, Oct. 13, during the awards ceremony.

“For almost three decades, Peregrine has been on the cutting edge of delivering game-changing products to the electronics market,” says Kinana Hussain, Peregrine’s director of marketing. “It is truly an honor to be recognized with an ECN IMPACT Award, especially in the coveted market disruptor category. Products like the PE42723 enable the cable industry to deliver equipment that is fully compliant with today’s stringent communication standards.”

The ECN IMPACT Awards recognize the products and services that have the greatest impact on the electronic components industry. The market disruptor category highlights a product that forever changed the electronic engineering industry or a particular vertical within the industry.

The PE42723 is an RF switch that boasts the highest linearity specifications on the market today. An upgraded version of the successful PE42722, this new RF switch offers enhanced performance in a smaller package. Like its predecessor, the PE42723 exceeds the linearity requirements of the DOCSIS 3.1 cable industry standard and enables a dual upstream/downstream band architecture in the next generation cable customer premises equipment (CPE) devices.

The PE29100 is the world’s fastest GaN FET driver. Built on Peregrine’s UltraCMOS technology, this new GaN driver empowers design engineers to extract the full performance and speed advantages from GaN transistors. Designed to drive the gates of a high-side and a low-side GaN FET in a switching configuration, the PE29100 delivers the industry’s fastest switching speeds, shortest propagation delays and lowest rise and fall times to AC-DC converters, DC-DC converters, class D audio amplifiers and wireless-charging applications.

In the quest for faster and more powerful computers and consumer electronics, big advances come in small packages.

The high-performance, silicon-based transistors that control today’s electronic devices have been getting smaller and smaller, allowing those devices to perform faster while consuming less power.

But even silicon has its limits, so researchers at The University of Texas at Dallas and elsewhere are looking for better-performing alternatives.

In a new study published Oct. 7 in the journal Science, UT Dallas engineers and their colleagues describe a novel transistor made with a new combination of materials that is even smaller than the smallest possible silicon-based transistor.

“Silicon transistors are approaching their size limit,” said Dr. Moon Kim, professor of materials science and engineering at UT Dallas and an author of the study. “Our research provides new insight into the feasibility to go beyond the ultimate scaling limit of silicon-based transistor technology.”

The study authors also included Kim’s graduate student Qingxiao Wang, and collaborators at the University of California, Berkeley, Stanford University and the Lawrence Berkeley National Laboratory, which led the project. Researchers in California fabricated the transistor and performed theoretical simulations, while the UT Dallas team physically characterized the device using an atomic resolution electron microscope on campus.

As current flows through a transistor, the stream of electrons travels through a channel, like tap water flowing through a faucet out into a sink. A “gate” in the transistor controls the flow of electrons, shutting the flow off and on in a fraction of second.

“As of today, the best/smallest silicon transistor devices commercially available have a gate length larger than 10 nanometers,” said Kim, the Louis Beecherl Jr. Distinguished Professor in the Erik Jonsson School of Engineering and Computer Science. “The theoretical lower limit for silicon transistors is about 5 nanometers. The device we demonstrate in this article has a gate size of 1 nanometer, about one order of magnitude smaller. It should be possible to reduce the size of a computer chip significantly utilizing this configuration.”

One of the challenges in designing such small transistors is that electrons can randomly tunnel through a gate when the current is supposed to be shut off. Reducing this current leakage is a priority.

“The device we demonstrated shows more than two orders of magnitude reduction in leakage current compared to its silicon counterpart, which results in reduced power consumption,” Kim said. “What this means, for example, is that a cellphone with this technology built in would not have to be recharged as often.”

Instead of using silicon, the researchers built their prototype device with a class of semiconductor materials called transition metal dichalcogenides, or TMDs. Specifically, their experimental device structure used molybdenum disulfide for the channel material and a single-walled carbon nanotube for the gate.

Kim said there are many technical challenges before large-scale manufacturing of the new transistor is practical or even possible.

“Large-scale processing and manufacturing of TMD devices down to such small gate lengths will require future innovations,” he said.

INVECAS Inc., an IP, ASIC and embedded software solutions provider, and GLOBALFOUNDRIES today announced the availability of foundation IP for GLOBALFOUNDRIES’ 14nm FinFET technology. The silicon-proven IP from INVECAS is optimized for the performance, power, and area requirements of high-performance “all-the-time” applications such as high-end smartphones, networking, server, and graphics processors. This application-tailored library enables customers to rapidly develop high-performance and power-efficient systems.

INVECAS IP taps the benefits of FinFET to deliver more processing power in a smaller footprint for the most demanding applications. The comprehensive IP portfolio includes foundation IP such as general-purpose I/O (GPIO), memories, standard cell libraries, and a full set of interface and analog IP solutions.

“GLOBALFOUNDRIES’ 14LPP offers a silicon-proven solution for customers seeking to differentiate their products and accelerate time-to-volume of designs on complex technologies,” said Alain Mutricy, senior vice president of product management at GLOBALFOUNDRIES. “We further enhance our technology through early engagement with ecosystem partners like INVECAS, to ensure a robust infrastructure with a low-risk, silicon-proven, and efficient design strategy. Our strategic relationship with INVECAS provides our customers with the 14LPP performance and power optimized IP platforms to push their SoC designs to new levels and deliver the highest performance silicon for a broad set of applications.”

“INVECAS is dedicated to overcoming SoC design challenges with optimized IP and silicon realization services on GLOBALFOUNDRIES’ processes,” said Dasaradha Gude, chairman and CEO of INVECAS Inc. “By combining our proven system-level expertise with GLOBALFOUNDRIES’ advanced 14nm FinFET technology, we are uniquely positioned to provide complete solutions for the compute, communication, mobile, and automotive markets.”

INVECAS will showcase its silicon-proven IP solutions during GLOBALFOUNDRIES Technology Conference (GTC) on September 29 at the Sofitel Munich Bayerpost in Munich, Germany.

Toshiba America Electronic Components, Inc. (TAEC) has expanded its family of 24nm single-level cell (SLC) NAND flash memory solutions. The new 16 gigabit (Gb) BENAND is housed in an industry-standard 48-pin TSOP package, and offers a combination of high read/write performance, effective write endurance (using 8-bit BCH error correction code), and extended temperature operation. This makes it suitable for a wide variety of commercial and industrial applications.

The new addition rounds out Toshiba’s broad SLC product lineup, allowing designers to take advantage of the price/performance of advanced 24nm NAND flash SLC technology at densities from 1Gb to 128Gb. Based on a 4x4Gb die, 16Gb BENAND operates from a power supply of 2.7V to 3.3V with a temperature range of -40°C to 85°C. Many industrial applications have a long life expectancy. Toshiba designed BENAND with this in mind. With the ability to replace older generations of discrete SLC NAND, BENAND extends the product life of everything from telecom applications and LCD TVs to robots and printers – while also potentially reducing BOM costs.

According to Brian Kumagai, director of business development for TAEC, “SLC NAND is still very much an integral part of the overall NAND market, and leading-edge 24nm devices play a key role in enabling replacement of the older NAND devices that are still being used today.”

Toshiba’s 24nm BENAND requires no ECC from the host controller. This enables it to be used with host controllers that do not have 8-bit ECC capability.  Many legacy designs still use older processors that do not have 8-bit ECC capability, making BENAND a viable option for companies looking to design in a cutting-edge NAND solution with existing hardware. To ensure easy migration, BENAND’s features such as page/block size, spare area size, commands, interface and package remain the same as legacy 4xnm SLC NAND.

Toshiba’s continuing commitment to supporting 24nm SLC NAND flash provides industrial designers with the confidence of knowing that they have chosen the correct technology for their applications requiring production longevity. This support eliminates concerns about redesigning to a newer generation.

Applied Materials, Inc. and the Institute of Microelectronics (IME), a research institute under the Agency for Science, Technology and Research (A*STAR), today announced a five-year extension of their research collaboration at the Centre of Excellence in Advanced Packaging in Singapore. The organizations will expand the scope of their R&D collaboration to focus on advancing Fan-Out Wafer-Level Packaging (FOWLP), a key technology inflection expected to help make chips and end-user devices smaller, faster and more power efficient.

With an anticipated additional S$188 million of combined investment, the Centre will expand to a second location at Fusionopolis 2, in addition to the existing facility at Singapore’s Science Park II. The two facilities combined will span an area of approximately 1,700 square meters and be staffed by a team of close to 100 researchers, scientists and engineers. The Centre was built to develop new capabilities in advanced packaging through a full line of Applied Materials’ Wafer-Level Packaging (WLP) processing equipment, and has successfully delivered advancements in semiconductor hardware, process and device structures.

“Our collaboration with A*STAR over the past five years has been instrumental in establishing Applied Materials’ presence in Singapore and building up our R&D capabilities,” said Russell Tham, Regional President, Applied Materials South East Asia. “With the entire R&D value stream from ideation to product development being carried out locally via this joint lab, the expansion will further Applied Materials’ development of new technologies and products for global markets, while remaining a key contributor to Singapore’s innovation economy.”

Dr. Raj. Thampuran, Managing Director, A*STAR, said, “Our relationship with Applied Materials transcends a new milestone with the extension of our collaboration in R&D into new areas. The progress we have made from our initial collaboration is a testament to the successful partnership A*STAR has with Applied Materials. As we look towards the future, we remain committed to advancing innovations in the semiconductor industry and being at the forefront of leading edge ideas in this rapidly evolving technological landscape.”

The Internet of Things (IoT) and Big Data are driving forces in today’s market of interconnected and multi-functional electronic devices. FOWLP is considered a key technology platform for system scaling, enabling multiple chips to be integrated in a small form factor on a single package. With FOWLP capable of providing significant benefits for the mobile and wireless markets, increased investment in the sector could help propel Singapore’s standing as a global hub for semiconductor R&D. Through a successful alliance with its private sector partners across the value chain, A*STAR has contributed to Singapore’s vibrant research, innovation and enterprise ecosystem. In 2014, A*STAR and 10 other industry partners launched four Advanced Semiconductor Joint Labs to provide an integrated platform for complex microchip manufacturing R&D. These global partnerships together with the Applied Materials – A*STAR joint R&D Centre will continue to strengthen Singapore’s capabilities in semiconductor R&D and contribute to the creation of high-value jobs and competitiveness of the industry.

The Singapore Centre conducts WLP research across Applied Materials for its global customers. The Centre undertakes complex multi-disciplinary research to develop new innovations in advanced packaging including bump, TSV, 2.5D interposers and now FOWLP. Through its work at the Centre, Applied Materials has developed technology that has been successfully implemented in several of its semiconductor equipment products. In addition, the extension of the collaboration highlights the important role a successful public-private partnership plays in creating value and building up differentiated competencies for Singapore.

“Applied Materials’ leading expertise in materials engineering drives the development of highly differentiated products and solutions that make new technologies possible,” said Dr. Prabu Raja, Group Vice President and General Manager of the Patterning and Packaging Group, Applied Materials. “We are excited to expand our collaboration with A*STAR and leverage our complementary strengths to solve challenges in advanced packaging and build new capabilities for future innovations.”

A*STAR takes a long-term vision towards strategic investments in industry-ready R&D that contribute to Singapore’s economic growth. It is home to one of the premier advanced packaging and wafer-level packaging research facilities in Asia. IME’s leading research capabilities in advanced chip packaging are focused on meeting the challenging requirements in complex and sophisticated chip packaging, in order to develop slimmer devices with greater system capabilities such as ultra-low power consumption, increased memory and bandwidth, and diverse functionality.

Dr. Tan Yong Tsong, Executive Director, IME, said, “Our long standing collaboration with Applied Materials demonstrates the value of public-private partnership under open innovation, and underscores the readiness and competitiveness of IME’s research capabilities for the industry. Through this joint lab, we will continue to push the envelope through our differentiated R&D competencies to deliver breakthrough technologies.”