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GLOBALFOUNDRIES today announced plans to deliver a new leading-edge 7nm FinFET semiconductor technology that will offer the ultimate in performance for the next era of computing applications. This technology provides more processing power for data centers, networking, premium mobile processors, and deep learning applications.

GLOBALFOUNDRIES’ new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30 percent performance boost compared to today’s 16/14nm foundry FinFET offerings. The platform is based on an industry-standard FinFET transistor architecture and optical lithography, with EUV compatibility at key levels. This approach will accelerate the production ramp through significant re-use of tools and processes from the company’s 14nm FinFET technology, which is currently in volume production at its Fab 8 campus in Saratoga County, N.Y. GLOBALFOUNDRIES plans to make an additional mutli-billion dollar investment in Fab 8 to enable development and production for 7nm FinFET.

“The industry is converging on 7nm FinFET as the next long-lived node, which represents a unique opportunity for GLOBALFOUNDRIES to compete at the leading edge,” said GLOBALFOUNDRIES CEO Sanjay Jha. “We are well positioned to deliver a differentiated 7nm FinFET technology by tapping our years of experience manufacturing high-performance chips, the talent and know-how of our former IBM Microelectronics colleagues and the world-class R&D pipeline from our research alliance. No other foundry can match this legacy of manufacturing high-performance chips.”

“GLOBALFOUNDRIES made a bold decision to jump directly from 14nm to 7nm–a decision that is now supported by several leading semiconductor companies as they see only marginal performance and power benefits for the high cost of the 10nm process node,” said Jim McGregor, founder and principal analyst at TIRIAS Research. “Much like the 28nm and 16/14nm process nodes, 7nm appears to be the next major process node that will be widely leveraged by the entire semiconductor industry for at least the next decade.”

“Leading-edge technologies like GLOBALFOUNDRIES 7nm FinFET are an important part of how we deliver our long-term roadmap of computing and graphics products that are capable of powering the next generation of computing experiences,” said Dr. Lisa Su, president and CEO, AMD. “We look forward to continuing our close collaboration with GLOBALFOUNDRIES as they extend the solid execution and technology foundation they are building at 14nm to deploy high-performance, low-power 7nm technology in the coming years.”

“IBM is committed to pushing the limits of semiconductor technology as part of its aggressive long term research agenda,” said Arvind Krishna, senior vice president and director of IBM Research. “IBM Research continues to collaborate with GLOBALFOUNDRIES in developing new ideas, new skills and new technologies that will help accelerate our joint research in 7nm technology and beyond.”

GLOBALFOUNDRIES will deliver a comprehensive and competitive IP library, co-optimized with process development. To enable customers to accelerate adoption of 7nm FinFET technology, GLOBALFOUNDRIES has expanded its strategic partnership with INVECAS beyond 14LPP and FDX™ processes to now include foundry IP development for 7nm process technologies. This will provide customers with a strong foundation to build early designs that meet their performance, power and area requirements.

“INVECAS specializes in providing unrivaled IP solutions, ASIC and design services to GLOBALFOUNDRIES’ customers that span the wide-range of GLOBALFOUNDRIES’ leading edge FinFET and FDX processes,” said Dasaradha Gude, CEO, INVECAS. “Our strategic partnership with GLOBALFOUNDRIES combined with our tailor-made foundry IP model allows us to develop a 7nm FinFET process foundation IP that meets the challenging performance requirements of 7nm customers’ leading-edge applications.”

Building on the success of its 14LPP technology platform, GLOBALFOUNDRIES’ 7nm FinFET technology is positioned to enable next-generation computing applications that demand ultra-high performance, from high-end mobile SoCs to processors for cloud servers and networking infrastructure. The company’s high-performance offerings are complemented by its 22FDXTM and 12FDXTMtechnologies, which have been developed to meet the ultra-low-power requirements of the next generation of intelligent connected devices, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

GLOBALFOUNDRIES’ 7nm FinFET technology will be supported by a full platform of foundation and complex intellectual property (IP), including an application-specific integrated circuit (ASIC) offering. Test chips with IP from lead customers have already started running in Fab 8. The technology is expected to be ready for customer product design starts in the second half of 2017, with ramp to risk production in early 2018.

GLOBALFOUNDRIES today introduced a scalable, embedded magnetoresistive non-volatile memory technology (eMRAM) on its 22FDX platform, providing system designers with access to 1,000x faster write speeds and 1,000x more endurance than today’s non-volatile memory (NVM) offerings. 22FDX eMRAM also features the ability to retain data through 260°C solder reflow, industrial temperature operation, while maintaining an industry-leading eMRAM bitcell size.

GLOBALFOUNDRIES’ eMRAM will be offered initially on its 22FDX platform, which leverages the industry’s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. This versatile eMRAM technology is designed for both code storage (flash) and working memory (SRAM) to enable ultra-efficient memory sub-systems that can be power cycled without any energy or performance penalty. The power efficiency of FDX and eMRAM, coupled with the available RF connectivity IP, makes 22FDX an ideal platform for battery-powered IoT products and automotive MCUs.

“Customers are looking for a high-performance non-volatile memory solution that expands their product capabilities,” said Gregg Bartlett, senior vice president CMOS Platforms Business Unit, GLOBALFOUNDRIES. “Our introduction of 22FDX eMRAM enables system designers with new capabilities, allowing them to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.”

The emergence of autonomous vehicles is rapidly driving the need for increased on-chip memory capacities required for real-time vision processing, high-precision, continuous 3D mapping data and next-generation automotive MCUs that update over-the-air. GLOBALFOUNDRIES’ eMRAM uniquely addresses these advanced driving assistance system (ADAS) requirements by combining greater memory density than SRAM, with the fast write, very high endurance, and non-volatility that only magnetoresistive memory can provide.

“Emerging non-volatile memories are moving from the lab to the fab,” said Thomas Coughlin, President of Coughlin Associates. “GLOBALFOUNDRIES’ 22FDX eMRAM will offer a major advancement in SoC capabilities, by leveraging the key performance attributes of embedded MRAM. Designers of battery powered IoT devices, automotive MCUs and SoCs and SSD storage controllers will certainly want to take advantage of this versatile embedded NVM technology.”

The introduction of GLOBALFOUNDRIES’ 22FDX eMRAM is a result of the company’s multi-year partnership with MRAM pioneer, Everspin Technologies. The partnership has already delivered the world’s highest density ST-MRAM in August, 2016  – Everspin’s 256Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, which is now successfully sampling and is being readied for mass production at GLOBALFOUNDRIES.

GLOBALFOUNDRIES’ 22FDX eMRAM is currently in development and is expected to be available for customer prototyping in 2017, with volume production in 2018. GLOBALFOUNDRIES’ eMRAM technology is scalable beyond 22nm and is expected to be available on both FinFET and future FDX platforms.

Last March, the artificial intelligence (AI) program AlphaGo beat Korean Go champion LEE Se-Dol at the Asian board game.

“The game was quite tight, but AlphaGo used 1200 CPUs and 56,000 watts per hour, while Lee used only 20 watts. If a hardware that mimics the human brain structure is developed, we can operate artificial intelligence with less power,” points out Professor YU Woo Jong.

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In collaboration with Sungkyunkwan University, researchers from the Center for Integrated Nanostructure Physics within the Institute for Basic Science (IBS), have devised a new memory device inspired by the neuron connections of the human brain. The research, published in Nature Communications, highlights the devise’s highly reliable performance, long retention time and endurance. Moreover, its stretchability and flexibility makes it a promising tool for the next-generation soft electronics attached to clothes or body.

The brain is able to learn and memorize thanks to a huge number of connections between neurons. The information you memorize is transmitted through synapses from one neuron to the next as an electro-chemical signal. Inspired by these connections, IBS scientists constructed a memory called two-terminal tunnelling random access memory (TRAM), where two electrodes, referred to as drain and source, resemble the two communicating neurons of the synapse. While mainstream mobile electronics, like digital cameras and mobile phones use the so-called three-terminal flash memory, the advantage of two-terminal memories like TRAM is that two-terminal memories do not need a thick and rigid oxide layer. “Flash memory is still more reliable and has better performance, but TRAM is more flexible and can be scalable,” explains Professor Yu.

TRAM is made up of a stack of one-atom-thick or a few atom-thick 2D crystal layers: One layer of the semiconductor molybdenum disulfide (MoS2) with two electrodes (drain and source), an insulating layer of hexagonal boron nitride (h-BN) and a graphene layer. In simple terms, memory is created (logical-0), read and erased (logical-1) by the flowing of charges through these layers. TRAM stores data by keeping electrons on its graphene layer. By applying different voltages between the electrodes, electrons flow from the drain to the graphene layer tunnelling through the insulating h-BN layer. The graphene layer becomes negatively charged and memory is written and stored and vice versa, when positive charges are introduced in the graphene layer, memory is erased.

IBS scientists carefully selected the thickness of the insulating h-BN layer as they found that a thickness of 7.5 nanometers allows the electrons to tunnel from the drain electrode to the graphene layer without leakages and without losing flexibility.

Flexibility and stretchability are indeed two key features of TRAM. When TRAM was fabricated on flexible plastic (PET) and stretachable silicone materials (PDMS), it could be strained up to 0.5% and 20%, respectively. In the future, TRAM can be useful to save data from flexible or wearable smartphones, eye cameras, smart surgical gloves, and body-attachable biomedical devices.

Last but not least, TRAM has better performance than other types of two-terminal memories known as phase-change random-access memory (PRAM) and resistive random-access memory (RRAM).

Applying an electric field to some materials causes their atoms to “switch” their electric polarization from one direction to another, making one side of the material positive and the other negative. This switching property of “ferroelectric” materials allows them to be used in a wide range of applications. For example, ferroelectric capacitors are used to store binary bits of data in memory devices.

The newly synthesized crystal is ferroelectric above room temperature (a-b, e-f) and turns into "plastic phase", meaning highly deformable, at higher temperature (a to c). The electric polarity of each molecule can be aligned in one direction by applying electric field as it cools (c to e). Credit: Harada J. et al., July 11, 2016, Nature Chemistry, DOI: 10.1038/NCHEM.2567

The newly synthesized crystal is ferroelectric above room temperature (a-b, e-f) and turns into “plastic phase”, meaning highly deformable, at higher temperature (a to c). The electric polarity of each molecule can be aligned in one direction by applying electric field as it cools (c to e). Credit: Harada J. et al., July 11, 2016, Nature Chemistry, DOI: 10.1038/NCHEM.2567

Researchers at Japan’s Hokkaido University have developed a novel ferroelectric plastic crystal that could accelerate the development of more flexible, cost-efficient and less toxic ferroelectrics than those currently in use.

The crystal is ferroelectric above room temperature, then turns into a plastic, more pliable phase at higher temperatures. At the higher temperatures, the molecules in the crystal have randomly different polarity axes, but they can be aligned in one direction by applying an electric field as the crystal cools, bringing it back to a ferroelectric state.

Being able to control the polarity in this manner addresses a major challenge previously faced by researchers working with organic compound-based ferroelectric crystals. These are less symmetric than inorganic crystals, and can thus be polarized only in one direction leading to a very weak overall polarization of randomly oriented crystals.

A distinct advantage of this particular crystal is its transition to a plastic state when heat is applied. This plasticity – as opposed to fracturing that occurs in regular organic and inorganic crystals when a mechanical stress is applied – makes it extremely advantageous for use as a thin ferroelectric film in devices, such as non-volatile ferroelectric random-access memory devices, which maintain memory when the power is turned off.

Exploring crystals composed of molecules similar to quinuclidine could lead to the discovery of more ferroelectric crystals, write the researchers in their paper published in the journal Nature Chemistry. Chemical modifications of the molecules’ constituent ions could also improve their performance, the researchers add.

A research team led by Professor Keon Jae Lee from the Korea Advanced Institute of Science and Technology (KAIST) and by Dr. Jae-Hyun Kim from the Korea Institute of Machinery and Materials (KIMM) has jointly developed a continuous roll-processing technology that transfers and packages flexible large-scale integrated circuits (LSI), the key element in constructing the computer’s brain such as CPU, on plastics to realize flexible electronics (Advanced Materials, “Simultaneous Roll Transfer and Interconnection of Flexible Silicon NAND Flash Memory”).

This schematic image shows the flexible silicon NAND flash memory produced by the simultaneous roll-transfer and interconnection process. (Image: KAIST)

This schematic image shows the flexible silicon NAND flash memory produced by the simultaneous roll-transfer and interconnection process. (Image: KAIST)

Professor Lee previously demonstrated the silicon-based flexible LSIs using 0.18 CMOS (complementary metal-oxide semiconductor) process in 2013 (ACS Nano, “In Vivo Silicon-based Flexible Radio Frequency Integrated Circuits Monolithically Encapsulated with Biocompatible Liquid Crystal Polymers”) and presented the work in an invited talk of 2015 International Electron Device Meeting (IEDM), the world’s premier semiconductor forum.

Highly productive roll-processing is considered a core technology for accelerating the commercialization of wearable computers using flexible LSI. However, realizing it has been a difficult challenge not only from the roll-based manufacturing perspective but also for creating roll-based packaging for the interconnection of flexible LSI with flexible displays, batteries, and other peripheral devices.

To overcome these challenges, the research team started fabricating NAND flash memories on a silicon wafer using conventional semiconductor processes, and then removed a sacrificial wafer leaving a top hundreds-nanometer-thick circuit layer. Next, they simultaneously transferred and interconnected the ultrathin device on a flexible substrate through the continuous roll-packaging technology using anisotropic conductive film (ACF). The final silicon-based flexible NAND memory successfully demonstrated stable memory operations and interconnections even under severe bending conditions. This roll-based flexible LSI technology can be potentially utilized to produce flexible application processors (AP), high-density memories, and high-speed communication devices for mass manufacture.

Professor Lee said, “Highly productive roll-process was successfully applied to flexible LSIs to continuously transfer and interconnect them onto plastics. For example, we have confirmed the reliable operation of our flexible NAND memory at the circuit level by programming and reading letters in ASCII codes. Out results may open up new opportunities to integrate silicon-based flexible LSIs on plastics with the ACF packing for roll-based manufacturing.”

Dr. Kim added, “We employed the roll-to-plate ACF packaging, which showed outstanding bonding capability for continuous roll-based transfer and excellent flexibility of interconnecting core and peripheral devices. This can be a key process to the new era of flexible computers combining the already developed flexible displays and batteries.”

Mentor Graphics Corporation (NASDAQ:  MENT) today announced the first phase of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of today’s advanced systems designs. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs. To efficiently manage the density and performance requirements for advanced PCB systems, the new Xpedition flow provides advanced technologies to enable design and verification of 3D rigid-flex structures, and to automate layout of high-speed topologies with advanced constraints.

“Our customers are industry leaders developing the world’s most advanced electronics systems. They require access to technologies that enable deployment of advanced technologies and techniques, from design for high performance, advanced packaging, growth of rigid-flex, and higher speeds and densities,” said AJ Incorvaia, vice president and general manager, Mentor Graphics Board Systems Division. “To deliver the latest Xpedition Enter­prise flow, we have partnered with our customers to address their strategic initiatives to manage increasing complexity, increase organizational collaboration, drive greater end-product quality, and facilitate enterprise IP management.”

Managing advanced rigid flex design complexity

Flex and rigid-flex PCBs are now found in all types of electronics products, from small consumer devices to aerospace, defense and automotive electronics where high reliability and safety are critical. The Xpedition rigid-flex technology enables a streamlined design process from initial stack-up creation through manufacturing.

Engineers can design complex rigid and flex PCBs in a fully supported 3D environment (3D design and verification—not just a 3D view), resulting in a correct-by-construction methodology for optimum reliability and product quality. 3D verification ensures that bends are in the right position, and elements on the board do not interfere with folding; this can be reviewed early in the design stage to prevent costly redesigns. Users can then export a 3D solid model to MCAD for efficient bi-directional PCB-enclosure co-design.

Integration with Mentor’s leading HyperLynx high-speed analysis technology enables optimization of signal and power integrity across complex rigid-flex stack-up structures. For fabrication preparation, the Xpedition flow provides all flex and rigid information using the ODB++ common data format. This methodology eliminates data ambiguities by clearly communicating the finished board intent to the fabricator. The new Xpedition flow is the optimum solution designed specifically for flex and rigid-flex design, from conception through fabrication output.

“Mentor’s new Xpedition flow provides multiple board outlines, stack-ups, and bend areas which allow us to define a rigid flex within the design environment, and export a folded 3D step model for efficient mechanical design integration,” stated Charles Ietswaard, PCB design engineer at NIKHEF, the national institute for sub-atomic physics in The Netherlands. “The automated rigid-flex capabilities in Xpedition help us manage the growing complexities of today’s advanced PCB systems with ease, higher productivity and overall product reliability.”

Samsung Electronics Co., Ltd. this week introduced a blueprint for next-generation flash memory solutions that will meet the ever-increasing demands of big data networks, cloud computing and real-time analysis.

Samsung 32TB SAS SSD - world's largest capacity drive (Photo: Business Wire)

Samsung 32TB SAS SSD – world’s largest capacity drive (Photo: Business Wire)

At Flash Memory Summit 2016, held in the Santa Clara (CA) Convention Center, Samsung showcased its 4th generation Vertical NAND (V-NAND) and a line-up of high-performance, high-capacity solid state drives (SSDs) available for its enterprise customers as well as Z-SSD, a new solution providing breakthrough performance for flash-based storage.

Samsung’s new flash storage devices are expected to contribute significantly to the global IT industry in meeting the growing storage requirements of today’s enterprise computing environment. These solutions will accommodate enormous amounts of data, and extremely high-speed information processing, while enhancing the total cost of ownership (TCO) for data centers.

“With our 4th generation V-NAND technology, we can provide leading-edge differentiated values in high-capacity, high-performance and compact product dimensions, which together will contribute to our customers achieving better TCO results,” said Young-Hyun Jun, President of the Memory Business at Samsung Electronics. “We will continue to introduce more advanced V-NAND solutions and expand our flash business initiatives in maximizing an unbeatable combination of performance and value.”

Samsung’s 4th Generation V-NAND stacks 30 percent more layers of cell-arrays than its predecessor

Samsung introduced its 4th generation, 64-layer triple-level-cell V-NAND flash memory that pushes the envelope of NAND scaling, performance and storage capacity. Stacking 64 layers of cell-arrays, the new V-NAND can increase its single-die density to an industry-leading 512Gb and its IO speed to 800Mbps. Starting in August 2013, Samsung has previously introduced three generations of “industry-first” V-NAND products with 24, 32 and 48-layer vertical cell-array stacking technologies.

Samsung plans to provide the world’s first 4th generation V-NAND flash memory products in the fourth quarter of this year, which will help manufacturers to produce faster, more stylish and portable computing devices, while offering consumers a more responsive computing environment.

World’s largest capacity drive − 32TB SAS SSD − for enterprise storage systems

Samsung’s latest Serial Attached SCSI (SAS) SSD is the world’s largest single drive ever introduced to the industry based on 512-gigabit (Gb) V-NAND chips. A total of 512 V-NAND chips are stacked in 16 layers to form a 1-terabyte (TB) package and the 32-terabyte (TB) SSD contains 32 of those packages.

By adopting a new 4th generation V-NAND design, the 32TB SAS SSD can reduce system space requirements up to 40 times compared with the same type of system using two racks of hard disk drives (HDDs). The 32TB SAS SSD will come in a 2-5-inch form factor and be produced in 2017. Samsung also expects that SSDs with more than 100TB of storage capacity will be available by 2020, thanks to continued refinement of V-NAND technology.

1TB memory in a single BGA package

The Samsung 1TB BGA SSD features an extremely compact, ball grid array (BGA) package design that contains all essential SSD components including triple-level-cell V-NAND flash chips, LPDDR4 mobile DRAM and a state-of-the-art Samsung controller.

It will deliver unprecedented performance, reading sequentially at 1,500MB/s and writing sequentially at 900MB/s. By reducing its size up to 50 percent compared to its predecessor, the SSD weighs only about one gram (less than half the weight of a U.S. dime), making it ideal for ultra-compact next generation notebooks, tablets and convertibles.

Next year, Samsung plans to launch its 1TB BGA SSD by adopting a high-density packaging technology called “FO-PLP (Fan-out Panel Level Packaging)” which Samsung Electronics developed with Samsung Electro-Mechanics.

New ‘Z-SSD’ breaks through performance limits of current NAND flash memory storage

Samsung has also developed a high-performance, ultra-low latency SSD solution, the Z-SSD. Samsung’s Z-SSD shares the fundamental structure of V-NAND and has a unique circuit design and controller that can maximize performance, with four times faster latency and 1.6 times better sequential reading than the Samsung PM963 NVMe SSD.

The Z-SSD will be used in systems that deal with extremely intensive real-time analysis as well as extending high performance to all types of workloads. It is expected to be released next year.

Microsemi Corporation (NASDAQ:  MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the production release of its Flashtec NVM Express (NVMe)2032 and NVMe2016 controllers, enabling the world’s leading enterprises and data centers to realize the highest performance solid state drives (SSDs) utilizing next-generation NAND technologies. Providing the highest capacity, performance and reliability to store critical data, the devices are the industry’s first SSD controllers to integrate DDR4 DRAM, alleviating bottlenecks and maximizing throughput.

“Microsemi is pleased to announce the production release of our second-generation Flashtec NVMe controllers, tuned for enterprise storage, server and data center workloads,” said Derek Dicker, vice president and business unit manager, performance storage, at Microsemi. “These controllers deliver world class performance, advanced low-density parity-check (LDPC) error correction suitable for managing next-generation 3D NAND, and a programmable architecture upon which SSD builders can develop custom firmware, providing developers the ultimate means of product differentiation.”

Microsemi’s second-generation Flashtec NVMe2032 and NVMe2016 controllers support the standard NVMe host interface and are optimized for high-performance 4KB random read/write operations, performing all flash management operations on-chip and consuming negligible host processing and memory resources. In addition, the controllers can achieve up to 1 million random read input/output operations per second (IOPS).

“We congratulate Microsemi on the production release of its second-generation NVMe 2032/2016 enterprise NVMe controller with a high-performance, flexible low-density parity-check engine,” said Eric Endebrock, vice president of Storage Marketing Micron. “These types of enabling technologies align to Micron’s 3D NAND needs which are focused on mission-critical and high performance workloads.”

Hyperscale and enterprise data centers continue adopting NVMe due to the high speed and low latency connection between SSDs and host processors, providing significant performance advantages over SAS and SATA. According to market research firm IDC’s report titled, “Worldwide Solid State Drive Forecast, 2015–2019,” the number of high-performance PCIe-based SSD units has an estimated compound annual growth rate of 44 percent from 2014-2019. As part of Microsemi’s broad Flashtec controller family, the NVMe2032 and NVMe2016 controllers cater to this growing demand for robust NVMe-based solutions, with the devices optimized for power efficiency while providing customers the highest levels of performance, data integrity and reliability.

Engineers from the University of Utah and the University of Minnesota have discovered that interfacing two particular oxide-based materials makes them highly conductive, a boon for future electronics that could result in much more power-efficient laptops, electric cars and home appliances that also don’t need cumbersome power supplies.

Their findings were published this month in the scientific journal, APL Materials, from the American Institute of Physics.

The team led by University of Utah electrical and computer engineering assistant professor Berardi Sensale-Rodriguez and University of Minnesota chemical engineering and materials science assistant professor Bharat Jalan revealed that when two oxide compounds — strontium titanate (STO) and neodymium titanate (NTO) — interact with each other, the bonds between the atoms are arranged in a way that produces many free electrons, the particles that can carry electrical current. STO and NTO are by themselves known as insulators — materials like glass — that are not conductive at all.

But when they interface, the amount of electrons produced is a hundred times larger than what is possible in semiconductors. “It is also about five times more conductive than silicon [the material most used in electronics],” Sensale-Rodriguez says.

This innovation could greatly improve power transistors — devices in electronics that regulate the electrical current –by making power supplies much more efficient for items ranging from televisions and refrigerators to handheld devices, Sensale-Rodriguez says. Today, electronics manufacturers use a material called gallium nitride for transistors in power supplies and other electronics that carry large electrical currents. But that material has been explored and optimized for many years and likely cannot be made more efficient. In this discovery made by the Utah and Minnesota team, the interface between STO and NTO can be at the very least as conductive as gallium nitride and likely will be much more in the future.

“When I look at the future, I see that we can perhaps improve conductivity by an order of magnitude through optimizing of the materials growth,” Jalan says. “We are bringing the possibility of high power, low energy oxide electronics closer to reality.”

Power transistors that use this combination of materials could lead to smaller devices and appliances because their power supplies would be more energy efficient. Laptop computers, for example, could ditch the bulky external power supplies — the big black boxes attached to the power cords — in favor of smaller supplies that are instead built inside the computer. Large appliances that consume a lot of electricity such as air conditioners could be more power efficient. And because there is less power wasted (wasted electricity usually dissipates into heat), these devices will not run as hot as before, says Sensale-Rodriguez. He also believes that if more electronics use these materials for transistors, collectively it could save significant amounts of electricity for the country.

“It’s fundamentally a different road toward power electronics, and the results are very exciting” he says. “But we still need to do more research.”

Smaller and faster has been the trend for electronic devices since the inception of the computer chip, but flat transistors have gotten about as small as physically possible. For researchers pushing for even faster speeds and higher performance, the only way to go is up.

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor “fin” for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

“We are exploring the electronic device roadmap beyond silicon,” said Xiuling Li, a U. of I. professor of electrical and computer engineering and the leader of the study. “With this technology, we are pushing the limit of the vertical space, so we can put more transistors on a chip and get faster speeds. We are making the structures very tall and smooth, with aspect ratios that are impossible for other existing methods to reach, and using a material with better performance than silicon.”

The team published the results in the journal Electron Device Letters.

Typically, finFETs are made by bombarding a semiconductor wafer with beams of high-energy ions. This technique has a number of challenges, Li said. For one, the sides of the fins are sloped instead of straight up and down, making them look more like tiny mountain ranges than fins. This shape means that only the tops of the fins can perform reliably. But an even bigger problem for high-performance applications is how the ion beam damages the surface of the semiconductor, which can lead to current leakage.

The Illinois technique, called metal-assisted chemical etching or MacEtch, is a liquid-based method, which is simpler and lower-cost than using ion beams, Li said. A metal template is applied to the surface, then a chemical bath etches away the areas around the template, leaving the sides of the fins vertical and smooth.

“We use a MacEtch technique that gives a much higher aspect ratio, and the sidewalls are nearly 90 degrees, so we can use the whole volume as the conducting channel,” said graduate student Yi Song, the first author of the paper. “One very tall fin channel can achieve the same conduction as several short fin channels, so we save a lot of area by improving the aspect ratio.”

The smoothness of the sides is important, since the semiconductor fins must be overlaid with insulators and metals that touch the tiny wires that interconnect the transistors on a chip. To have consistently high performance, the interface between the semiconductor and the insulator needs to be smooth and even, Song said.

Right now, the researchers use the compound semiconductor indium phosphide with gold as the metal template. However, they are working to develop a MacEtch method that does not use gold, which is incompatible with silicon.

“Compound semiconductors are the future beyond silicon, but silicon is still the industry standard. So it is important to make it compatible with silicon and existing manufacturing processes,” Li said.

The researchers said the MacEtch technique could apply to many types of devices or applications that use 3-D semiconductor structures, such as computing memory, batteries, solar cells and LEDs.