Tag Archives: letter-ap-tech

Rudolph Technologies, Inc. (NYSE: RTEC) today unveiled its new patented Clearfind technology, which can detect organic defects that are difficult or impossible to see with conventional white-light imaging techniques. Organic contaminants are often the root cause of field failures, which occur after the material has been exposed to operating conditions for extended periods. Rudolph has been actively collaborating with several key customers to fully understand their inspection challenges and how the new technology addresses them, and plans to incorporate Clearfind technology in its upcoming defect inspection systems for advanced packaging applications.

“As advanced packaging processes become more complex, process windows are shrinking and manufacturers are seeking better methods for control and inspection that balance the need for high throughput against the ‘escape’ of true defects and the ‘false positive’ detection of nuisance defects,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Organic defects, in particular, have become more troublesome as die interconnects shrink and there is less surface area for good adhesion. Clearfind technology will help our customers see these defects earlier in the process, permitting faster action to mitigate the root cause and reducing the amount of product in jeopardy.”

Goodrich continued, “Using laser illumination we are able to clearly identify residue defects that typical white-light optics would miss. In addition to optimizing the wavelength of the illumination to enhance detection, we have specifically designed the mechanics of the system to accommodate the high warpage found in advanced packaging applications.”

Clearfind technology highlights organic residues on bumps and bond pads or at the bottoms of vias so that they are easy to detect. On metals, it eliminates the high-contrast graininess seen under conventional illumination, resulting in an obvious defect signal against a featureless background. This same graininess in conventional imaging can also cause false positives, which are especially costly at this stage of the process where the sunk cost of unnecessarily rejected good product is high. Finally, Clearfind technology readily detects shorts and opens in metal lines when inspected with an underlying organic layer. Rudolph believes these capabilities will significantly increase its customer’s ability to detect process and manufacturing related issues earlier in the process resulting in significant yield, which equates to millions of dollars in savings, especially for processes utilizing known-good die. Rudolph’s customers see this as a critical technology to improve quality for their customers in order to avoid the high costs of replacement and penalties.

For more information about the new Clearfind technology, please visit Rudolph at SEMICON West, booth 6543, in the North Hall.

clearfind-images-final

Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

The Applied PROVision– system is the industry’s most advanced e-beam inspection tool, incorporating innovations based on more than 20 years of leading expertise in e-beam technology for review and metrology. It is the only e-beam hotspot inspection tool offering down to 1nm resolution, allowing customers to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields.

“The PROVision system is the latest addition to our e-beam portfolio, and is a key part of Applied’s growth strategy,” said Bob Perlmutter, vice president and general manager of Applied’s Imaging and Process Control Group. “Our differentiated e-beam column technology is the best in the industry and when coupled with our customers’ new inspection methodologies, enables the PROVision system to go beyond R&D use and into production environments.”

The PROVision system is gaining momentum with already more than a dozen shipments, including repeat orders from a leading foundry and a major memory manufacturer. Additional systems are scheduled for shipment to existing and new customers in the second half of 2016.

“The PROVision system’s unique combination of high resolution and massive sampling has helped accelerate time to solution and time to market for our advanced nodes,” said Dr. Oh-Jang Kwon, SK hynix R&D EBI Group.

Offering 3x faster throughput over existing e-beam hotspot inspection tools, the PROVision system ensures accurate process characterization, prediction and detection of performance- and yield-limiting defects throughout the fab product life cycle. The PROVision system complements Applied’s e-beam metrology and review products as well as the optical patterned wafer inspection product line.

071116 Applied PROVision system

The Strategic Materials Conference (SMC 2016), focusing on “Scaling Challenges: The Future of Materials and Packaging,” will be held September 20-21, at the Computer History Museum in Mountain View, Calif.  The annual two-day SEMI conference brings together key players from the semiconductor industry ecosystem to share insights on the latest developments in advanced materials. SMC 2016 will delve into what’s driving demand for new materials and packaging and discuss how suppliers are responding to problems posed by existing scaling limitations.

Productivity gains, process improvements, and materials innovation are being combined with novel device packaging approaches. Presentations from representatives of NVIDIA, Samsung, Intel Corporation, ICMTIA China, Tokyo Electron America, GLOBALFOUNDRIES, Micron Technology, Bank of America, Qualcomm Research, STATS ChipPAC and many other industry leaders will discuss trends and opportunities. Professionals interested in industry innovation and business success are encouraged to attend. The sessions include:

  • Economic & Market Trends: Industry and Wall Street experts will present findings on trends in materials, equipment, production, and emerging applications.
  • Future of Moore’s Law and Encounters of a 3D Kind: Will 2D CMOS scaling pace Moore’s Law or will new 3D options be the pathway to keep on track?
  • Disruptive Trends and Opportunities for New Materials: Demand for PCs, tablets, and smartphones is slowing. How quickly will new market segments such as IoT, smart cars, and wearable devices drive demand for new materials?
  • Advanced Packaging: Advanced packaging extends the scaling of advanced devices. As a result, competitors are introducing an array of new proprietary packaging technologies and designs.  Innovation in packaging materials is working hard to keep pace.
  • Contamination and Metrology Challenges: Devices are increasingly sensitive to contaminants, making detection, identification, and control a focal point in fab operations and the supply chain. How will the industry address contamination control issues at advanced technology nodes?
  • Strategic Materials Challenges from the Fab Perspective: Facing flat growth, cost sensitivity, and consolidation, the industry must now focus on next materials needs, supply chain issues, and building collaborative, win-win relationships between manufacturers and suppliers.

The Strategic Materials Conference provides comprehensive in-depth content and unprecedented networking opportunities for professionals who share common strategic objectives for the extended electronics ecosystem.  To register for SMC 2016, click here.

What do you use to handle thin wafers and thin reconstituted wafers?  Increasingly miniaturized electronic devices require decreased profile heights, reduced foot-prints and ultimately, the perpetual thinning of wafers.  Initially, working with thin wafers typically required temporary bonding of the wafer to a carrier and use of a temporary coating layer for wafer protection.

For fan-out wafer-level packaging and 3D packaging, thin wafer handling is critical; the wafer must not warp, bend or shift during any wafer-processing steps.  These wafer processing steps may involve different temperature ranges and exposure to a variety of chemicals depending on the processing steps such as etching, metallization, CMP, PVD, RDL in embedded, fan-out, and 3D wafer-level packaging.

AI Technology, Inc. (AIT) manufactures a series of temporary bonding materials for processing temperatures up to 150 Cº. They are well accepted for grinding, dicing, etching, and deposition.  AIT customers prefer AIT bonding materials over conventional wax materials specifically because AIT’s products feature ease of use and quick removal, especially for very delicate compound wafers and photonics.

For higher temperature processing, AI Technology, Inc. (AIT) developed high temperature wafer processing adhesives (WPA) that can withstand processing temperature up to 330ºC. Also important is the chemical resistance of these WPA materials to acids and bases during the etching processes.  The thermal and chemical stability allows these adhesive to maintain its chemical integrity allowing the thin wafer be separated from the wafer handler/carrier by heat-sliding or by laser de-bonding equipment.  The WPA adhesive layer is designed to absorb UV breaking chemical bonds at the interface allowing for ease of separation.  After separation, the WPA adhesive layer can be removed by peeling with minimum stress or solvent cleaning.

Besides supplying these WPA products in spin coating liquid, AI Technology, Inc. (AIT) also provides WPA as a thin film. This unique and innovative WPA-film minimizes processing time and total waste produced compared to a typical spin-coating process allowing higher through-put.  In high volume manufacturing, some fan-out packaging involves reconstituted panels with larger dimensions compared to the traditional circular and small wafer size. For these high volume manufacturing panels, adhesive film in sheet format may provide the most efficient productivity.  Typically heat-laminated onto a wafer first and followed by vacuum lamination of the wafer onto the carrier, AIT’s WPA thin film processing conditions and debonding techniques resemble the spin coating process used in WPA products.

AI Technology, Inc. (AIT) understands that different types of wafers, Si, GaAs, GaN, InP, glass, and sapphire are used in different applications and, depending on wafer processing conditions, demand highly specialized tools and equipment.  AIT is committed to working closely with our customers and equipment suppliers to satisfy customer needs.

By Paula Doe, SEMI

Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors. There’s also the challenges of packaging integrated photonics, flexible electronics, and high-voltage, high-temperature wide-bandgap power devices. Speakers from the National Network for Manufacturing Innovation Institutes targeting these new growth markets will update the SEMICON West 2016 audience on their efforts to cut the time and cost of moving from R&D to volume production for U.S. companies by supporting development of key technologies, U.S.-based facilities for fabrication and packaging, and education of the workforce.

ap forum 2016-1

Integrating silicon with optics

The new American Institute for Manufacturing Integrated Photonics (AIM Photonics) is ramping up its program to spur development of U.S. technology and manufacturing capability for integrated photonics, for next-generation high performance computing, telecommunications, and sensors. In the packaging space, first steps will be a university-industry effort to develop passive fiber-to-silicon assembly technology and automated test equipment, with a manufacturing facility targeted for 2017.

“We’re focusing on packaging, assembly and test since it accounts for most of the cost of integrated photonics,” says CEO Michael Liehr, who will update on the plans to facilitate U.S. manufacturing in this emerging sector in the Packaging Photonics session at SEMICON West on July 12.

Attaching an optical fiber of 120µm diameter to a waveguide of only several thousand angstroms remains a major challenge, typically requiring active alignment.  Volume production will need a passive alignment solution, which will require some combination of major improvement in precision of current placement tools (such as with image recognition) with some way to make the coupling more fault tolerant ─ such as by using an interposer to bridge the gap. Tool makers will need standard package interfaces to make common, not custom equipment. The institute will also work on the packaging issues of integrating the laser with the waveguides and other optical features on silicon.

“Key elements are also missing for test,” Liehr notes. “The in-line part is missing. No one has put together a commercially available system that includes the prober, the optical detection, and the coupler needed.”  The institute is putting together a university and industry team to develop solutions, and then will equip a facility to do the test, assembly and packaging of these photonic integrated circuits.

AIM Photonics also targets a Process Design Kit (PDK) design kit by the end of the year for its multi-project photonic wafers run in its front-end fab. Besides data center and telecommunications applications of integrated photonics, AIM Photonics is working with companies on phased arrays and optical sensors for healthcare and defense applications. The organization is a public-private venture, funded by the U.S. Department of Defense, the States of New York, Massachusetts, California, Arizona, and university and industry members.

Integrating silicon die into flexible, conformable electronics systems

Another emerging “packaging” opportunity is integrating silicon intelligence into  flexible, stretchable products. “People have been talking for decades now about a purely printed solution, but printed transistors do not have enough mobility for the needed performance, and in a switching application will burn out in about a day” notes Jason Marsh, Director of Technology at NextFlex, the Manufacturing Innovation Institute for Flexible, Hybrid Electronics, who will talk about this effort at the SEMICON program on flexible packaging July 14. “But there is real demand for flexible, conformable products for medical wearable and implantable devices and for IoT edge devices.”  The collaborative program aims to develop the manufacturing technology to enable these products, by integrating silicon die into flexible, stretchable environments.

This will require the development of new processes for bridging directly from ~100µm-scale printed electronic circuits to 50µm-scale PCB artwork to much finer die-level bond-pad pitch, eliminating the usual intervening steps ─ of wirebond/flip chip, package, interposer, circuit board, connector ─ all at low temperature and with good signal integrity. Potential approaches could include flip chip with an anisotropic conductor connection, or alternatively, printing the traces directly on bigger pond pads. The institute aims to develop the basic building blocks of the technology and put together a U.S. supply chain that companies can then use to develop and manufacture their own products. NextFlex is building a facility in San Jose for the technology, which members can use to develop prototypes and build their pilot products.

Building this new manufacturing supply chain means re-thinking the traditional food chain of circuit board, packaging and assembly. “We may need to do things in different order, with die attach to the substrate before circuitization, and may need big arrays on big substrates, with new process tools to handle them,” suggests Marsh. “Package and assembly suppliers will need to understand more of the full end-to-end process, with assembly companies understanding packaging, and packaging companies understanding interposers.” The project aims to help bring these suppliers together, and also to help develop the necessary technical expertise in the workforce in the U.S. “The goal is to accelerate the speed of development from some 5-6 years to 1-2 years,” says Marsh.

The program is funded by $75 million from the U.S. government, and $96 million from the City of San Jose, and other corporate, academic, and government partners.

Building a U.S. ecosystem for wide bandgap power semiconductor manufacturing

PowerAmerica, the Next Generation Power Electronics Manufacturing Innovation Institute, aims to build the U.S. ecosystem for manufacturing wide bandgap power semiconductors, by supporting R&D, production facilities, and workforce development to accelerate the adoption of these smaller, lighter and more energy efficient power systems, and to make it easier for new and small U.S. companies to develop products.

“It’s about driving down cost and validating the reliability of SiC and GaN for demanding power electronics applications. The physics are clear. Wide bandgap semiconductors can offer very high-power densities and higher performance with a lower cost bill of materials. We are rapidly approaching the tipping point where market demand and production volume will bring the price of wide bandgap devices down to match silicon in $/Amp,” says John Muth, PowerAmerica’s deputy director, who will update on the effort in the power packaging program at SEMICON West on July 12.

Taking full advantage of the physical properties of wide bandgap semiconductors for high performance will require highly optimized packages that can handle high voltages while minimizing inductance and efficiently remove heat, with more reliable materials for interconnections, die attach, and baseplate/substrates, and better cooling solutions. One result of the packaging projects to date are the low inductance, high performance power modules recently announced by Wolfspeed.

PowerAmerica activities across the supply chain range from the 6-inch SiC foundry at X-Fab in Lubbock, Texas, now being used by five members, to products under development by end users across in transportation, renewable energy, motor drives, data centers, and the power grid, at members such as ABB, Agile Switch, Atom Power, John Deere, Navitas, Lockheed-Martin, and Toshiba.

The institute has recently also started to invite unsolicited proposals that solve a technical problem to help grow and strengthen the supply chain or to accelerate adoption of SiC or GaN into new products. All projects have 1:1 cost sharing, and require a clear path to market. Other efforts include aggressive demonstrations of wide bandgap semiconductor performance by universities, industry-led road mapping activities, and curriculum development at member universities, and tutorials and short courses to bring industry engineers quickly up to speed in GaN and SiC technology.

The five-year $146 million program is funded by $70 million from DOE and another $76 million from cost matching from its members and the state of North Carolina.

To learn more about SEMICON West 2016, visit the Schedule-at-a-Glance and learn about the eight forums.

Correction: The first draft of this article stated in error that Jason Marsh’s talk would take place on July 12. Jason Marsh will speak on flexible packaging at SEMICON West on July 14.

Samsung Electronics Co., Ltd. announced today that it has introduced “Fx-CSP,” a line-up of LED packages which features chip-scale packaging and flexible circuit board technology, for use in automotive lighting applications.

New Samsung Fx-CSP automotive LED packages (Graphic: Business Wire)

New Samsung Fx-CSP automotive LED packages (Graphic: Business Wire)

“Our new Fx-CSP line-up will bring greater design flexibility and cost competitiveness to the automotive lighting industry,” said Jacob Tarn, executive vice president, LED Business Team, Samsung Electronics. He added that, “We will continue to introduce innovative LED products and technologies, such as multi-chip array technology, that can play a key role in the growth of the automotive LED lighting industry.”

Samsung’s new Fx-CSP provides an advanced combination of chip-scale packaging and flexible circuit board technology, which together enable more compact chip sizing and a higher degree of reliability. The use of a flexible circuit board also enables more heat to dissipate, which leads to lower resistance and brings about a greater degree of lumen-per-watt efficiency than using a ceramic board.

In addition, the new Samsung automotive LED line-up allows car designers to use a variety of chip arrangements such as a single chip, a 1 by 4, or a 2 by 6 multi-chip arrangement to suit different lighting configurations. The Fx-CSP line-up can be widely used in automotive lighting applications that include position lamps and daytime running lamps as well as headlamps that require higher luminous flux and reliability than other automotive lamps.

The Fx-CSP line-up consists of single packages, Fx1M and Fx1L, with 1-3 watts each, as well as packages with a 14W high voltage array, Fx4 and a 40W high voltage array, Fx2x6. The variation in wattage levels allows Samsung LED lighting packages to work well with a wide range of exterior automotive lighting.

By adding the new Fx-CSP line-up to its existing mid-power and high-power automotive LED component line-ups, Samsung now provides a highly competitive family of automotive lighting components.

Samsung’s new Fx-CSP LED line-up was recently selected for a compact car headlamp project from one of the major global automotive manufacturers.

Samsung plans to introduce more CSP technology-based LED components such as the new Fx-CSP line-up for automotive lighting, later this year.

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented junction-less gate-all-around (GAA) nanowire (NW) FETs built in lateral and vertical configurations. With their simplified processing, improved reliability, reduced low frequency noise and lower IOFF values, they are an attractive option for advanced logic, low power circuits and analog/RF applications. Moreover, they enable a simpler path for considerable SRAM scaling via the stacking of vertical devices.

GAA-NWFETs -with the gate fully wrapped around the device body for optimum electrostatics control- are considered one of the most promising candidates for enabling (sub-)5nm CMOS scaling. Moreover, junction-less devices offer great process simplicity as they do not require junctions.

Previously, at the 2015 VLSI and IEDM conferences, imec demonstrated the superior reliability behavior of these devices and their potential for low power circuits. At today’s VLSI symposium, imec thoroughly evaluated key control knobs for junction-less devices operation, namely controlling the NW doping vs. NW size to achieve optimum performance. The feasibility of these devices for analog/RF applications was also studied, concluding them to be a viable option with reported similar speeds and voltage gains as compared to inversion-mode NWFETs.

Imec also addressed the variability of junction-less GAA-NWFETs, showing that whereas the VT mismatch increased with increasing nanowire doping for NMOS devices, less impact was observed for PMOS devices and at smaller nanowire dimensions.

Additionally, the junction-less concept was demonstrated in vertical devices integrated on the same 300mm Si platform, also used for lateral devices. Low IOFF and IGvalues and good electrostatics were achieved over a wide range of vertical nanowire arrays.

Lastly, taking advantage of the junction-less devices process simplicity, Imec further explored their potential by proposing a novel SRAM cell design with two vertically stacked junction-less vertical NWFETs with the same channel doping, thus enabling reduction of the SRAM area per bit by 39%.

“Imec’s work has contributed to an increased and more in-depth understanding of junction-less GAA-NWFETs,” stated Dan Mocuta, Director Logic Device and Integration at imec. “Our thorough evaluation highlighted the excellent performance of junction-less lateral and vertical nanowire devices for beyond 5nm logic devices. Moreover, junction-less devices appeared as a viable option for analog/RF applications, whereas stacked junction-less vertical nanowire FETs could significantly reduce SRAM area.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

Today, SEMI announced that the latest packaging solutions will be the topic of an in-depth session at the SEMICON West 2016 Advanced Packaging Forum – and on display on the exhibition floor. Rapidly changing technologies and accelerated product life cycles are driving the need for new assembly and packaging solutions suited for next-generation products such as Internet of Things (IoT) devices and wearables. To meet these packaging needs, semiconductor technologies with smaller form factors, lower power consumption, and flexible designs are increasingly in demand.

Advanced Packaging Forum 

Six complimentary packaging sessions are offered at the Advanced Packaging Forum at SEMICON West’s TechXPOT North stage. Pre-registration is required. Sessions explore what’s ahead in the world of packaging and assembly. The three-day forum will explore the challenges posed by new and emerging devices and offer solutions capable of enabling them. Technical sessions include:

  • SiP Next 1: Processor – Memory/Analog Integration
  • SiP Next 2:  IoT & Smart Things – SiP Integration
  • Sensing the Future: Enabling Applications for a Smarter World
  • Packaging Developments for Flexible, Hybrid Electronics
  • Packaging Power: Enabling a Variety of Applications and Efficiency
  • Packaging Photonics for Speed & Bandwidth

Sessions feature speakers from Cisco, Mentor Graphics, Texas Instruments, and more.  Attendees will learn about the latest in electronic packaging, thermal management, additive manufacturing, simulation, and reliability assessment; system optimization and differentiation through heterogeneous integration and SiP; sensor technologies for monitoring and analyzing complex data streams; and other advanced developments.

Packaging and Assembly Equipment Exhibitors

This year’s SEMICON West exposition also features packaging solutions on the show floor. Attendees can view more than sixty new products from some 200 exhibitors.

The industry is seeing dramatic changes and SEMICON West 2016 has expanded its technical programming by nearly 50 percent to help attendees get a clear view of the road ahead. To learn more about SEMICON West 2016’s eight new forums (Extended Supply Chain, Advanced Manufacturing, Advanced Packaging, Test, Silicon Innovation, Flexible Hybrid Electronics, and World of IoT), visit www.semiconwest.org.

MACOM Technology Solutions reported the newest entries in its MAGb series of GaN on Silicon power transistors for use in macro wireless basestations.

According to a media release, based on MACOM’s Gen4 GaN technology, the new MAGb-101822-240B0P and MAGb-101822-120B0P power transistors harness the clear performance benefits of GaN in rugged, low-cost plastic packaging, enabling improved cost efficiencies that further distinguish MACOM’s GaN power transistors as the natural successors to legacy LDMOS offerings for basestation applications.

The Company noted that the new plastic TO-272-packaged MAGb-101822-240B0P and MAGb-101822-120B0P power transistors provide 320 W and 160 W output peak power, respectively, in the load-pull system with fundamental tuning only, and cover all cellular bands and power levels within the 1.8 – 2.2 GHz frequency range. These transistors’ ability to operate over 400 MHz of bandwidth precludes the need to use multiple LDMOS-based products, further optimizing cost and design efficiencies.

MACOM said that plastic-packaged MAGb power transistors deliver power efficiency up to 79 percent – an improvement of up to 10 percent compared to LDMOS offerings – with only fundamental tuning across the 400 MHz RF bandwidth, and with linear gain of up to 20 dB. These transistors provide an alternative to ceramic-packaged devices without compromising RF performance or reliability – thermal behavior is improved by 10 percent compared to ceramic-packaged MAGb offerings.

“DPD is critical to increase the efficiency of power amplifiers for 4G and 5G basestation applications and has a significant impact on network operators’ operating expenses and capital expenditures,” said Dr. Chris Dick, Chief DSP Architect at Xilinx. “Our joint demonstration with MACOM at IMS 2016 will showcase the combined DPD capabilities of MACOM’s Gen4 GaN-based MAGb power transistors and Xilinx’s complementary DPD technologies on our 28 nm Zynq SoC and 16 nm UltraScale+ MPSoCs. This joint solution highlights the time-to-market advantages that can be achieved with a proven, interoperable DPD solution.”

“Our collaboration with Xilinx demonstrates the linearity and ease of correction of our MAGb, especially with signals that are known to be challenging to correct using GaN-based solutions like multi-carrier GSM and TDD-LTE signals,” said Preet Virk, Senior Vice President and General Manager, Carrier Networks, at MACOM. “We believe that with the introduction of our new plastic-packaged MAGb power transistors, we’re further extending this price/performance advantage over competiting LDMOS and other GaN technologies, and accelerating the evolution to GaN-based PAs for wireless basestations.”

The nanoelectronics research centers imec and Holst Centre (set up by imec and TNO), presented a low-power wide-area (LPWA) multi-standard radio chip today at imec’s annual technology forum in Brussels (ITF Brussels 2016). The new radio chip is a best-in-class product, which can operate with a lower level of power consumption than any other radio chip technology released to date for long range connectivity in sensor networks. The sub-GHz radio chip’s technology can serve a multitude of protocols including IEEE 802.15.4g/k, W-MBUS, KNX-RF, as well as the popular LoRa and SIGFOX networks, and future cellular IoT for applications such as smart metering, smart home, smart city and critical infrastructure monitoring.

The radio chip operates in industrial, scientific, medical (ISM) and short-range devices (SRD) bands, covering a frequency range from 780MHz to 930MHz. The robust, low-power design combines a large link budget, with state-of-the-art interference rejection and lowest bill of materials by minimizing external components as compared to of-the-shelf available chips. The radio is implemented as a complete System-on-Chip (SoC) including the RF front end, power management, an ARM processor,160kBytes of SRAM and peripherals like SPI, I2C and UART. It features a targeted sensitivity of -120dBm at 0.1% BER (1kbps) and ultra-low power consumption of 8mW (Rx) and 113mW (Tx) for 13.5dBm output power. The receiver supports a wide gain range to handle input signals from -120dBm to -15dBm, corresponding to a large dynamic range of 105dB. The PA features automatic ramp-up and ramp-down for ARIB spectral mask compliancy. Furthermore, the output power is controllable from <-40dBm up to 15dBm.

“With the foreseen release of the NB-IoT protocol in June 2016 by the 3GPP, it is clear that protocols such as NB-IoT, SigFox and LoRA are here to stay for the coming years,” stated Kathleen Philips, program director perceptive systems at imec/Holst Centre. “Our novel sub-GHz radio chip can serve multiple of these protocols and is an ideal solution for long-range wireless connectivity  for IoT applications.”

Imec’s Industrial Affiliation program on the Intuitive Internet-of-Things (IoT) focuses on developing the building blocks for the future. The program explores an intuitive IoT, with sensor systems that can detect and assist with the needs and wants of people in an unobtrusive way, and can take into account their varied perspectives and surrounding environment. Along with low-power radio chips, imec also develops ultra-small, low-cost, intelligent, and ultra–low power sensors and heterogeneous sensor networks. Interested companies are invited to partner with imec on its varied research initiatives. Companies can also connect with imec to request access to imec’s technological advances to further develop their projects through licensing programs with imec.