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GLOBALFOUNDRIES today announced a next-generation radio-frequency (RF) silicon solution for its Silicon Germanium (SiGe) high-performance technology portfolio. The technology is optimized for customers who need improved performance solutions for automotive radar, satellite communications, 5G millimeter-wave base stations and other wireless and wireline communication network applications.

GLOBALFOUNDRIES’ SiGe 8XP technology is the latest extension to the company’s 130nm high-performance SiGe family and enables customers to develop RF solutions that deliver even faster data throughput, over greater distances, while consuming less power. The advanced technology offers an improved heterojunction bipolar transistor (HBT) performance with lower noise figure, higher signal integrity, and up to a 25 percent increase in maximum oscillation frequency (fMAX) to 340GHz compared to its predecessor, SiGe 8HP.

The complexity and performance demands of high bandwidth communication systems operating in the mmWave frequency bands have created the need for higher performance silicon solutions. This creates opportunities for high-performance SiGe solutions in the RF front end of 5G smartphones and other mmWave phased array consumer applications in addition to the current applications that depend on SiGe for high performance, such as the communications infrastructure base stations, backhaul, satellite and fiber optic networks.

“5G networks promise to bring a new level of innovation to RF SOC design to support high bandwidth data delivery and meet the demands for increased data rates and low latency applications,” said Dr. Bami Bastani, senior vice president of GLOBALFOUNDRIES RF business unit. “GLOBALFOUNDRIES’ SiGe 8HP and 8XP technologies offer an outstanding balance of performance, power, and efficiency that enable customers to develop differentiated RF solutions in next-generation mobile and infrastructure hardware.”

“GLOBALFOUNDRIES’ SiGe technology leadership and comprehensive PDKs enable our designers to develop performance-optimized, differentiated millimeter wave solutions quickly,” said Robert Donahue, Anokiwave CEO. “Utilizing SiGe 8XP allows us to take performance to even higher levels in future-ready mmWave solutions designed to help providers stay ahead of the demands for reliable connectivity, from anywhere, while handling exploding volumes of mobile data traffic.”

With tomorrow’s 5G deployments poised to drive a proliferation of base stations with smaller cell areas, SiGe 8HP and 8XP are designed to help offer a balance of value, power output, efficiency, low noise, and linearity at microwave and millimeter-wave frequencies for differentiated RF solutions in next-generation mobile infrastructure hardware and smartphone RF front ends. GLOBALFOUNDRIES’ SiGe 8HP and 8XP high-performance offerings enable chip designers to integrate significant digital and RF functionality while exploiting a more economical silicon technology base compared to gallium arsenide (GaAs) and higher performance than CMOS.

In addition to high performance transistors for efficient operation at mmWave frequencies, SiGe8HP and 8XP introduce technology innovations that can reduce the die size and enable area-efficient solutions. A new Cu metallization feature provides improved current carrying capabilities with five times the current density at a 100C, or up to 25 degrees C higher operating temperature at the same current density compared to standard Cu lines. In addition, GLOBALFOUNDRIES’ through-silicon-via (TSV) interconnect technology is available.

Synopsys, Inc. today announced that the company’s Custom Compiler tool has been enabled by Samsung for 14 nanometer (nm) LPP and LPC FinFET production. The process delivers high performance for compute-intensive designs and lower power consumption for mobile applications. Custom Compiler is a custom design solution from Synopsys that was announced on March 30th of this year. Custom Compiler support is provided through a jointly developed interoperable process design kit (iPDK)-format design kit. Unified with Synopsys’ circuit simulation, physical verification and digital implementation tools, Custom Compiler provides Samsung 14nm LPP and LPC process users with a comprehensive custom design solution.

“Samsung support for Custom Compiler is very important to our mutual customers,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, the two companies were able to deliver a design kit and set of tool features that enable Custom Compiler’s visually-assisted automation flow for Samsung Foundry customers.”

Custom Compiler shortens the time it takes to complete custom design tasks from days to hours—especially for FinFET process nodes. Its visually-assisted automation leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler’s visually-assisted automation provides four types of assistants: Layout, In-Design, Template and Co-Design. Layout Assistants speed layout with user-guided automation of device placement and routing. In-Design Assistants reduce design iterations by catching physical and electrical errors before signoff verification. Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Co-Design Assistants combine the IC Compiler place-and-route tool and Custom Compiler into a unified solution for custom and digital implementation. Custom Compiler is based on the industry standard OpenAccess database. It provides an open environment spanning schematics, simulation analysis and layout. Unified with Synopsys’ circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has received multiple orders for its GEMINI FB XT automated fusion wafer bonders from multiple leading device manufacturers. The GEMINI FB XT offers wafer-to-wafer alignment accuracy, customizable pre- and post-processing configurations with faster handling and improved process flows that increase throughput by up to 50 percent compared to the previous-generation platform, as well as integrated metrology to maximize yields and productivity in high-volume manufacturing (HVM). These latest orders for the GEMINI FB XT system will support several leading-edge HVM applications, including 3D stacked image sensors, memory stacking, and die partitioning for next-generation 3D system-on-chip (SoC) devices.

GEMINI FB XT Automated Production Fusion Bonding System

GEMINI FB XT Automated Production Fusion Bonding System

Vertical stacking of devices has become an increasingly viable approach to driving continuous improvements in device density and performance without the need for increasingly costly and complex lithography processing. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.

“These latest orders for our GEMINI FB XT system from multiple leading manufacturers reflect the fact that our most advanced fusion bonding platform meets critical production requirements for a variety of 3D chip stacking applications, and further demonstrates our leadership in fusion bonding,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Unparalleled wafer-to-wafer alignment accuracy supports IC manufacturers’ efforts to move wafer stacking upstream from back-end-of-line (BEOL) and mid-end-of-line (MEOL) applications to front-end-of-line (FEOL) processing where they can integrate more functionality into their product at the wafer level and further drive down manufacturing costs. The GEMINI FB XT has proven to fulfill the most stringent compatibility requirements and standards of front-end fabs. It also combines the capabilities necessary to bring new bonding technologies, like hybrid bonding for CMOS image sensors, into high-volume production. It is a true testament to our Triple-i philosophy of invent, innovate and implement.”

Leveraging EVG’s XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. It incorporates EVG’s proprietary SmartView NT face-to-face aligner to achieve wafer-to-wafer overlay alignment accuracy below 200 nm (3 sigma), which leads the industry in performance and is essential to enabling 3D integration. In addition, the system can accommodate up to six pre-and post-processing modules for surface preparation, conditioning and metrology steps―such as wafer cleaning, plasma activation, alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding. This enables the GEMINI FB XT to support fully automated and integrated wafer loading, alignment, bonding and unloading of bonded wafers in HVM environments.

One secret to creating the world’s fastest silicon-based flexible transistors: a very, very tiny knife.

Working in collaboration with colleagues around the country, University of Wisconsin-Madison engineers have pioneered a unique method that could allow manufacturers to easily and cheaply fabricate high-performance transistors with wireless capabilities on huge rolls of flexible plastic.

The researchers — led by Zhenqiang (Jack) Ma, the Lynn H. Matthias Professor in Engineering and Vilas Distinguished Achievement Professor in electrical and computer engineering, and research scientist Jung-Hun Seo — fabricated a transistor that operates at a record 38 gigahertz, though their simulations show it could be capable of operating at a mind-boggling 110 gigahertz. In computing, that translates to lightning-fast processor speeds.

It’s also very useful in wireless applications. The transistor can transmit data or transfer power wirelessly, a capability that could unlock advances in a whole host of applications ranging from wearable electronics to sensors.

The team published details of its advance April 20 in the journal Scientific Reports.

The researchers’ nanoscale fabrication method upends conventional lithographic approaches — which use light and chemicals to pattern flexible transistors — overcoming such limitations as light diffraction, imprecision that leads to short circuits of different contacts, and the need to fabricate the circuitry in multiple passes.

Using low-temperature processes, Ma, Seo and their colleagues patterned the circuitry on their flexible transistor — single-crystalline silicon ultimately placed on a polyethylene terephthalate (more commonly known as PET) substrate — drawing on a simple, low-cost process called nanoimprint lithography.

In a method called selective doping, researchers introduce impurities into materials in precise locations to enhance their properties — in this case, electrical conductivity. But sometimes the dopant merges into areas of the material it shouldn’t, causing what is known as the short channel effect. However, the UW-Madison researchers took an unconventional approach: They blanketed their single crystalline silicon with a dopant, rather than selectively doping it.

Then, they added a light-sensitive material, or photoresist layer, and used a technique called electron-beam lithography — which uses a focused beam of electrons to create shapes as narrow as 10 nanometers wide — on the photoresist to create a reusable mold of the nanoscale patterns they desired. They applied the mold to an ultrathin, very flexible silicon membrane to create a photoresist pattern. Then they finished with a dry-etching process — essentially, a nanoscale knife — that cut precise, nanometer-scale trenches in the silicon following the patterns in the mold, and added wide gates, which function as switches, atop the trenches.

With a unique, three-dimensional current-flow pattern, the high performance transistor consumes less energy and operates more efficiently. And because the researchers’ method enables them to slice much narrower trenches than conventional fabrication processes can, it also could enable semiconductor manufacturers to squeeze an even greater number of transistors onto an electronic device.

Ultimately, says Ma, because the mold can be reused, the method could easily scale for use in a technology called roll-to-roll processing (think of a giant, patterned rolling pin moving across sheets of plastic the size of a tabletop), and that would allow semiconductor manufacturers to repeat their pattern and mass-fabricate many devices on a roll of flexible plastic.

“Nanoimprint lithography addresses future applications for flexible electronics,” says Ma, whose work was supported by the Air Force Office of Scientific Research. “We don’t want to make them the way the semiconductor industry does now. Our step, which is most critical for roll-to-roll printing, is ready.”

The 62nd annual IEEE International Electron Devices Meeting (IEDM), to be held at the San Francisco Union Square Hilton hotel December 3 – 7, 2016, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 10, 2016. This deadline –– about 1½ months later than has been the norm for the IEDM – reduces the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Also new for 2016 is that authors are asked to submit four-page camera-ready abstracts (instead of three pages), which will be published as-is in the proceedings.

Because of the more abbreviated schedule, only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 12, 2016.

“Because microelectronics technology changes so rapidly, it makes sense to shorten the time between when results are achieved and when they are discussed among the industry’s best and brightest who attend IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair and Intel Fellow and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group. “This later submission deadline ensures that the freshest and most up-to-date work can be presented at the conference.”

Overall, the 2016 IEDM is seeking increased participation in the areas of power, wearable/Internet of Things (IoT), ultra-high speed, and quantum computing devices, which will be explored in depth in Special Focus Sessions in each area.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

Further information

For more information, interested persons should visit the IEDM 2016 home page at www.ieee-iedm.org.

Leti, an institute of CEA Tech, today announced the continuation of its collaboration with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to develop CoolCube, Leti’s new sequential integration technology that eliminates the need for through-silicon vias (TSVs) and enables the stacking of active layers of transistors in the third dimension.

The extended project’s goals include building a complete CoolCube ecosystem that takes the technology from design to fabrication.

CoolCube was created by Leti as a unique and innovative device scale-stacking technology that allows the design and fabrication of very high-density and high-performance circuits.

By introducing an innovative stacking process combined with low-temperature transistor processing, the technology allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

Mobile devices, in which minimal power consumption is key, are the primary segment for chips manufactured with the CoolCube technology. It also enables designers to include back-side imagers in chips, and co-integration of NEMS in a CMOS fabrication process.

Launched in 2014 so that Qualcomm Technologies could evaluate CoolCube’s potential, the project achieved several breakthroughs and original design methodology that demonstrated that it can provide a concrete solution for true 3D chips.*

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.”

As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs that will accelerate adoption of the technology.

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

Rudolph Technologies, Inc. today announced the availability of new, high-speed 3D metrology on its flagship NSX Series, a highly-flexible inspection and measurement platform for process development and control of die-level interconnects. Already in use by multiple customers worldwide, the NSX Series with high-speed 3D metrology is capable of both high-volume production monitoring and advanced process development.

“The new capability provides a 200-400 percent throughput improvement over our previous Wafer Scanner bump metrology system, and when paired with our Discover Software, provides a complete coplanarity solution for our customers,” said Scott Balak, Rudolph’s director, inspection product management. “With the increasing number of new packaging technologies being developed by foundries, outsourced assembly and test (OSAT) manufacturers, and integrated device manufacturers (IDMs), the flexibility and reliability of this new capability on the trusted NSX Series platform is especially valuable to customers seeking to move rapidly from pilot lines to production.”

Data is collected in seconds from millions of bumps and then analyzed by Rudolph’s Discover Software analysis database. Engineers gain unique insight into critical metrology applications, from both an individual bump point of view or holistically as a wafer, as part of a simultaneous product and process control solution.

“Manufacturers are looking for a more comprehensive and flexible process control solution that provides, not only inspection or bump data, but also usable analytical information about their processes,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Our powerful Discover analysis software provides insight into the process that is otherwise unavailable to process control tool owners. The high-speed 3D bump metrology capability incorporates a three segment optical range, giving our customers the flexibility to control both smaller micro bumps and larger traditional solder bumps with a single inspection and metrology platform. When combined with Rudolph’s advanced automation capability, customers can measure thin and warped wafers without the extra expense of frame and tape mounting.”

Goodrich concluded, “We understand the importance of 3DIC and next-generation packaging processes and we have aggressively pursued development of this comprehensive 3D coplanarity solution to meet our customers’ needs for a cost efficient, multi-functional process control tool.”

Two-dimensional electronic devices could inch closer to their ultimate promise of low power, high efficiency and mechanical flexibility with a processing technique developed at the Department of Energy’s Oak Ridge National Laboratory.

A team led by Olga Ovchinnikova of ORNL’s Center for Nanophase Materials Sciences Division used a helium ion microscope, an atomic-scale “sandblaster,” on a layered ferroelectric surface of a bulk copper indium thiophosphate. The result, detailed in the journal ACS Applied Materials and Interfaces, is a surprising discovery of a material with tailored properties potentially useful for phones, photovoltaics, flexible electronics and screens.

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

“Our method opens pathways to direct-write and edit circuitry on 2-D material without the complicated current state-of-the-art multi-step lithographic processes,” Ovchinnikova said.

She and colleague Alex Belianinov noted that while the helium ion microscope is typically used to cut and shape matter, they demonstrated that it can also be used to control ferroelectric domain distribution, enhance conductivity and grow nanostructures. Their work could establish a path to replace silicon as the choice for semiconductors in some applications.

“Everyone is looking for the next material – the thing that will replace silicon for transistors,” said Belianinov, the lead author. “2-D devices stand out as having low power consumption and being easier and less expensive to fabricate without requiring harsh chemicals that are potentially harmful to the environment.”

Reducing power consumption by using 2-D-based devices could be as significant as improving battery performance. “Imagine having a phone that you don’t have to recharge but once a month,” Ovchinnikova said.

Ceramic capacitors are used in a wide variety of electronics, ranging from computers and mobile phones to telecommunications transmitter stations and high voltage laser power supplies. Capacitors act, in a way, like batteries. They are “dielectric” – they act as an electronic insulator in which an electric field can be sustained with minimum loss of power. Their dielectric properties allow them to store electricity and then release it. One of the most widely used ceramics in capacitors is lead zirconate titanate, but it is hazardous to the health and the environment once it’s disposed. Scientists are trying to find other less hazardous ceramic materials for use in capacitors.

Perovskite oxynitrides – cheap and easily fabricated materials with a distinctive crystalline structure – are particularly promising. But ceramics manufactured from these materials need to be made denser to improve their insulating properties. This is usually done by applying intense heat; a process called “sintering”. However, sintering the material can lead to a change in its chemical composition, turning it from an insulator to an electrical conductor.

The researchers sintered the perovskite powder SrTaO2N at a temperature of 1723 Kelvin (1450° Celsius) for three hours. They then “annealed” the material by heating it with flowing ammonia at 1223 Kelvin (950° Celsius) for 12 hours and then allowing it to slowly cool.

They found that the surface of the material after this process (but not its interior) displayed an important dielectric property called “ferroelectricity”. This was the first time that a ferroelectric response has been observed on oxynitride perovskite ceramics, they say, making it promising as a new dielectric material for multi-layered ceramic capacitors.

A team of scientists from Hokkaido University and the multinational electronics company TDK Corporation in Japan has developed a method to improve the insulating properties of the oxynitride perovskite SrTaO2N for potential use as a ceramic capacitor. Credit: Tanusin Phunya/ 123rf

A team of scientists from Hokkaido University and the multinational electronics company TDK Corporation in Japan has developed a method to improve the insulating properties of the oxynitride perovskite SrTaO2N for potential use as a ceramic capacitor. Credit: Tanusin Phunya/ 123rf

GLOBALFOUNDRIES today announced new advanced radio-frequency (RF) silicon solutions, further expanding the portfolio of Silicon Germanium (SiGe) power amplifier (PA) technologies designed to enable performance-optimized cellular and Wi-Fi solutions in increasingly sophisticated mobile devices and hardware.

GLOBALFOUNDRIES’ 5PAx and 1K5PAx, together called PAx, are the latest extensions to its broad family of SiGe-based PA technologies. The advanced offerings deliver optimized PA, LNA and switch technology with improved power efficiency, noise figure and insertion loss enabling more power efficient next-generation Wi-Fi and cellular solutions for faster data access and uninterrupted connections.

“Mobile suppliers are facing mounting pressure to expand network capacity as wireless data consumption continues to increase rapidly,” said Dr. Bami Bastani, senior vice president of GLOBALFOUNDRIES RF business unit. “Our broad portfolio of high-performance SiGe power amplifier technologies provides a distinct design, performance and cost advantage that enables our mobility customers to deliver cost-effective solutions with faster data throughput, support wider coverage areas, and consume less power.”

Skyworks, a leader in high-performance analog semiconductor solutions, plans to use the technology to enhance both the power capability and efficiency for the next generation of mobile WLAN products and high-performance WLAN products, including access points, routers and IoT applications.

“The advances that are part of GLOBALFOUNDRIES’ SiGe PAx technologies enable RF front-end solutions for all levels of performance and complexity,” said Bill Vaillancourt, vice president and general manager of Mobile Connectivity at Skyworks Solutions. “With these advanced features and the ability to minimize form factor by implementing multiple RF functions on a chip, GLOBALFOUNDRIES’ latest PAx offerings enhance the capabilities of integrated semiconductor solutions that support customers’ needs for high performance, cost effective technologies addressing portable wireless communication devices.”

There are four technologies in GLOBALFOUNDRIES’ SiGe PA family, SiGe 5PAe, 1KW5PAe, and now 5PAx and 1K5PAx. All four offerings feature GLOBALFOUNDRIES’ proven through-silicon via technology and provide significant performance, integration functionality and cost advantages for customers who are currently using gallium arsenide (GaAs)-based alternatives. Today, there are more than three billion SiGe power amplifiers shipped worldwide using this family of technologies, and GLOBALFOUNDRIES has recently invested in additional manufacturing capacity to address the anticipated growth in the mobile sector. The newest offerings, 5PAx and 1K5PAx, are optimized to meet the rigorous demands of evolving mobile standards like 802.11ac, which demands three times faster data throughput than the previous generation of standards.

For 5GHz applications, SiGe 5PAx, the follow-on to SiGe 5PAe, supports 2dB gain along with a 5 percent PAE and 0.2dB low noise amplifier (LNA) improvements relative to the previous generation. SiGe 1K5PAx, like its predecessor 1KW5PAe, is built on a high-resistivity substrate, and is tuned for integration and higher performance. It features RF switches with approximately 15 percent better Ron-Coff compared to 1KW5PAe, and like 1KW5PAe, enables designers to minimize form factor by implementing multiple functions, such as power amplifiers, RF switches and LNAs, on a single chip.