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When people think about Wide Band Gap (WBG) materials for power electronics applications, they usually think of GaN or SiC. This is a not a surprise: indeed SiC and GaN are currently the most advanced WBG technologies for power electronics applications. However, there are materials with an even larger band gap which can further increase power device performance. What is the development status of such innovative technologies? Are there already some products available on the market? What is the added-value of such materials?

Yole Développement (Yole) proposes a comprehensive overview of the whole WBG solutions dedicated to the power electronics industry. This survey is entitled SiC, GaN and other WBG materials for power electronics applications. Including a detailed analysis of the most advanced WBG materials, SiC and GaN, Yole’s report also highlights the added-value of disruptive technologies such as Ga2O3, diamond and AlN. Yole’s analysts detail the status of such new solutions and the related technology roadmap. The “More than Moore” market research and strategy consulting company also presents the technical and market challenges facing WBG players.

wbj materials

As the Si technology is reaching the theoretical limits, new semiconductor materials called wide band gap (WBG) is becoming the new choice for power electronics applications. Different WBG materials are SiC, GaN, Ga2O3, Diamond and AlN. The development status of these WBG materials varies from one to other. Indeed SiC and GaN-on-Si based power devices are commercially available today; the development of GaN-on-GaN power devices is ongoing; Ga2O3, diamond and AlN power devices are just at a primitive stage. And Yole details:

•  Thanks to its high band gap and doping possibility at room temperature, Ga2O3 has been proposed for power electronics applications. Compared to existing SiC and bulk GaN technology, GaSO3 key selling point is the possibility of using melt growth to make large, inexpensive wafers. Under this process, much little energy is used compared to energy-consuming methods employed for GaN and SiC bulk crystals and substrates creation: sublimation, vapor phase epitaxy, and high-pressure synthesis.

“It is estimated that the power dissipated per-unit-area of substrate at the time of production is just one-third of that associated with SiC sublimation, due to a lower growth temperature and a higher growth rate,” explained Dr. Hong Lin, Technology & Market Analyst at Yole. “As the same system configuration for sapphire is used, it should be possible to make cheaper Ga2O3 substrates than bulk GaN or SiC. If there is demand, it should be also possible to make 6” Ga2O3 substrates at a low unit cost. However, the demand is quite limited so far and the price remains high.”

•  Diamond is the ideal candidate for power electronic applications, thanks to a combination of unique properties. Electronics applications identified by Yole are Schottky diodes, transistors, etc. They require high-quality single-crystalline CVD diamond.

•  Having initially targeted UV LED applications but finding subpar demand, some AlN suppliers are now targeting the power market in order to diversify their activities. AlN’s key value proposition for power applications is the fact that it has the largest band gap.

Under its WBG materials report, Yole’s analysts reveal the state-of-the-art materials like SiC, GaN, Ga2O3, diamond, and AlN. They define a comprehensive technology roadmap and propose a deep understanding of the WBG materials evolution in the power electronics sector.

Applied Materials, Inc. today announced that Dr. Chorng-Ping Chang, who leads the company’s strategic external research with universities and industry consortia, has been named a 2016 IEEE Fellow. Dr. Chang is being recognized for his contributions to “replacement gate and shallow trench isolation for CMOS technology,” which have had a profound impact on the advancement of integrated circuit (IC) fabrication. The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement. The total number selected in any one year cannot exceed one-tenth of one-percent of the total voting membership.

“Chorng-Ping’s brilliant work helped the industry adopt novel methods in CMOS scaling and made important contributions to the performance, functionality and size of the electronic products we use every day,” said Dr. Om Nalamasu, senior vice president and CTO of Applied Materials. “I commend him on this well-deserved honor and for his efforts leading Applied Materials’ collaborations with universities and consortia.”  

Dr. Chang’s outstanding technical contributions and extensive semiconductor industry community service span nearly three decades. While working at Bell Laboratories he led pioneering research that helped the industry through one of the most significant transitions in the history of CMOS technology – the shift from the gate-first to the gate-last (replacement gate) process. His work on extending the use of replacement gate technology continued at Applied Materials, and today virtually all state-of-the-art CMOS logic devices, including FinFET transistors, use replacement gate technology. In addition, early on in his career Dr. Chang made pivotal contributions in deposition, etching and advanced plasma processing technologies.

Another critical area where Dr. Chang made significant contributions is advanced shallow trench isolation (STI). He led an early detailed study that demonstrated how changing the shape of the top trench corners helped resolve serious issues of defect density, junction leakage and device threshold voltage control. This research had a long-term impact on the robustness and extendibility of STI in mainstream CMOS manufacturing, to the extent that major CMOS process technologies introduced in recent years have used STI corner engineering techniques developed by Dr. Chang and his team.

Dr. Chang has served the IEEE community in several facets throughout his career, including as editor of IEEE Electron Device Letters for 12 years. He has also been a member of the program committees of various international technical conferences on IC technology, and is currently the U.S. Chair of the International Technology Roadmap for Semiconductors (ITRS) Process, Integration, Devices and Structures Chapter. Dr. Chang holds a bachelor’s degree from National Tsing Hua University and a Ph.D. in engineering from the University of California, Berkeley.

Due to the further scaling and increasing complexity of transistors, the boundaries between back-end-of-line and front-end-of-line reliability research are gradually fading. Imec’s team leaders Kristof Croes and Dimitri Linten give their vision on the future of reliability research.

In April 2015, the 53rd edition of the IEEE International Reliability Physics Symposium (IRPS) took place, a top conference where experts in reliability of micro- and nanoelectronics meet. With 16 contributions as either an author or a co-author, imec was prominently present.

Dimitri Linten: “Our contributions to conferences such as IRPS highlight the unique role that imec plays in the field of reliability. And they show the importance of reliability research at imec for the development of new transistor and memory concepts. As scaling continues, a whole range of new technology options is being researched. New materials and architectures with often unknown failure mechanisms are being introduced. Reliability is one of the factors that determine which concept will finally have a chance. For example, one of the options is to replace silicon in the transistor’s channel by germanium or a III/V material since these materials provide a higher charge carrier mobility. But until now, these materials pose important challenges to the reliability of the transistors that are made of these materials. Or, researchers look at introducing either air gaps or ultralow-k materials as spacers between the transistor’s gate and drain in order to keep the capacity as low as possible. The integration of all these new materials is important, but their reliability is crucial as well: reliability before performance.”

Front of line Fig 1

Kristof Croes: “10 years ago, reliability was tested only in a final stage of a technology development. But due to the ever decreasing reliability margins, the reliability is now being tested from the very beginning. And this starts with an understanding of the physics behind the failure, for which we often collaborate with universities. Once we understand the failure of e.g. new materials, we can model our findings and predict the lifetime of the device.”

Front-end-of-line vs back-end-of-line

Traditionally, CMOS process engineers classify the semiconductor process in two main parts: the front-end-of-line (FEOL) and the back-end-of-line (BEOL). The FEOL comprises all the process steps that are related to the transistor itself, including the gate of the transistor. The BEOL comprises all subsequent process steps. In the BEOL, the various transistors are being interconnected through metal lines. The same classification is being used in reliability research. Consequently, FEOL and BEOL reliability is tested independently.

Kristof Croes: “This historical separation is being applied at imec as well, where reliability research within the process technology division is distributed among several groups. One group looks into the reliability of FEOL and memory chips. Another group investigates the BEOL reliability and chip packaging interaction. Today, in BEOL processes, electromigration (the movement of metal atoms as a result of an electric current), stress migration, time dependent dielectric breakdown (TDDB) and thermomechanical stress are the main failure mechanisms. We also look into 3D structures, where the impact and reliability of through-Si vias are important issues. In a 3D-stacked structure, for some applications, the Si wafer needs to be thinned down to about 5 micrometer. And this impacts the reliability. And there are thermal and thermo-mechanical influences related to the assembly of materials with completely different mechanical properties. All these failure mechanisms in the BEOL will become increasingly important for future technology nodes.”

Dimitri Linten: “We look into the time dependent breakdown (TDDB) of the gate stack, and into stress-induced leakage current (SILC) and hot carrier stress (HC). The bias temperature instability (BTI) is important as well, as it causes a shift of the threshold voltage (VT) of the transistor during the lifetime of the circuit. We also investigate memory elements, by testing and modelling the retention and endurance of the memories. ESD or electrostatic discharge is still one of the main important failure mechanisms at the level of the final ICs in a certain technology. In order to intercept the current that is released during an electrostatic discharge, protecting ESD structures are implemented in the FEOL.”

Front of line Fig 2

FEOL and BEOL reliability: fading boundaries

As the dimensions of the transistor shrink, the impact of the FEOL on the BEOL reliability – and vice versa – increases. Kristof Croes: “A well-known example is self-heating in FinFETs. In planar CMOS processes, the heat that is released during the transistor’s operation is dissipated mainly through the Si substrate. But in a FinFET architecture, we have to take into account a higher thermal coupling towards the metal intercon- nects. The FinFETs warm up and heat the metal lines. And this impacts the reliability of the BEOL structure. In 3D technology, we thin down wafers with TSVs. After opening the TSVs, we can stack them on top of another wafer. The integration of the TSVs, the thinning and stacking of the wafers influence both the FEOL and the BEOL performance and reliability.”

Dimitri Linten: “Also the introduction of new architectures brings the reliability of FEOL and BEOL closer to each other. Think about vertical nanowires, potential successors of the FinFET because they promise a better electro- static channel control. One of the challenges in terms of reliability is to provide these structures with an ESD protection. While in more conventional structures, the FEOL is most sensitive to electrostatic discharge, the impact of electrostatic discharge on the BEOL becomes critical in vertical nanowires. In these 3D structures, we have to connect all the vertical nanowires through local interconnects and interconnects that will be located very close to each other. And these interconnects will put other requirements to the ESD protection circuit than we are used to. A possible solution is to consider a 3D stacking of ESD protection circuits on top of the transistor architecture.”

Another consequence of further scaling is an increase in the variability of the transistor parameters. In FEOL, variability is a well-known phenomenon.

Dimitri Linten: “Time dependent variability of BTI is a relatively new challenge for reliability research. For large transistors – the older generations – BTI translates into an average shift of the circuit’s threshold voltage of e.g. 50mV, the spec for BTI. But upon further scaling, there is no average shift anymore. Instead, there will be a static distribution of shifts. The variability becomes time dependent and the lifetime of the circuits will be spread. The imec FEOL reliability group is a world leader in this domain: we have developed a defect centric BTI model that has been adopted by market leaders in the semiconductor industry. On time dependent BTI, we closely collaborate with the design group in order to develop methodologies that take into account the time dependence.”

Kristof Croes: “Also in BEOL, variability becomes increasingly important. Think about via misalignment or line edge roughness of increasingly smaller metal lines. These issues degrade the reliability and the lifetime of the BEOL. To deal with the increasing variability, a powerful statistical toolbox is required. And this toolbox can be deployed for BEOL as well as for FEOL reliability research.”

Front of line Fig 3

When BEOL meets FEOL reliability

As dimensions are shrinking, the boundaries between FEOL and BEOL reliability are gradually fading.

Kristof Croes: “We are convinced that we should optimally attune the activities and tools used for reliability research. We have to bring the people from BEOL and FEOL reliability closer together. And we want to unite the researchers outside these groups that work on reliability. Reliability is a field of expertise and sharing problems often provides part of the solution. For future technology nodes and for develop- ments beyond scaling, this will increase the operational efficiency of reliability research. To strengthen this idea, we will organize an internal workshop at imec on September 4, with the help of our predecessors and colleagues Guido Groeseneken and Ingrid De Wolf. This will help our researchers to gain more insight into each other’s work and into the tools they use. Hopefully, this idea will be adopted outside of imec as well.”

Additional reading

Technical program of the 2015 IRPS conference with abstracts (http://www.irps.org/program/technical-program/15-program.pdf)

“New test allows to visualize in real-time crack formation of BEOL,” March issue of imec magazine (http://magazine.imec.be/data/57/ reader/reader.html#preferred/1/package/57/pub/63/page/2)

At this week’s IEEE International Electron Devices Meeting 2015, nano-electronics research center imec presented breakthrough results to increase performance and improve reliability of deeply scaled silicon CMOS logic devices.

Continued transistor scaling has resulted in increased transistor performance and transistor densities for the last 50 years. With transistor scaling reaching the critical limits of atomic dimensions, imec’s R&D program on advanced logic scaling targets the new and mounting challenges for performance, power, cost, and density scaling to future process technologies. Imec is looking into extending silicon CMOS technology by tackling the detrimental impact of parasitics on device performance and reliability, and by introducing novel architectures such as gate-all-around nanowires, that are considered to improve short channel control.

One of the achievements is a record low contact resistivity of 1.5 Ωcm2 for n-Si that was realized by combing dynamic surface anneal (DSA) to enhance P activation in highly-doped Si:P, with Ge pre-amorphisation and Ti silicidation. Imec also presented a decreased access resistance in NMOS Si bulk finFETs by applying extension doping by phosphorus doped silicate glass (PSG) to achieve damage free and uniform sidewall doping of the fin. Finally, imec introduced junction-less high-k metal-gate-all-around nanowires to improve on- and off-state hot carrier reliability.

“I am extremely proud with the record number of 23 papers that we present at this year’s IEDM2015,” stated Luc Van den hove, President and CEO at imec. “Our presence rewards and confirms our leading position in advanced semiconductor R&D. As much as 10 of the presented papers concerned the different aspects of our advanced logic program. Next to our research efforts to extend silicon CMOS technology into 7nm technology node and beyond. We are looking into beyond silicon CMOS, integrating high mobility materials to increase the channel mobility, and explore new concepts beyond silicon such as spintronics and 2D materials.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

Cross-section of JL nanowires with or without an acceptor type interface, cut along the middle of the gate. The electrostatic potential is asymmetric when a trap is introduced; the squeezed channel improves the electrostatics and the subthreshold slope.

Cross-section of JL nanowires with or without an acceptor type interface, cut along the middle of the gate. The electrostatic potential is asymmetric when a trap is introduced; the squeezed channel improves the electrostatics and the subthreshold slope.

CEA-Leti today announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed at the same, or lower, power consumption, and improve performance.

The local-strain solutions are dual-strained technologies: compressive SiGe for PFETs and tensile Si for NFETs. In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing.

The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel.

The first relies on strain transfer from a relaxed SiGe layer on top of SOI film. In a recent paper in the ECS Journal of Solid State Science and Technology, Leti researcher Sylvain Maitrejean described how with this technique he was able to boost the short-channel electron mobility by more than 20 percent compared to unstrained reference. This shows significant promise for enhancing the on-state currents of CMOS transistors and thus for improving the circuit’s speed.

The second technique is closer to strain memorization methods and relies on the ability of the BOX to creep under high-temperature annealing. At SSDM 2015 in Japan, Leti researchers showed that with this local-stress technique they can turn regular unstrained SOI structures into tensile strained Si (sSOI), for NFET areas. Moreover, this “BOX-creep” process also can also be applied to compressive strain creation, as presented at the 2015 Silicon Nanoelectronics Workshop (SNW) conference.

Strained channels enable an increase in the on-state current of CMOS transistors. As a result, the corresponding IC circuits can deliver more speed at the same power, or reduced consumed power and longer battery life at the same performance.

They also have been proven to be an effective way to increase performance of n and p MOSFET transistors via mobility enhancement of electrons and holes. These kinds of techniques enable boosting of the carrier transport in the CMOS channels, and thus increasing the on-state currents. Beginning with the 90nm node, this strain option has been one of the main approaches of the microelectronics industry for improving the IC speed in bulk transistors. While it was not necessary at the 28nm node for FD-SOI, it becomes mandatory beyond the 22/20nm node.

“Leti has continuously focused on improving and fine-tuning FD-SOI technology’s inherent advantages, since pioneering the technology 20 years ago,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory. “These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future.”

SSDM 2015: Stress profile from 2D Raman extractions for Si MESAs after BOX creep process with 50nm thick SiN

SSDM 2015: Stress profile from 2D Raman extractions for Si MESAs after BOX creep process with 50nm thick SiN

CEA-Leti today announced preliminary steps for demonstrating a quantum bit, or qubit, the building block of quantum information, in a process utilizing a silicon-on-insulator (SOI) CMOS platform.

While the leading solid-state-based approach today for treating quantum information uses superconducting qubits, there are several potential alternatives. These include semiconductor spin qubits, historically demonstrated in III-V materials, but with limited “lifetime” due to coupling between the electron spin and the nuclear spins of the III-V elements.

Only in recent years has the prospect of using nuclear spin-free, isotopically purified silicon-28, the most-common isotope, made silicon an especially attractive candidate for hosting electron spin qubits with a long quantum coherence time. The main challenge now is defining an elementary cell compatible with circuit upscaling to hundreds of qubits and more.

Leti and its long-time research partner Inac, a fundamental research division of CEA, are investigating a silicon-on-insulator (SOI) technology for quantum computing with proven scalability, since it was originally developed for CMOS VLSI circuits. In this approach, quantum dots are created beneath the gates of n-type (respectively p-type) field effect transistors, which are designed to operate in the “few-electron” (respectively “few-hole”) regime at cryogenic temperatures (below 0.1 K).

Leti and Inac have developed a process for mastering control of the operation of both types of devices using Leti’s SOI nanowire FET technology. Their teams have demonstrated the co-integration and successful operation of quantum objects with conventional CMOS control electronics (standard ring oscillators) on 300mm SOI substrates.

“This technology has acquired a certain degree of robustness, and we aim at using it with very minor modifications to demonstrate qubits co-integrated with their control electronics,” said Louis Hutin, scientific staff. “This co-integration success represents a critical asset for the eventual design of a quantum computer.”

Cambridge CMOS Sensors (CCS), a semiconductor company with gas sensor solutions to monitor the local environment, today announced that it has been crowned winner of the Product of the Year category at this year’s National Microelectronics Institute (NMI) Awards, held at the Grange Tower Bridge Hotel in London.

CCS was awarded the Product of the Year award for their excellent approach to understanding market needs, customer acceptance and reliability methodology for their CCS801 sensor for Indoor Air Quality Monitoring. This is the second successive year that CCS have been honoured in the annual NMI Awards, after winning last year’s Innovation Award.

The 2015 NMI awards are designed to celebrate the year’s key electronics innovations, people and companies from across the UK and Ireland. It has been run as an annual event since 2001. The fourteen categories also included awards such as Manufacturing Supplier of the Year, University Research Group of the Year, Company of the Year and Research Collaboration Award.

Nat Edington, CEO, at CCS said, “We are honoured to have received this award and to be recognised by NMI for the second year in a row. The past 12 months have been a transformational period for CCS and everyone has worked incredibly hard to ensure we capitalise on the great opportunities in front of us. I would like to thank all of our employees for their efforts, which have enabled us to win this award.”

Vacuum technology trends can be seen over the period of innovation defined by Moore’s Law, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling.

BY MIKE CZERNIAK, Edwards UK, Crawley, England

The sub-fab lies beneath. And down there in that thicket of pipes amidst the hum of vacuum pumps, the sentinel of gas combustors and the pulse of muscular machinery doing real work — innovation has also played a crucial role in enabling Moore’s Law. Without it the glamor boys up top with their bunny suits and FOUPS would not have achieved the marvelous feats of engineering derring-do for which they are so deservedly celebrated.

Vacuum and abatement are two of the most critical functions of the sub-fab. Many process tools require vacuum in the process chamber to permit the process to function. Vacuum pumps not only provide the required vacuum, they also remove unused process gases and by-products. Abatement systems then treat those gasses so they are safe to release or dispose. Vacuum and abatement systems in the sub-fab have had to innovate just as dramatically as the exposure, deposition and etch tools of the fab. In many cases, new processes would not have been possible without new vacuum pumps that could handle new materials and new abatement systems that could make those materials safe for release or disposal.

Moore’s Law

Moore’s Law originated in a paper published in 1965 and titled “Cramming More Components onto Integrated Circuits,” written by Gordon Moore, then director of research and engineering at Fairchild Semiconductor [1]. In it Moore observed that the economics of the integrated circuit manufacturing process defined a minimum cost at a certain number of components per circuit and that this number had been doubling every two years as the manufacturing technology evolved. He believed that the trend would continue for at least the short term, and perhaps as long as ten years. His observation became a mantra for the industry, soon to be known as Moore’s Law (FIGURE 1).

Vaccuum 1

More an astute observation than a law, Moore’s Law is remarkable in several respects. First, the rate of improvement it predicts, doubling every two years, is unheard in any other major industry. In “Moore’s Curse” (IEEE, March 2015) Vaclav Smil calculated historical rates of improvement for a variety of essential indus- tries over the last couple of centuries and found typical rates of a few percent, and order of magnitude less than Moore’s rate [2]. Second, is its longevity. Moore thought it was good for the short term, perhaps as long as ten years. This is perhaps due, at least partly, to the unique role Moore’s Law has assumed within the semicon- ductor industry where it has become both a guide to and driver of the pace of innovation. The Law has become a guiding principle – you shall introduce a new generation with double the performance every two years. It is a rule to live by, enshrined in the industry’s roadmap, and violated only at great peril. Only painfully did Intel recently admit that the doubling period for its latest generation appeared to have stretched to something more like two and a half years [3]. To an extent the Law is a self-fulfilling prophecy, which some have argued works to the detriment of the industry when it forces the release of new processes before they are fully optimized. Whatever you might think of it, the Law’s persistence is remarkable. The literature is full of dire predictions of its demise, all of which, at least so far, have proven premature.

Finally we must ask, what is meant by the names assigned to each new node? What exactly does 14nm, the current state of the art, mean? Although Moore originally described the number of components per integrated circuit, the Law was soon interpreted to apply to the density of transistors in a circuit. This was variously construed. Some measured it as the size of the smallest feature that could be created, which determined the length of the transistor gate. Others pointed to the spacing between the lines of the first layer of metal conductors connecting the transistors, the metal-1 half-pitch. These may have been a fairly accurate measures twenty years ago at the 0.35μm node, but node names have since steadily lost their connection to physical features of the device. It would be difficult to point to any physical dimension at the 14nm node that is actually 14nm. For instance, the FinFET transistor in a 22nm chip is 35nm long and the fin is 8nm wide.

What remains true is that in each successive generation the transistors are smaller and more densely packed and performance is significantly increased. Each generation seems to be named with a smaller number that is approximately 70% of the previous generation, reflecting the fact that a 70% shrink in linear dimension equates to a 50% reduction in area and therefore a nominal doubling in transistor density.

Enabling Moore’s Law in the sub-fab: A brief chronology

In the 1980s, new semiconductor processes and increasing gas flows associated with larger diameter wafers led to problems with aggressive chemicals and solids collecting in the oil used in oil-lubricated “wet” pumps, resulting in short service intervals and high cost of ownership. These were resolved by the development and introduction of oil-free “dry pumps” which have subsequently become the semiconductor industry standard.

Dry rotary pumps require extremely tight running clearances and multiple stages to achieve a practical level of vacuum. Additional cost of these machines, however was more than offset by the benefits offered to semiconductor manufacturing. Dry pumps use a variety of pumping mechanisms — roots, claw, screw and scroll (FIGURE 2).

Vaccuum 2

Many of these are new concepts, but modern machining capabilities made it possible to produce them at a realistic cost, the most notable being Edwards’ introduction of the first oil-free dry pump in the 1980’s. Each pumping mechanism has been successfully deployed and each has its own advantages and disadvantages in a given application. The scroll pump, for example, is unique in its ability to economically scale down to much smaller sizes.

In the early 1990s it became apparent that with the introduction of dry pumps, the pump oil no longer acted as a “wet scrubber” to collect process by-product gases, which therefore passed into the exhaust system. The solution was the development of the Gas Reactor Column (GRC) to chemically capture process exhaust gases in a disposable/recyclable cartridge, minimizing exhaust emissions to the atmosphere.

At about the same, new, more aggressive process gases being used in leading-edge semiconductor processes posed significant challenges for turbo molecular pumps (TMPs) due to the damage they caused to the mechanical bearings used to support their high-speed rotating shafts (typically ~40,000 rpm). Turbo pumps use rapidly spinning blades to impart direction to gas molecules, propelling them through multiple stages of increasing pressure. Early turbo pumps used oil- or grease-lubricated bearings. Similar to the problems encountered with oil sealed rotary pumps, the new process chemicals tended to degrade the oil, frequently causing pumping failures in as little as a few weeks. This problem was solved by introducing magnetic bearings to levitate the pump drive shaft and eliminate the need for lubricating oil.

In the mid-1990s the semiconductor industry started to use perfluorinated compounds (PFC’s) as a convenient source of chamber cleaning and etch gases. However, since only ~30% of the input gas was consumed in the process chamber, there were considerable PFC emissions to the atmosphere. Of particular concern was CF4 due to its half-life of 50,000 years. The solution was the Thermal Processor Unit which offered the first system with proven destruction reaction efficiency (DRE) of 90% or more for CF4.

In the 2000’s safety concerns regarding the increasing use of toxic gases led to increasing concerns about the abatement of these materials before they were released to the environment and the safety of personnel within the fab. Integrated vacuum and abatement systems, where everything is contained in a sealed and extracted enclosure, offer a significant improvement in safety. Integrated systems have since been refined with improvements such as a common control system, reduced footprint and installation costs, and shorter pipelines to reduce operating and maintenance costs.

Abatement systems have continued to evolve. New processes using new materials often require a different approach the abatement. For example, new technologies were developed for high hydrogen processes, copper interconnects and low k dielectrics.

Trends and prospects

Certain vacuum technology trends can be seen over this history of innovation, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling to monitor performance and predict when maintenance will be required so that it can be synchronized with other activities in the fab.

Shaft Speed

When dry pumps were first introduced, they typically operated at around 3,000 to 3,600 rpm. Today’s dry pumps use electric drives to run considerably faster, typically 6,000 rpm for claw, screw, and multi-stage roots pumps (FIGURE 3).

Vaccuum 3

Increasing a pump’s rotational speed delivers a number of advantages. It makes it possible to build more compact pumps and motors, with less internal leakage, which in turn, enables a reduction in the number of pump stages required. It also allows the speed to be reduced when wafers are not being processed, thereby saving energy. Combined, these benefits help reduce the overall pump cost.

Each type of pumping mechanism has different characteristics in the size and shape of volume to fill. A scroll mechanism, with a narrow, ported inlet and long, thin volume space, is one of the slowest pumping mechanisms to fill, so its performance does not increase in proportion to increasing shaft speed. Most scroll pumps operate at just 1500 rpm. A roots mechanism, by contrast, has a very large opening and a short volume length, enabling it to fill quickly allowing efficient use of higher shaft speeds.

The conductance ceiling for roots and screw pumps is probably ~15,000 rpm. Achieving this speed, will require incremental improvements in materials, bearings, and drives. It is likely that we will reach the conductance ceiling for most of the current primary pumping mechanisms within the next decade, although some, such as roots and screw mechanisms, may prove more durable than others.

Turbomolecular pump conductance is governed by blade speed and molecular velocities. Turbo performance has been limited primarily by the maximum speed the bearings and rotor can withstand. The industry is looking for new materials that are lighter and stronger to enable increased speed. While this pump type may be reaching its conductive limit on heavier gases, it is far from reaching it for lighter gases, such as hydrogen. This may take a much longer time to achieve.

Power management

Significant advances have been made in improving the energy efficiency of both vacuum pumps and abatement systems. Improvements in pump design have increased energy efficiency. Variable speed motors and controllers allow better matching of the motor speed to varying pump requirements. Idle mode allows both pumps and abatement systems to go into a low power mode when not in use. Improvements in burner design have reduced the fuel consumption of combustion based abatement. With the increase in concern about environmental impact and carbon foot print continued improvement in this area can be expected.

Modeling

Computer modeling has been applied extensively to all stages of pump performance. Such variables as stage size, running clearance, leakage, and conductance can all be modeled quite effectively. This allows design simulation and the optimization of performance, such as the shape of the power and speed curve. In this way, a pump can be designed for specific duties, such as load lock pumping or processing high hydrogen flows (FIGURE 4).

Vaccuum 4

Vacuum pumps of the future will be more reliable and capable of operating for longer periods of time before requiring maintenance. They will be safer to operate, will occupy less fab space, run cleaner and require less power, as well as generate less noise, vibration, and heat. They will also have improved corrosion resistance and the ability to run hotter when required.

As a result, vacuum pumps will be more environmentally friendly, running cleaner and using less power to help reduce their carbon footprint. In addition, they will likely make much greater use of recycled materials and use fewer consumables, thereby helping to reduce overall pump costs. The pumps will be easier to clean, repair, and rebuild for reuse.

Likely technical developments will also include higher shaft speeds, a growing proliferation of pump mechanisms and combinations of mechanisms to increase performance. Finally, vacuum pumps will incorporate new materials and improved modelling to further sharpen performance and reduce system and operating costs.

References

1. G. Moore, “Cramming more Components onto Integrated Circuits” in Electronics, April 19, 1965.
2. V. Smil, “Moore’s Curse” in IEEE Spectrum, March 19, 2015.
3. R. Courtland, “The Status of Moore’s Law: It’s Complicated” in IEEE Spectrum October 28, 2013.

MIKE CZERNIAK is the Environmental Solutions Business Development Manager, Edwards UK, Crawley, England.

Recent trends and future directions for wafer bonding are reviewed, with a focus on MEMS.

BY ERIC F. PABO, CHRISTOPH FLÖTGEN, BERNHARD REBHAN, PAUL LINDNER and THOMAS UHRMANN, EV Group, St. Florian, Austria

All devices and products are evaluated to varying degrees on the following factors: 1) availability or assurance of supply, 2) cooling requirements, 3) cost, 4) ease of integration, 5) ease of use, 6) performance, 7) power requirements, 8) reliability, 9) size, and 10) weight. MEMS devices are no exception and the explosive growth of MEMS devices during the last decade was driven by substantial improvements in some of the aforementioned variables. MEMS manufacturing is based on patterning, deposition and etch technologies developed over the last 50 years for the manufacturing of ICs along with the relatively new technologies of aligned wafer bonding and deep reactive ion etch (DRIE). This article will review the recent trends and future directions for wafer bonding with a focus on MEMS along with some mention of wafer bonding for RF and power devices.

The incredible growth in MEMS over the last 20 years has been enabled by the development of the DRIE process by Bosch and by aligned wafer bonding. Many MEMS devices have very small moving parts, which must be protected from the external environment. Initially, this was done using special packages at the die level, which was relatively expensive. Wafer-level capping of MEMS devices seals a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged in a much simpler and lower-cost package. Anodic bonding and glass frit bonding were the initial bonding processes used for MEMS and are often referred to as “tried and true.” However, both of these processes have challenges, and as a result, few new MEMS products and processes are being developed using these processes.

Anodic bonding requires the presence of Na or some other alkali ion which causes several problems. The first is that Na ions are driven to the exterior of the wafer during the bonding process and will accumulate on the bonding tooling, requiring the tooling be cleaned on a periodic basis. The second is that Na can cause CMOS circuits to fail – preventing anodic bonding from being used to combine MEMS and CMOS. Almost all MEMS devices require a CMOS ASIC to process the output signal from the MEMS device. Historically, this integration has been done at the package level with wire bonding but now some high-volume products are available where the integration of the CMOS and the MEMS is done as part of the wafer-level capping process. Also, anodic bonding typically requires a maximum process temperature of over 400 ̊C and the presence of a strong electric field during bonding. The high temperature influences the throughput of the bonding process and some devices cannot tolerate the high electric field.

Even though the majority of the MEMS parts that exist today were probably bonded using glass frit, this wafer bonding process has several challenges as well. The major one is that the glass frit is applied and patterned using a silk screen process, which has a typical resolution in the 250 to 300μm range. This means that as the size of the MEMS die decreases, an ever greater percentage of the wafer surface is consumed by the bond line, which limits the number of die per wafer and increases the cost per die. FIGURE 1 shows the effect of bond line width and die size on the percentage of the wafer surface that is consumed by the bond line [1]. Also, many of the glass frits contain Pb to lower the glass transition temperature. Although the amount of Pb is very small, there is widespread concern regarding the use of Pb and being RoHS (Restriction of Hazardous Substance) compliant.

Wafer bonding 1

 

Both anodic bonding and glass frit bonds are nonconductive and therefore not suitable for the formation of connections to electrically conductive through silicon vias (TSVs) at the same time as the seal ring is formed. This means that these processes are not as suitable for the 3D integration of CMOS and MEMS.

For MEMS applications there is a strong trend toward the use of metal-based wafer bonding; in particular, liquid metal-based processes such as solder, eutectic and transient liquid phase (TLP). This trend is driven by the aforementioned challenges with anodic and glass frit bonding. Moving from glass frit to a metal-based bonding for a die size of 2mm2 can result in up to a 100% increase in the die per wafer. This doubling of the die per wafer will result in an approximately 50% decrease in the cost per MEMS die.

Some of the metal-based aligned-wafer-bonding processes that are currently used in high-volume manufacturing are: Au-Au thermo-compression bonding, which has been in volume production for over 10 years; and Al-Ge eutectic bonding, which is very popular even though it requires a very careful process setup and control and has a peak process temperature of over 400 ̊C. Cu-Sn transient liquid phase (TLP) wafer bonding, another metal-based process, is used in low-volume production of hermetically sealed devices such as micro-bolometers [2] but is not currently used in medium- or high-volume production. Cu-Sn TLP wafer bonding also requires very careful design and control of the metal stack as well as the bonding process.

The maximum process temperature that is required for a bonding process has three significant effects. The first is that the bonding process takes longer as the maximum process temperature increases due to the increased time required to heat up to the bonding temperature from the loading temperature and the time required to cool down to the unload temperature. The bonding process time determines the throughput of the wafer bonder(s) and factors into the cost of ownership (CoO) for the bonding process. The second is that the process temperature required for bonding may damage the devices on the wafers being bonded. The aluminum metallization of certain CMOS devices may be damaged at tempera- tures greater than 450 ̊C. The VOx or vanadium oxide used on the sensor pixels for micro-bolometers will be damaged by temperatures greater than 200 ̊C. The third is the internal stress that is created when wafers with mismatched coefficients of thermal expansion (CTE) are bonded together at an elevated temperature. In this case the higher the bonding temperature, the higher the internal stress at room temperature.

Unless the bonding metals are noble metals such as Au, oxides will form on the metal layer and have a negative effect on the bonding process – making an oxide management strategy necessary. This oxide management strategy can have elements that prevent the oxide from growing using special storage conditions or coatings, removing the oxide before bonding, and heating in an inert or reducing environment. In some cases, the bonding process can also be adjusted to overcome the effect of the oxides by increasing the pressure, temperature and time for the bonding process.

There is substantial interest in bonding processes and equipment that are capable of removing the native oxide from metals and other materials prior to wafer bonding and preventing the regrowth of oxide. Equipment capable of running such a process will have several substantial advantages. The first is that it will allow materials that have been previously difficult to bond to be bonded at or near room temperature. For example, Al-Al thermo-compression wafer bonding without the removal of the native oxide has previously been demonstrated, but required a process temperature of greater than 500 ̊C, which made the process unattractive for production [3]. Low temperature Al-Al thermo-compression bonding has been demonstrated by using a special surface treatment and doing all handling in a high vacuum environment (FIGURE 2). A low-temperature Al-Al thermo-compression bonding process has the advantage of using an inexpensive readily available conductive material and increased throughput due to the low process temperature. In addition to being used to form the seal ring, this low-temperature Al-Al bonding could be used for the 3D integration of MEMS and CMOS through the use of TSVs filled with Al.

Wafer bonding 2

This surface pretreatment and handling in high vacuum enables covalent bonding of two wafers at or near room temperature with no oxide in the interface. This process has several very significant advantages. The first is that the low process temperature allows the bonding of substrates with substantially different CTE such as LiNbO3 or LiTaO3 to Si or glass. This combination of materials has drawn the interest of RF filter manufacturers due to its ability to reduce the temperature sensitivity of surface acoustic wave (SAW) devices. The second is that materials with both a CTE mismatch and a lattice mismatch can be bonded together without the development of major crystalline defects that can arise when forming the material stack by growing one crystalline layer on top of another when there is a lattice mismatch. One interesting possibility is bonding GaN to diamond for applications where large amounts of heat must be removed from the GaN device. In addition, bonding a thin layer of monocrystalline SiC to a polycrystalline SiC could offer wafers with the electrical performance of monocrystalline SiC at a cost closer to the cost of polycrystalline SiC. Another application of this bonding process is to join materials such as GaInP, GaAs, GaInAsP and GaInAs for fabrication of quadruple junction concentrated solar cells with record conversion efficiency of 44.7% [4, 5].

A high-vacuum cluster tool capable of aligned wafer bonding offers significant advantages for MEMS applications where the vacuum level in the cavity after bonding is important, such as gyroscopes and micro-bolometers (FIGURE 3) [6]. Modules can be added to the base cluster tool to enable the wafers to be baked out at a controlled elevated temperature prior to alignment and bonding in high vacuum. Getter activation can also be done in the bake-out module without loading or saturating the getter, as all subsequent steps are done in high vacuum. For devices where getter activation requires a high temperature and the other wafer has thermal limits, two bake-out chambers allow a high-temperate bake-out and getter activation while the other chamber performs a lower-temperature bake out. For example, micro-bolometers that used vanadium oxide on the detector pixel have a thermal limit of about 200 ̊C, whereas the cap wafer contains a getter that should be activated around 400 ̊C. Also, the high-vacuum capability is beneficial for producing devices that are heated and use vacuum for thermal isolation because a higher vacuum reduces the heat loss, which reduces the power required to maintain the fixed temperature.

Wafer bonding 3

This high-vacuum cluster tool allows the separation of the process steps of bake out, surface treatment, alignment and bonding as well as allows the tool to be configured to the specific application needs. Also, the cluster tool base makes it possible to develop modules for specific applications without redesigning the entire tool.

The availability of reliable, highly automated, high-volume aligned wafer bonding systems and processes was one of the keys to the growth of MEMS over the past 15 years. The next 15 years are expected to be an exciting period of advancement for aligned wafer bonding as new equipment and processes are introduced, such as the tools and processes that allow separate pre-processing of the top and bottom wafer, as well as all handling, alignment, and bonding in vacuum. The cluster tools that will be used to do this will allow for further innovation by adding new modules to the cluster tool. In addition, the ability to remove surface oxides prior to bonding, prevent these oxides from reforming, bond at or near room temperature, and have a strong, oxide-free, optically transparent, conductive bond with very low metal contamination will allow many new product innovations for RF filters, power devices and even products that have not yet been thought of.

References

1. E. F. Pabo, “Metal Based Bonding – A Potential Cost Reducer?,” in MEMS MST Industry Conference, Dresden, 2011.
2. A. Lapadatu, “High Performance Long Wave Infrared Bolometer Fabricated by Wafer Bonding,” Proc. SPIE, vol. 7660, no. 766016-12.
3. E.Cakmak,“Aluminum Thermocompression Bonding Characterization,” in MRS Fall Mtg, Boston, 2009.
4. Fraunhofer ISE, Fraunhofer ISE Teams up with EVGroup to Enable Direct Semiconductor Wafer Bonds for Next-Generation Solar Cells, Freiburg: Press Release, 2013.
5. F. Dimroth, “Wafer bonded four-junction GaInP/GaAa/GaInAsP/ GaInAs,” Progress in Photonics, vol. 22, no. 3, pp. 277-282, 2014.
6. V.Dragoi,“Wafer Bonding for Vacuum Encapsulated MEMS,” Proc. SPIE9517 Smart Sensor, Actuators, and MEMS VII, 2015.

ERIC F. PABO is Business Development Manager, MEMS; CHRISTOPH FLÖTGEN, and BERNHARD REBHAN are scientists, PAUL LINDNER is Executive Technology Director and THOMAS UHRMANN is Director Of Business Development at EV Group, St. Florian, Austria

Researchers from RMIT University in Melbourne have helped crack the code to ultra-secure telecommunications of the future in an international research project that could also expedite the advent of quantum computing.

A team co-led by RMIT MicroNano Research Facility Director Professor David Moss has added a new twist to create photon pairs that fit on a tiny computer chip.

Researchers pioneered a new approach to create photon pairs that fit on a computer chip. Credit: RMIT University

The breakthrough, published in Nature Communications, heralds the next-generation of integrated quantum optical technology, being compatible with current technology and secure communications.

The team pioneered a new approach based on a micro-ring resonator – a tiny optical cavity – in which energy conservation constraints can be exploited to suppress classical effects while amplifying quantum processes.

They used laser beams at different wavelengths and then had to overcome the risk of the two pump beams being able to destroy the photons’ fragile quantum state.

“One of the properties of light exploited within quantum optics is ‘photon polarization’, which is essentially the direction in which the electric field associated with the photon oscillates,” Moss said.

“Processes used to generate single photons or photon pairs on a chip allow the generation of photons with the same polarization as the laser beam, forcing us to find a way to directly mix, or cross-polarize, the photons via a nonlinear optical process on a chip for the first time.”

Moss worked with Professor Roberto Morandotti at the INRS-EMT in Canada and researchers from the University of Sussex and Herriot Watt University, City University of Hong Kong, and the Xi’an Institute in Chin, on the research.

“While a similar suppression of classical effects has been observed in gas vapours and complex micro-structured fibres, this is the first time it has been reported on a chip, opening a route for building scalable integrated devices that exploit the mixing of polarization on a single photon level,” he said.

“It also has the advantage that the fabrication process of the chip is compatible with that currently used for electronic chips which not only allows the exploitation of the huge global infrastructure of CMOS foundries, but will ultimately offer the potential to integrate electronic devices on the same chip.

“Both of these are fundamental requirements for the ultimate widespread adoption of optical quantum technologies.”