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Micron Technology, Inc. this week announced the production of 8GB DDR4 NVDIMM, the company’s first commercially available solution in the persistent memory category. Persistent memory delivers a unique balance of latency, bandwidth, capacity and cost, delivering ultra-fast DRAM-like access to critical data and allowing system designers to better manage overall costs. With persistent memory, system architects are no longer forced to sacrifice latency and bandwidth when accessing critical data that must be preserved.

As data centers evolve to handle the massively growing influx of data, the cost of moving data and storing it away from the CPU becomes increasingly prohibitive, creating the need for a new generation of faster, more responsive solutions. Persistent memory, a new addition to the memory hierarchy, allows greater flexibility in data management by providing non-volatile, low latency memory closer to the processor. With NVDIMM technology, Micron delivers a persistent memory solution capable of meeting many of today’s biggest computing challenges.

Micron’s NVDIMM begins to address some of the difficult architectural challenges facing CIOs today, and is ideal for applications such as big data analytics, storage appliances, RAID cache, In-Memory Databases and On Line Transaction Processing. Traditional memory architectures force system architects to sacrifice latency or bandwidth needed to access the critical data for these applications, and as a result, performance is often limited by I/O bottlenecks. Micron’s NVDIMM solutions deliver architectures suited to meet the demands of applications that require high performance coupled with frequent access to large data sets while being sensitive to down time. In the event of a power failure or system crash, Micron’s NVDIMM solution provides an onboard controller that safely transfers data stored in DRAM to the onboard non-volatile memory, preserving the data that would otherwise be lost.

“Micron is delivering on the promise of persistent memory with a solution that gives system architects a new approach for designing systems with better performance, reduced energy usage and improved total cost of ownership,” said Tom Eby, vice president for Micron’s compute and networking business unit. “With NVDIMM, we have a powerful solution that is available today. We’re also leading the way on future persistent memory development by spearheading R&D efforts on promising new technologies such as 3D XPoint memory, which will be available in 2016 and beyond.”

Persistent memory: A new architecture for the new data age

Micron’s NVDIMM technology is a non-volatile solution that combines NAND flash reliability, DRAM performance and an optional power source into a single memory subsystem, delivering a powerful solution that ensures data stored in memory is protected against power loss. By placing non-volatile memory on the DRAM bus, this new architecture allows customers to store data close to the processor and significantly optimize data movement by delivering faster access to variables stored in DRAM.

“Persistent memory is a critical new technology to move computing forward. The amount of information that can be found in data produced by today’s organizations requires a platform with the performance abilities to more efficiently store, manage and analyze large data sets frequently and quickly,” said Greg Wong, founder and principal analyst at Forward Insights. “Micron’s NVDIMM technology is a positive step in this direction, delivering a solution that fills a gap in the current memory hierarchy right now.”

Additional Resources:

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

WEST LAFAYETTE, Ind. — Silver nanowires hold promise for applications such as flexible displays and solar cells, but their susceptibility to damage from highly energetic UV radiation and harsh environmental conditions has limited their commercialization.

New research suggests wrapping the nanowires with an ultrathin layer of carbon called graphene protects the structures from damage and could represent a key to realizing their commercial potential.

“We show that even if you have only a one-atom-thickness material, it can protect from an enormous amount of UV radiation damage,” said Gary Cheng, an associate professor of industrial engineering at Purdue University.

The lower images depict how graphene sheathing protects nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, an intensity that vaporizes the unwrapped wires. The upper images depict how the unwrapped wires are damaged with an energy intensity as little as .8 megawatts per square centimeter. (Purdue University image)

The lower images depict how graphene sheathing protects nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, an intensity that vaporizes the unwrapped wires. The upper images depict how the unwrapped wires are damaged with an energy intensity as little as .8 megawatts per square centimeter. (Purdue University image)

Devices made from silver nanowires and graphene could find uses in solar cells, flexible displays for computers and consumer electronics, and future “optoelectronic” circuits for sensors and information processing. The material is flexible and transparent, yet electrically conductive, and is a potential replacement for indium tin oxide, or ITO. Industry is seeking alternatives to ITO because of drawbacks: It is relatively expensive due to limited abundance of indium, and it is inflexible and degrades over time, becoming brittle and hindering performance, said Suprem Das, a former Purdue doctoral student and now a postdoctoral researcher at Iowa State University and The Ames Laboratory.

However, a major factor limiting commercial applications for silver nanowires is their susceptibility to harsh environments and electromagnetic waves.

“Radiation damage is widespread,” said Das, who led the work with Purdue doctoral student Qiong Nian (pronounced Chung Nee-an). “The damage occurs in medical imaging, in space applications and just from long-term exposure to sunlight, but we are now seeing that if you wrap silver nanowires with graphene you can overcome this problem.”

Findings appeared in October in the journal ACS Nano, published by the American Chemical Society. The paper was authored by Das; Nian; graduate students Mojib Saei, Shengyu Jin and Doosan Back; previous postdoctoral research associate Prashant Kumar; David B. Janes, a professor of electrical and computer engineering; Muhammad A. Alam, the Jai N. Gupta Professor of Electrical and Computer Engineering; and Cheng.

Raman spectroscopy was performed by the Purdue Department of Physics and Astronomy. Findings showed the graphene sheathing protected the nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, which vaporizes the unwrapped wires. The unwrapped wires were damaged with an energy intensity as little as .8 megawatts per square centimeter. (The paper is available at http://pubs.acs.org/doi/abs/10.1021/acsnano.5b04628.)

“It appears the graphene coating extracts and spreads thermal energy away from the nanowires,” Das said. The graphene also helps to prevent moisture damage.

The research is a continuation of previous findings published in 2013 and detailed in this paper: http://onlinelibrary.wiley.com/doi/10.1002/adfm.201300124/full. The work is ongoing and is supported by the National Science Foundation and a National Research Council Senior Research Associateship.

Santa Clara, Calif. — November 5, 2015 — GLOBALFOUNDRIES today announced it has demonstrated silicon success on the first AMD products using GLOBALFOUNDRIES’ most advanced 14nm FinFET process technology. As a result of this milestone, GLOBALFOUNDRIES’ silicon-proven technology is planned to be integrated into multiple AMD products that address the growing need for high-performance, power-efficient compute and graphics technologies across a broad set of applications, from personal computers to data centers to immersive computing devices.

AMD has taped out multiple products using GLOBALFOUNDRIES’ 14nm Low Power Plus (14LPP) process technology and is currently conducting validation work on 14LPP production samples.  Today’s announcement represents another significant milestone towards reaching full production readiness of GLOBALFOUNDRIES’ 14LPP process technology, which will reach high-volume production in 2016. The 14LPP platform taps the benefits of three-dimensional, fully-depleted FinFET transistors to enable customers like AMD to deliver more processing power in a smaller footprint for applications that demand the ultimate in performance.

“FinFET technology is expected to play a critical foundational role across multiple AMD product lines, starting in 2016,” said Mark Papermaster, senior vice president and chief technology officer at AMD. “GLOBALFOUNDRIES has worked tirelessly to reach this key milestone on its 14LPP process. We look forward to GLOBALFOUNDRIES’ continued progress towards full production readiness and expect to leverage the advanced 14LPP  process technology across a broad set of our CPU, APU, and GPU products.”

“Our 14nm FinFET technology is among the most advanced in the industry, offering an ideal solution for demanding high-volume, high-performance, and power-efficient designs with the best die size,” said Mike Cadigan, senior vice president of product management at GLOBALFOUNDRIES. “Through our close design-technology partnership with AMD, we can help them deliver products with a performance boost over 28nm technology, while maintaining a superior power footprint and providing a true cost advantage due to significant area scaling.”

GLOBALFOUNDRIES’ 14LPP FinFET is ramping with production-ready yields and excellent model-to-hardware correlation at its Fab 8 facility in New York. In January, the early-access version of the technology (14LPE) was successfully qualified for volume production, while achieving yield targets on lead customer products. The performance-enhanced version of the technology (14LPP) was qualified in the third quarter of 2015, with the early ramp occurring in the fourth quarter of 2015 and full-scale production set for 2016.

Today, in conjunction with the 41st International Symposium for Testing and Failure Analysis (ISTFA), DCG Systems® announced the release of EBIRCH™, a new, unique technology for localizing shorts and other low-resistance faults that may reside in the interconnect structures or the polysilicon base layer of integrated circuits. Named for Electron Beam Induced Resistance Change, EBIRCH offers fault analysis (FA) engineers and yield experts the ability to detect and isolate low-resistance electrical faults without resorting to brute-force binary search approaches that rely on successive FIB* cuts. Its unparalleled ability to quickly isolate low-resistance faults enables EBIRCH to boost the success rate of physical failure analysis (PFA) imaging techniques to well above 90%, accelerating time-to-results and establishing the FA lab as a critical partner organization in solving yield and reliability problems.

“At foundries and IDM* fabs, the process has become more difficult to control using traditional inline measures,” said Mike Berkmyre, business unit manager of the Nanoprobing Group at DCG Systems. “More yield issues are remaining undetected until they show up at final test — and land on the desk of the FA lab manager. The FA engineers must be equipped to localize the fault and supply images of the root cause to process or yield engineers in a timely manner. The ability to quickly and reliably localize low-resistance faults was missing before we developed EBIRCH. With the introduction of EBIRCH, we are helping to solve an FA problem that has been growing in prevalence and importance with each new device node.”

Available on DCG’s current SEM*- based nanoprobing systems, EBIRCH offers the following capabilities:

  • Detects and isolates electrical faults with resistances from < 10 ohm to > 50 Mohm;
  • Finds faults at surface and several levels below concurrently, significantly accelerating the existing work flow; and
  • Can scan areas as large as 1mm by 1mm, and zoom in to areas as small as 50nm by 50nm, providing accurate and actionable fault localization within minutes.

To collect an EBIRCH image, the operator lands two nanoprobes on surface metal layers, straddling the suspected defect site. A bias is applied, and the electron beam rasters across the region of interest. As the e-beam interrogates the defect site, localized heating from the e-beam changes the resistance of the defect, thereby changing the current sensed by the nanoprobe. The EBIRCH map displays the change in current as a function of the e-beam position—typically showing a bright spot at the site of the resistance change. The simultaneously acquired SEM image, together with knowledge of the circuit layout, allows the engineer to determine the exact defect location. The depth at which the defect lies can be explored by optimizing the landing energy as a function of the EBIRCH signal.

Available exclusively on the flexProber™, nProber™ and nProber II™ nanoprobers from DCG Systems, EBIRCH is part of an integrated electron beam current (EBC) module that offers seamless switching from EBAC to EBIRCH, with no re-cabling needed.

SAN JOSE, Calif. — mCube, provider of MEMS motion sensors, today announced the industry’s first 3-axis accelerometer which is less than a cubic millimeter in total size (0.9mm3). The MC3571 is only 1.1×1.1×0.74mm in size making it 75% smaller than current 2x2mm accelerometers on the market today, enabling developers to design high-resolution 3-axis inertial solutions for products that require ultra-small sensor form factors.

mCube_MC3571_AccelerometerThe MC3571 features a Wafer Level Chip Scale Package (WLCSP), making it smaller than a grain of sand. This achievement marks a major innovation milestone in the MEMS sensor industry and opens up new design possibilities for the next generation of sleek new mobile phones, surgical devices, and consumer products.

“The new MC3571 truly represents mCube’s vision of delivering a high-performance motion sensor in less than a cubic millimeter size,” said Ben Lee, president and CEO, mCube. “This advancement demonstrates how our monolithic technology can unleash amazing possibilities for designers to create exciting new products that could never be possible with today’s standard 2x2mm sensors.”

“mCube is the first company we’ve seen with a 1.1×1.1mm integrated MEMS+CMOS accelerometer and stretches once again the limits of miniaturization establishing new standards for the industry,” said Guillaume Girardin, Technology & Market Analyst MEMS & Sensors at Yole Développement (Yole). And his colleague, Thibault Buisson, Technology & Market Analyst, Advanced Packaging added: “Clearly, there is a growing trend among consumer companies to transition to wafer-level CSP packaging designs and with the MC3571 inertial motion sensor, mCube is at the forefront of this market evolution and at Yole, we are curious to see how competition will react.”

The high-resolution 14-bit, 3-axis MC3571 accelerometer is built upon the company’s award-winning 3D monolithic single-chip MEMS technology platform, which is widely adopted in mobile handsets with over 100 million units shipped. With the mCube approach, the MEMS sensors are fabricated directly on top of IC electronics in a standard CMOS fabrication facility. Advantages of this monolithic approach include smaller size, higher performance, lower cost, and the ability to integrate multiple sensors onto a single chip.

About the MC3571 Accelerometer

MC3571 is a low-noise, integrated digital output 3-axis accelerometer, which features the following:

  • 8, 10, or 14-bit resolution;
  • Output Data Rates (ODR) up to 1024Hz;
  • Selectable interrupt modes via an I2C bus;
  • Requires only a single external passive component, compared to competitive offerings requiring 2 or more.

Samples of the world’s smallest 1.1×1.1mm WLCSP accelerometer are available to select lead customers now with volume production scheduled for the second quarter of 2016.

 

Caen, Oct. 22, 2015 – Two years after the launch of the PICS project (funded by the FP7 funding instrument dedicated to research for the benefit of SMEs), three European SMEs, IPDiA, Picosun, and SENTECH Instruments along with CEA-Leti and Fraunhofer IPMS-CNT announce the major technological results achieved during this program.

Started in September 2013, the PICS project was focused on developing innovative dielectric materials deposited by atomic layer deposition (ALD) and related tools (ALD batch tool and etching tool) to bring to mass production a new technology of high- density and high-voltage 3D trench capacitors targeting high-end markets like medical or aeronautics. Capacitors are key components presented in every electronic module. The integrated silicon capacitors technology offered by the SME IPDiA outperforms current technologies (using ceramic or tantalum substrates) in stability in temperature, voltage, aging and reliability and enables to build highly integrated and high-performance electronic modules.

The consortium’s three major technological results are:

  • A novel ALD batch tool was developed by Picosun and Fraunhofer IPMS-CNT. It enables to reduce cost-of-ownership and deliver better uniformity and step coverage for high-K dielectrics into 3D structures. With its demonstrated, optimized, and production-proven ALD processes, Picosun is solidifying its position as a technological leader in the IC, Semiconductor, MEMS markets, from R&D to production systems.
  • A new process for accurately etching high-K dielectrics, which are very specific materials, was demonstrated by SENTECH with the help of Fraunhofer IPMS-CNT. As a result, SENTECH has the potential to gain market share in the field of high-k materials, which have high interest for different applications, e.g. LED, MEMS, magnetic data storage.
  • Two new dielectric stacks were developed and integrated into the IPDiA 3D trench capacitors by IPDiA, CEA-Leti and Fraunhofer IPMS-CNT. The initial specifications were fulfilled and proven by electrical measurements. A new record on capacitance density (>500nF/mm² at 3.3V) and an extended operation voltage (10V with 150nF/mm²) were obtained, which expands IPDiA’s ability to meet current market requirements particularly in the field of medical or aeronautics. Qualification procedure was initiated during the project by launching preliminary reliability studies and it will continue in the coming months.

On top of these R&D results, the other main objective of PICS was the industrialization of this new integrated capacitors technology. Thanks to the partnerships set up, the manufacturability and financial viabilities were ensured by developing adequate industrial tools targeting mass production.

The PICS project is a success for all three SMEs and a good example of the benefits brought by the EU funding instrument “Research for the benefit of SMEs”. The SMEs were able to outsource a part of their research to get from RTD performers innovative know-how and cutting-edge technological processes. The project was built to answer the SMEs’ specific needs and a common goal was set up around the new IPDiA capacitors technology and the specific tools (ALD batch tool and etching) required for its commercial exploitation.

 

SUNNYVALE, Calif. – OCT 21, 2015 – Advanced Linear Devices, Inc. (ALD), a design innovation leader in analog semiconductors, today announced a family of Supercapacitor Auto Balancing (SAB™) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) designed for industrial applications to regulate and balance leakage currents while minimizing energy used for balancing supercapacitor cells stacked in series stack of two or more.

The devices are ideal for a number of industrial-grade energy storage applications that require an operating temperature range between -40 to 85 degrees Celsius. The devices are ideally suited for a range of applications such as remote monitoring applications, automotive systems, backup power, transportation, automation, or any application that operates in exposure to the elements and needs to endure extreme climate conditions.

In outdoor industrial energy storage, leakage current of supercapacitors used in a stack is balanced by connecting one or more SAB MOSFETs across each cell. Leakage current balancing is critical to prevent damage to cells from over voltage that can dramatically shorten supercapacitor operating life.

“ALD’s industrial-grade SAB MOSFETS are designed to withstand a greater range of ambient temperature differential, and are therefore more reliable under greater stresses,” said Robert Chao, President and CEO of Advanced Linear Devices, Inc.

“Operators of industrial grade systems demand the utmost in reliability so all of the components used must be able to withstand harsh environmental elements and climates,” Mr. Chao added.

MOSFETs_thumbEach device in the industrial SAB MOSFET ALD8100xxx/ALD9100xxx family contains 26 different products and each product can balance supercapacitor up to 4 cells in a single IC package. Starting with two cells, the devices can balance an unlimited number of supercapacitor cells stacked in a series.

Each device in the SAB MOSFET family dissipates near zero leakage current to eliminate extra power dissipation. They provide a superior circuit design alternative to passive or active balancing methods by offering automatic active leakage current regulation. As an alternative to op-amp based schemes, the high voltage SAB MOSFET arrays can reduce board space, and lower cost while enhancing system and component lifespan.

SAB MOSFETs connected across these supercapacitors exhibit complementary opposing current levels, resulting in little or no additional leakage currents other than those caused by the supercapacitors themselves.

Leakage current differences in series stacked supercapacitor make it difficult to control respective cell voltages. This causes one or more supercapacitor to exceed its rated voltage over time, which reduces lifespan by rupturing materials inside each cell. Eventually this leads to catastrophic failure, which can begin over days, weeks, or months.

The voltage dependent characteristic of the ALD810019xxx/ALD91001xxx on-resistance controls excessive voltage rise of each individual supercapacitor cell. In series-connected stacks, when one supercapacitor voltage rises, the voltage of the other supercapacitors drops. The supercapacitors that have the highest leakage currents also have the lowest voltages. By increasing drain current exponentially when voltages increase, and by decreasing drain current exponentially when voltages decrease, the MOSFET arrays automatically regulate the voltage across each supercapacitor cell.

The products offer different threshold voltages for various supercapacitor operating voltages and leakage current characteristics which diminishes energy spent in balancing the circuits. The new device family covers a wide range of operating voltages from 1.6V to 2.7V and leakage current ranges from <0.3nA to >3000μA.

Available in both quad and dual packages, the industrial SAB MOSFETs are made with ALD’s precision EPAD® technology.

Perovskite solar cells are the rising star in photovoltaics. They absorb light across almost all visible wavelengths, they have exceptional power conversion efficiencies exceeding 20% in the lab, and they are relatively easy to fabricate. So, why are perovskite solar cells yet to be found on the top of our roofs? One problem is their overall cost, and another is that cheaper perovskite solar cells have a short lifespan. A study published in Advanced Materials Interfaces  by the Energy Materials and Surface Sciences Unit at the Okinawa Institute of Science and Technology Graduate University (OIST), reveals a cause for the short lifetime of perovskite solar cells with silver electrodes.

Currently, the most common electrode material in perovskite solar cells is gold, which is extremely expensive. A low-cost alternative to gold is silver, around 65 times cheaper. To keep the cost even lower, the team wants to use solution-processed method to fabricate the layers of the solar cell, instead of expensive vacuum-based techniques. The problem of using silver electrodes and the solution-based method is that silver gets corroded within days of the solar cell fabrication. The corrosion makes the electrode turn yellow, and reduces the efficiency of the cell. The OIST team, headed by Prof. Yabing Qi, has demonstrated the cause of this degradation and proposed an explanation.

Flexible perovskite solar cell device before (top) and after (bottom) corrosion of the silver electrode (Energy Materials and Surface Sciences Unit, OIST). The device was prepared by Dr. Mikas Remeika.

Flexible perovskite solar cell device before (top) and after (bottom) corrosion of the silver electrode (Energy Materials and Surface Sciences Unit, OIST). The device was prepared by Dr. Mikas Remeika.

Perovskite solar cells are composed of a sandwich of layers that work together to transform light into electricity. Light is absorbed by the perovskite material and stimulates electron excitations, generating the so-called electron-hole pairs. In simple terms: when electrons are excited, they “jump and leave holes behind.” Excited electrons and holes are transported in opposite directions by the adjacent layers of the solar cells, comprising of an electron-transport titanium dioxide layer, a spiro-MeOTAD hole-transport layer (HTL), a glass layer coated with a transparent conductive material, and a silver top electrode. The whole mechanism generates current, but it needs the correct functioning of each layer of the solar cell in order to work efficiently. “If one layer fails, the whole solar cell will suffer,” explains Luis Ono, a staff scientist and group leader in Prof. Qi’s unit.

In this study, the team analyzed the composition of the corroded silver electrode and identified the formation of silver iodide as the reason for the electrode corrosion. The color change was due to the oxidation from silver to silver iodide. They also found that exposure to air accelerates the corrosion, when compared to dry nitrogen gas exposure.

The team proposed a mechanism for this damage: silver iodide forms because gas molecules from ambient air reach the perovskite material and degrade it forming iodine containing compounds. These iodine-containing compounds diffuse to the silver electrode and corrode it. The migration of both air molecules and iodine-containing compounds could happen through small pinholes present in the spiro-MeOTAD HTL layer (see animation). The pinholes present in the spiro-MeOTAD HTL layer produced with the solution-processed method were identified some months ago by Zafer Hawash, a PhD student in the same laboratory.

Replacing gold with silver and using the solution-processed method are key to bringing down the cost of the solar cells. The OIST team believes that understanding the corrosion mechanism is the first step in increasing the electrode lifetime. Since preventing the formation of pinholes in the spiro-MeOTAD HTL layer is essential for a longer cell lifetime, the team is also working on producing pinhole-free solar cells with the solution-process method, while the production of pinhole-free HTL with the vacuum-based method has already been published by the same group. “Perovskite-based solar cells show potential for commercial use as the next generation photovoltaic technology. Our goal is to design and fabricate large-area and low-cost photovoltaic modules with extended lifetime by employing appropriate HTLs and encapsulation materials,” explains Qi.