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Peregrine Semiconductor Corp., founder of RF SOI (silicon on insulator) and pioneer of advanced RF solutions, announces the UltraCMOS 11 platform, the industry’s first RF SOI technology built on GLOBALFOUNDRIES’ 130nm 300mm RF technology platform. By moving to a 300mm wafer, Peregrine opens the door to new enhancements and advanced features in future generations of the UltraCMOS technology platform, which can leverage GLOBALFOUNDRIES’ 300mm production-proven design enablement and manufacturing expertise and scale.

Peregrine Semiconductor's UltraCMOS(R) technology platform now includes 300 mm wafers. Pictured are wafers from the UltraCMOS 11 technology platform (left), UltraCMOS 10 platform and UltraCMOS silicon on sapphire (right).

Peregrine Semiconductor’s UltraCMOS(R) technology platform now includes 300 mm wafers. Pictured are wafers from the UltraCMOS 11 technology platform (left), UltraCMOS 10 platform and UltraCMOS silicon on sapphire (right).

To develop the next-generation UltraCMOS 11 platform, Peregrine collaborated with tier-one fab GLOBALFOUNDRIES. UltraCMOS 11 technology uses a custom fabrication flow from GLOBALFOUNDRIES’ Fab 7 facility in Singapore.

“As an industry first, the new RF SOI technology reaffirms our commitment to the RF market, and is another example how GLOBALFOUNDRIES’ 300mm fab in Singapore can provide new levels of performance, reliability and scalability for integrated RF front-end solutions,” said Brian Harrison, senior vice president of Integration and Factory Management at GLOBALFOUNDRIES. “We are pleased to see the tremendous efforts resulted in this achievement, and we will continue to leverage our RF process development expertise and manufacturing scale to maximize the technology’s capabilities and drive differentiation with our customers.”

The UltraCMOS 11 platform will be the foundation for Peregrine’s high volume mobile products and SOI products for other applications. It builds on the success of the award-wining UltraCMOS 10 technology platform, also developed and manufactured by GLOBALFOUNDRIES, and offers unparalleled performance and cost-competitive advantages.

Portable electronics users tend to upgrade their devices frequently as new technologies offering more functionality and more convenience become available. A report published by the U.S. Environmental Protection Agency in 2012 showed that about 152 million mobile devices are discarded every year, of which only 10 percent is recycled — a legacy of waste that consumes a tremendous amount of natural resources and produces a lot of trash made from expensive and non-biodegradable materials like highly purified silicon.

Now researchers from the University of Wisconsin-Madison have come up with a new solution to alleviate the environmental burden of discarded electronics. They have demonstrated the feasibility of making microwave biodegradable thin-film transistors from a transparent, flexible biodegradable substrate made from inexpensive wood, called cellulose nanofibrillated fiber (CNF). This work opens the door for green, low-cost, portable electronic devices in future.

In a paper published this week in the Applied Physics Letters from AIP Publishing, the researchers describe the biodegradable device.

“We found that cellulose nanofibrillated fiber based transistors exhibit superior performance as that of conventional silicon-based transistors,” said Zhenqiang Ma, the team leader and a professor of electrical and computer engineering at the UW-Madison. “And the bio-based transistors are so safe that you can put them in the forest, and fungus will quickly degrade them. They become as safe as fertilizer.”

Nowadays, the majority of portable electronics are built on non-renewable, non-biodegradable materials such as silicon wafers, which are highly purified, expensive and rigid substrates, but cellulose nanofibrillated fiber films have the potential to replace silicon wafers as electronic substrates in environmental friendly, low-cost, portable gadgets or devices of the future.

Cellulose nanofibrillated fiber is a sustainable, strong, transparent nanomaterial made from wood. Compared to other polymers like plastics, the wood nanomaterial is biocompatible and has relatively low thermal expansion coefficient, which means the material won’t change shape as the temperature changes. All these superior properties make cellulose nanofibril an outstanding candidate for making portable green electronics.

To create high-performance devices, Ma’s team employed silicon nanomembranes as the active material in the transistor — pieces of ultra-thin films (thinner than a human hair) peeled from the bulk crystal and then transferred and glued onto the cellulose nanofibrill substrate to create a flexible, biodegradable and transparent silicon transistor.

But to make portable electronics, the biodegradable transistor needed to be able to operate at microwave frequencies, which is the working range of most wireless devices. The researchers thus conducted a series of experiments such as measuring the current-voltage characteristics to study the device’s functional performance, which finally showed the biodegradable transistor has superior microwave-frequency operation capabilities comparable to existing semiconductor transistors.

“Biodegradable electronics provide a new solution for environmental problems brought by consumers’ pursuit of quickly upgraded portable devices,” said Ma. “It can be anticipated that future electronic chips and portable devices will be much greener and cheaper than that of today.”

Next, Ma and colleagues plan to develop more complicated circuit system based on the biodegradable transistors.

When the new iPhone came out, customers complained that it could be bent — but what if you could roll up your too big 6 Plus to actually fit in your pocket? That technology might be available sooner than you think, based on the work of USC Viterbi engineers.

For many decades, silicon has been the heart of modern electronics — but as a material, it has its limits. As our devices get smaller and smaller, the basic unit of these devices, a transistor, must also get tinier and tinier. Bottom line: the size of the silicon transistor is reaching its physical limit. As silicon devices are based on what is called a top-down cutting method, it is increasingly difficult for silicon to be made even smaller. Consumers also demand phones to be lighter, faster, smaller, more flexible, wearable, bendable, etc. Yet silicon is also rigid — one can’t bend your smart phone or computer. These physical limitations have driven the race for new materials that can be used as semiconductors in lieu of silicon.

The demand for a silicon material aided the discovery of graphene, a single layer of graphite — which won the Nobel Prize in Physics in 2010. Since this time, scientists and engineers have developed many two-dimensional (2D) material innovations — layered materials with the thickness of only one atom or a few atoms. One such layered 2D material is black arsenic phosphorous. Now, a team of scientists at USC Viterbi, in collaboration with Technische Universität München, Germany, Universität Regensburg, Germany, and Yale University, have developed a new method to synthesize black arsenic-phosphorous without high pressure. This method demands less energy and is cheaper, and the synthesized materials have some incredible new properties.

The innovation, developed by USC Viterbi researchers, including Bilu Liu, the paper’s lead author and postdoctoral researcher; Ahamad Abbas, graduate student; Han Wang, assistant professor; Rohan Dhall, graduate student; Stephen B. Cronin, associate professor; Mingyuan Ge, research assistant; Xin Fang, graduate student; and Professor Chongwu Zhou of the Ming Hsieh Department of Electrical Engineering, in concert with their collaborators, is documented in a paper titled “Black Arsenic-Phosphorus: Layered Anisotropic Infrared Semiconductors with Highly Tunable Compositions and Properties.” The paper appeared in Advanced Materialson June 25, 2015.

What the researchers are most excited about is the ability to adjust the electronic and optical properties of these materials to a range that cannot be achieved by any other 2D materials thus far. This includes manipulating the materials’ chemical compositions during materials synthesis and the materials’ ability to sense long wavelength infrared (LWIR) waves due to their small energy gaps. This particular electromagnetic spectral range of LWIR is important for a range of applications such as LIDAR (light radar) systems, basically because LWIR waves are highly transparent in earth atmosphere. This wave range also has great application for the soldiers in the military who rely on infrared thermal imaging technology and for flexible night vision glasses. Another intriguing aspect of these new layered semiconductors is their anisotropic electronic and optical properties, which means the materials have different properties along x and y direction in the same plane. The researchers believe these are marked improvement from existing materials and devices and would lead to unique applications.

In addition, the researchers anticipate that it could also lead to important improvement for devices that monitor the environment. “We believe these materials are important members in a large family of 2D materials, because they fit into the long-wavelength-infrared light range and deliver properties that any other currently existing 2D materials cannot,” said Zhou, the research team leader.

According to Liu, the paper’s lead author: “As these are rather new materials, we anticipate there is lots of exciting fundamental physics research as well as engineering work to be done. For example, what’s the electronic and optical properties of a truly single layer black arsenic phosphorus?”

The latest manufacturing, materials and production developments in semiconductor and related technologies will be featured at SEMICON West 2015 on July 14-16 at Moscone Center in San Francisco, Calif.  Semiconductor processing is at a crossroads and is changing how companies operate to be competitive. Learning about breakthrough technology and networking is essential to remain ahead of the curve.  

More than 25,000 professionals are expected, and over 600 companies will exhibit the latest in semiconductor manufacturing.  Major semiconductor manufacturers, foundry, fabless companies, equipment and materials suppliers — plus leading companies in MEMS, displays, printed/flexible electronics, PV, and other emerging technologies — attend SEMICON West.

SEMICON West will feature valuable on-exhibition floor technical sessions and programs that are included in the  $100 registration “expo pass” (registration fee increases on July 11).  Keynote events include: 

·         “Scaling the Walls of Sub-14nm Manufacturing” with panelists from Qualcomm, Stanford University, ASE and IBM, moderated by imec’s Jo de Boeck, senior VP of Corporate Technology (July 14, 9:00-10:00am)

·         “The Internet of Things and the Next Fifty Years of Moore’s Law“ by Intel’s Doug Davis, senior VP and GM of loT (July 15, 9:00am-9:45am)

TechXPOTs will provide updates in areas including test, advanced materials and processes, advanced packaging, productivity and emerging markets and technologies. TechXPOTs include:

·      What’s Next for MEMS? With speakers from ASE, CEA-Leti, EV Group, MEMS Industry Group, Silicon Valley Band of Angels, Teledyne DALSA, and Yole Developpement (July 14, 10:30am-12:30pm)

·      Automating Semiconductor Test Productivity with speakers from ASE, Optimal+, Texas Instruments, and Xcerra (July 14, 10:30am-12:30pm)

·      Materials Session: Contamination Control in the Sub-20nm Era with speakers from Entegris, Intel, JSR Micro, Matheson, and Nanometrics; moderated by Mike Corbett, Linx (July 14, 1:30pm-3:30pm)

·      Emerging Generation Memory Technology: Update on 3DNAND, MRAM, and RRAM (July 14, 1:30pm-3:40pm).

·      The Evolution of the New 200mm Fab for the Internet of Everything with speakers from Entrepix, Genmark Automation, Lam Research, Qorvo, and Surplus Global (July 15, 2:00pm-4:00pm)

·      Monetizing the IoT: Opportunities and Challenges for the Semiconductor Sector with Amkor, Cadence Design Systems, Ernst & Young, Freescale Semiconductor, and Gartner; moderated by Edward Sperling, Semiconductor Engineering (July 16, 10:30am-12:30pm)

·      The Factory of the (Near) Future: Using Industrial IoT and 3D Printing  with speakers from AirLiquide, Applied Materials, Lawrence Livermore National Laboratory, Oak Ridge National Laboratory, and Proto Cafe (July 16, 1:00pm-3:00pm) 

The Silicon Innovation Forum will be held on July 14-15.  A special exposition segment, this area will include exhibits and two days of presentations.  The first day will be a forum where start-up companies seeking investment capital will present to a panel of investors.  Open to all attendees, this session will feature exciting new technologies.  The second day will be a forum on new research. Attendees can hear presentations on advanced research from SLAC National Accelerator Laboratory, International Consortium for Advanced Manufacturing Research, SUNY Network of Excellence – Materials & Advanced Manufacturing, Novati Technologies, MIST Center, Micro/Nano Electronics Metrology at NIST, Texas State University and Georgia Tech Heat Lab. 

On July 16, University Day welcomes students and faculty to learn about the microelectronics industry, connect with industry representatives, and explore career opportunities. University Day is on the Keynote Stage (North Hall E). The agenda includes career networking, exploration forum, expo and SEMICON West tours.

For the eighth year, SEMICON West will be co-located with Intersolar North America, the leading solar technology conference and exhibition in the U.S.  Premier sponsors of SEMICON West 2015 include Applied Materials, KLA-Tencor, and Lam Research.  Register now at www.semiconwest.org.

Freescale Semiconductor has disclosed initial details regarding the next generation of its successful QorIQ multicore processor portfolio, today announcing it will drive innovation for the secure Internet of Tomorrow (IoT) on highly advanced 16nm FinFET process technology.

The move to 16nm FinFET is expected to enable next-generation QorIQ processors to deliver 2x performance gains within the same power envelope relative to 28nm products. Freescale has already performed extensive evaluation and testing on 16nm FinFET, and is now applying its findings to next-node implementations of cores, hardware accelerators, interconnect fabrics and other IP.

At this node, Freescale will maintain its focus on extending its leadership in standard product communications processor families, while also unleashing the breadth of its extensive IP portfolio with complementary new go-to-market engagement models, including the development of innovative semi-custom designs in tight alignment with select strategic customers.

“The world’s networks are moving and changing faster than ever before, driven by the convergence of extreme virtualization, software-centric network topologies, continued expansion of the IoT, and growing demand for increased, flexible intelligence at the network’s edge,” said Tom Deitrich, SVP and GM of Freescale’s Digital Networking group. “This new paradigm favors silicon providers like Freescale with advanced process technology, deep bonds with the world’s leading equipment OEMs, and the breadth of critical IP like software, advanced acceleration engines and optimized compute densities ideally suited to drive the Internet of Tomorrow.”

To help its deep roster of top networking OEM customers differentiate and thrive in this new environment, Freescale plans to exploit the full value of its 16nm FinFET IP to create innovative, semi-custom designs engineered to meet the dynamic requirements of highly virtualized networks. Customers can mix and match Freescale IP alongside their own proprietary IP to offer the most differentiated solution in their market space. Aligning in this manner with strategic customers is expected to optimize efficiencies, speed time-to-market and foster closer customer cooperation in the development of next-generation solutions. For Freescale, these kinds of new engagement models can enable optimized R&D investment and synergistic roadmap alignment.

Providing the building blocks for innovation at 16nm

To meet the demands of tomorrow’s networks, Freescale will provide lead customers and partners access to a broad spectrum of 16nm building blocks. Freescale maintains one of the broadest and most diverse portfolios of networking IP in the world, including high performance 64-bit cores based on ARM and Power Architecture technology, StarCore DSP cores, highly advanced I/O and acceleration technologies, world-class network security blocks and extensive software solutions – all backed by Freescale’s proven networking systems knowledge and decades of SoC design experience.

Rich ecosystem and complete enablement

The Freescale 16nm platform will be supported by a comprehensive ecosystem providing ease-of-use support for its QorIQ processors, supplemented with operating systems and BSPs from its partner network. The CodeWarrior Integrated Development Environment (IDE), and an optimized and compliance tested Layer-1 software components library for FDD & TDD LTE/LTE-A processing chains will enable rapid customer LTE L1 software development. Communications targeted Linux SDKs including low latency Layer 2 support will also be offered. Freescale supports Linaro and OpenDataPath (ODP) APIs and management software for easy setup, initialization and teardown of interfaces, accelerators and networking functions. For fast time to market, performance-optimized functional datapath libraries, Freescale VortiQa software solutions and a selection of development tools and open-source software are planned. Software services are offered enabling customers to leverage Freescale’s systems expertise for specifically targeted deliverables.

Initial 16nm FinFET SoC product sampling is expected in mid-2016.

CEA-Leti will host a workshop on major trends in Fully Depleted Silicon-on-Insulator process and design technologies in connection with the 17th annual LetiDays Grenoble, June 24-25.

The June 22-23 FDSOICE workshop, which will be on the MINATEC campus, brings together experts from academia, semiconductor companies, system-design houses and the EDA industry to present a vision of the strategic directions and state-of-the-art in FD-SOI IC design. Specific topics cover the FD-SOI food chain: applications, process roadmaps and manufacturing technologies, energy-efficient architectures and power management, circuit-design techniques, body-bias techniques, modeling, characterization and design enablement.

In addition to keynotes by Thomas Skotniki from STMicroelectronics and Prof. Boris Murmann from Stanford University, the workshop’s 30 presentations will cover the whole knowledge chain and the market value chain from academia and industry. Highlights of the presentations include:

  • ST, GLOBALFOUNDRIES and Samsung will cover FD-SOI manufacturing offers
  • Ciena, ST and NXP will discuss products based on FD-SOI chips
  • Cadence, Synopsys, Mentor Graphics, sureCore, eSilicon and Tiempo will explain their offers for FD-SOI in terms of IP and EDA tools
  • Prominent professors from world-class universities (ETH Zurich, University of Bologna, University of Kyoto, University of California, Berkeley) will present their innovations to design with FD-SOI
  • Leti will present state-of-the-art research in FD-SOI and facilities available to partners willing to start design with FD-SOI

Visit LetiDays Grenoble registration details and other information about the conference on June 24-25, and associated workshops and seminars on June 22, 23 and 26.

Europe’s leading nanoelectronics institutes, Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, have entered a €4.7 million collaborative open-access project called ASCENT (Access to European Nanoelectronics Network). The project will mobilize European research capabilities at an unprecedented level and create a unique research infrastructure that will elevate Europe’s nanoelectronics R&D and manufacturing community.

ASCENT opens the doors to the world’s most advanced nanoelectronics infrastructures in Europe. Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, leading European nanoelectronics institutes, have entered into a collaborative open-access project called ASCENT (Access to European Nanoelectronics Network), to mobilise European research capabilities like never before.

The €4.7 million project will make the unique research infrastructure of three of Europe’s premier research centres available to the nanoelectronics modelling-and-characterisation research community.

ASCENT will share best scientific and technological practices, form a knowledge-innovation hub, train new researchers in advanced methodologies and establish a first-class research network of advanced technology designers, modellers and manufacturers in Europe. All this will strengthen Europe’s knowledge in the integral area of nanoelectronics research.

The three partners will provide researchers access to advanced device data, test chips and characterisation equipment.  This access programme will enable the research community to explore exciting new developments in industry and meet the challenges created in an ever-evolving and demanding digital world.

The partners’ respective facilities are truly world-class, representing over €2 billion of combined research infrastructure with unique credentials in advanced semiconductor processing, nanofabrication, heterogeneous and 3D integration, electrical characterisation and atomistic and TCAD modelling. This is the first time that access to these devices and test structures will become available anywhere in the world.

The project will engage industry directly through an ‘Industry Innovation Committee’ and will feed back the results of the open research to device manufacturers, giving them crucial information to improve the next generation of electronic devices.

Speaking on behalf of project coordinator, Tyndall National Institute, CEO Dr. Kieran Drain said: “We are delighted to coordinate the ASCENT programme and to be partners with world-leading institutes CEA-Leti and imec. Tyndall has a great track record in running successful collaborative open-access programmes, delivering real economic and societal impact. ASCENT has the capacity to change the paradigm of European research through unprecedented access to cutting-edge technologies. We are confident that ASCENT will ensure that Europe remains at the forefront of global nanoelectronics development.”

“The ASCENT project is an efficient, strategic way to open the complementary infrastructure and expertise of Tyndall, Leti and imec to a broad range of researchers from Europe’s nanoelectronics modelling-and-characterisation sectors,” said Leti CEO MarieNoëlle Semeria. “Collaborative projects like this, that bring together diverse, dedicated and talented people, have synergistic affects that benefit everyone involved, while addressing pressing technological challenges.”

“In the frame of the ASCENT project, three of Europe’s leading research institutes – Tyndall, imec and Leti – join forces in supporting the EU research and academic community, SMEs and industry by providing access to test structures and electrical data of state-of-the-art semiconductor technologies,” stated Luc Van den hove, CEO of imec. “This will enable them to explore exciting new opportunities in the ‘More Moore’ as well as the ‘More than Moore’ domains, and will allow them to participate and compete effectively on the global stage for the development of advanced nano-electronics.”

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 65384.

BY PHIL GARROU, Contributing Editor

At the recent IMAPS conference, Yole’s Jerome Alzemer updated the audience on the Fan Out and Embedded die marketplace, based on his new report “Fan out and Embedded Die: Technology and Market Trends.”

Embedded packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infra- structure such as FOWLP and (2) those based on a PWB/ PCB laminate panel infrastructure.

Fan-out WLP are “re-configured” by placing known good ICs active face down on a foil and by over-molding them. These wafers are then flipped and processed in the wafer fab with RDL/ball placing and diced.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.

Fan Out WLP (FOWLP)

Unlike Fan In WLP, which has been commercialized since the late 1990’s, FOWLP is not constrained by die size, and thus can offer an unlimited number of interconnects for maximum connection density. One can also achieve finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and perfor- mance demands of the mobile market.

Commercialization of the Infineon e-WLB (embedded wafer level BGA) technology started in 2009 with single die packages for cell phone baseband chips. The Infineon technology was later licensed to OSATS Nanium, STATSChipPAC and ASE, thus creating a multi-sourced infrastructure.

A similar process called Redistributed Chip Packaging (RCP) was developed by Freescale during the same time period. It was subsequently licensed to NEPES but has not yet reached HVM. Other developing FOWLP technologies — including those of TSMC (called InFO), SPIL and J- Devices — are approaching commercialization but will initially lack the multi- sourcing available with eWLB.

The second generation of FOWLP are multichip packages including PoP and SiP configurations. These are generating increased interest in this packaging approach.

As of 2014 Yole estimates that the market is ~ $174MM. With the expected entry of several major players like TSMC, Yole envisions the market growing at a 30% CAGR to > $600MM by 2020.

Technical challenges such as warpage, die shift, chip- to-mold non planarity and topography remain significant limitations.

Imec researchers have developed a novel technique – termed conductive atomic force microscopy tomography (or scalpel C-AFM) – that enables a three-dimensional characterization of emerging logic and memory devices.

BY UMBERTO CELANO, imec, Leuven, Belgium

Umberto Celano, using the novel scalpel C-AFM tool.

Umberto Celano, using the novel scalpel C-AFM tool.

With the introduction of three-dimensional devices (such as FinFETs) and stackable architectures (such as vertical NAND Flash memories), there is a growing need for 3D characterization techniques. These techniques should not only be capable of probing in three dimensions and examining the topological properties. They should also enable an analysis of the electrical properties of the 3D nano-sized volumes.

A shining example illustrating the need for this technique are conductive bridging random access memory (or CBRAM) devices. These devices belong to the emerging class of resistive RAM (or RRAM) memories which exhibit a fast operation, low power consumption, high endurance and high scalability. They are currently seen as a candidate memory technology for application in storage class memories and embedded non-volatile memories. Their operation basically relies on the formation of a highly conductive path, the conductive filament, in a poorly conductive medium. But the formation of this filament in an integrated device has so far never been observed with the techniques available today. A full 3D characterization of the conductive filament would considerably enhance our understanding of the filament growth dynamics and the underlying physical mechanisms. And it would enable a further optimization of the memory device.

Scalpel C-AFM, extending the 2D capabilities of C-AFM

A well-known characterization technique for advanced logic and memory devices is scanning probe microscopy (or SPM), where a sharp tip slides on a flat surface.

The 2D-maps of electrical properties provided by this technique have for many years enabled the understanding and development of advanced planar technologies at the nanoscale. SPM comes in several flavors, such as scanning tunnel microscopy (STM), atomic force microscopy (AFM), and a whole range of secondary analysis modes such as conductive AFM (or C-AFM). C-AFM is based on contact-mode AFM using a (biased) conductive tip. The topography is measured in contact-mode, while the current flowing between the biased sample and the tip is recorded simultaneously.

Researchers at imec have now evolved the C-AFM technique into a 3D characterization tool, suited to probe very confined volumes at the nanoscale. The new method consists in collecting the C-AFM images of the sample at different depths. The sectioning is induced by a controlled material removal. This is done by applying a strong pressure (GPa) between the (biased) conductive-diamond tip and the sample during the C-AFM scan. This way, sub-nm vertical removal rates are obtained. Since the diamond tip acts as a scalpel, the new method is referred to as scalpel C-AFM. The technique can be used for a wide variety of materials, and can be extended to other contact-mode AFM methods such as scanning spreading resistance microscopy.

Case: CBRAM memory devices

The imec researchers have used the scalpel C-AFM technique for studying the conductive filament formation in CBRAM memory devices. In these devices, an abrupt change in electrical resistance occurs when the device is subjected to a voltage pulse. The different resistance states are induced by the formation or dissolution of a highly conductive filament into a poorly conductive medium.

The heart of the CBRAM memory cell is a thin dielectric (e.g., Al2O3) that is sandwiched between the active electrode (Cu or Ag) and an inert counter electrode (e.g., TiN). When a positive voltage is applied to the active electrode, a field-assisted injection and transport of cations begins. This leads to the creation of the conductive filament inside the Al2O3 oxide layer. The presence of this filament dramatically lowers the resistance of the device, leaving it in a low resistive state (LRS). The conductive filament can be dissolved by applying a negative voltage to the active electrode and thus restoring a high resistance state (HRS). The two different resistance states are used as the logic values 1 or 0 for data storage applications. The overall performance of the device is highly related to the properties of the conductive filament, which has so far not been observed in 3D on scaled devices.

Observation of the conductive filament

The memory device under investigation is a Cu/5nm Al2O3/TiN-based memory, integrated in a one-transistor-one-resistor configuration. The device is placed at the cross-point between the bottom and top electrode. The scalpel C-AFM technique was applied to memory devices programmed in both the low and high resistive state. An in-house fabricated conductive- diamond tip was used for probing and removing the material.

By using the scalpel C-AFM technique, the researchers were able to observe, for the first time ever, the conductive filament formation which is responsible for the resistive switching behavior in CBRAM devices (FIGURE 1). The observed conductive filament, embedded in the Al2O3 oxide, shows a conical shape: it shrinks moving from the active electrode (Cu) towards the inert electrode (TiN). The low resistive state is created when the conductive filament eventually shorts the two electrodes.

Filaments 1-1 Filaments 1-2

 

FIGURE 1. CBRAM device: Cross-section transmission electron microscopy (TEM) image of the CBRAM memory device (left) and the device stack (middle), and AFM image of the cross-point area (right).

The experiments suggest that the dynamics of the conduction filament growth are limited by the mobility of the Cu cations in the electrolyte (FIGURE 2). When the bias is reversed, a Joule-heating assisted electro-chemical reaction is responsible for the rupture of the conductive filament (the high resistive state).

The study also demonstrates the close correlation between the programming current, the physical volume of the conductive filament and the resistance. A larger programming current induces a larger physical volume and a lower resistance value of the conductive filament. Hence, by controlling the programming current, the resistance can be modulated. This opens the possibility of creating multiple resistance sates in one single memory cell, which can considerably enhance the memory density of non-volatile CBRAM devices.

Scalpel C-AFM will rapidly find applications in other emerging technologies as well. At imec, the technique is currently being used for investigating vertical NAND Flash memory devices and oxide-based RRAM memory devices.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

Suggested additional reading

‘Three-dimensional observation of the conductive filament in nanoscaled resistive memory devices’, U. Celano et al., Nano Letters, 2014. http://pubs.acs.org/ doi/abs/10.1021/nl500049g.

‘The memory roadmap, a paradigm shift from 2D to 3D’, interview with imec’s Jan Van Houdt in imec magazine, March issue. http://magazine.imec.be/ data/57/reader/reader.html#preferred/1/package/57/ pub/63/page/4.

UMBERTO CELANO is PhD student in the Material and Component Analysis (MCA) group at imec, Leuven, Belgium.

SEMI this week announced the SEMICON West 2015 test and packaging program agendas. In addition to over 650 exhibitors, SEMICON West will feature more than 180 total hours of programs — including free technical, applications and business events as well as exclusive programs. Discounted registration for SEMICON West 2015 ends June 5.

Exclusive programs include the three-day Semiconductor Technology Symposium (STS), a comprehensive technology and business conference, addressing the key issues driving the future of semiconductor manufacturing and markets. This year, STS programs on Packaging and Test include:

  • The Very Big Picture, the Future of Semiconductor Packaging Technology (July 14) — with speakers from 3MTS, AMD, Oracle, and more; plus a panel discussion on “Value vs. Cost”
  • Packaging: Digital Health and Semiconductor Technology (July 14) — with speakers from Cisco, Medicustek, GE Global Research Center, Medtronic, and more
  • Test Vision 2020The Road to the Future of Test  (July 15-16) — with keynote from Kaivan Karimi, VP at Atmel, Inc. plus speakers Brad Shaffer of IHS and Thomas Burger of AMS. Sessions include: Wireless Test in the IoT Era; Unique Test Flows for New Cost Challenges; and Advanced Packaging, Advanced Test Challenges. Panel sessions will discuss “How Secure is your Test Data, Really?” and “What Does RF Test Look like in Five Years? Future Solutions for Lowering the Cost of Transceiver Tests”

In addition, two packaging and test sessions will be offered as part of the TechXPOT program on the exhibition floor (free to exposition attendees):

  • Automating Semiconductor Test Productivity (July 14) — a panel of experts from the semiconductor test community, including representatives from TI, STMicro and ASE,  will discuss challenges and opportunities for automating test operations to maximize productivity
  • Auto Utopia: Gearing up Semiconductor to Turns Dreams to Reality (July 15) — with speakers from ASE, Gartner, PRIME Research, ASE Singapore, and more (session partner: MEPTEC)

Other key segments at SEMICON West 2015 include:

  • Global Business Outlook
  • Semiconductor Fabrication, Equipment and Materials
  • The Internet of Things
  • MEMS
  • Flexible Hybrid Electronics
  • Sustainable Manufacturing
  • Next-Generation Products

SEMICON West (www.semiconwest.org) continues to feature a full set of complimentary programs, including keynote addresses, executive panels, technical and business sessions.  The Tuesday Keynote Panel features imec, Qualcomm, and Stanford University tackling the issue of “Scaling the Walls of sub-14nm Manufacturing.” Doug Davis, senior VP and GM, IoT Group at Intel, will present the Wednesday Keynote.

To view a SEMICON West 2015 “schedule at-a-glance,” click here.  Discounted pricing is available through June 5.  Early-bird pricing for the Semiconductor Technology Symposium (STS), Test Vision 2020, and Sustainable Manufacturing Forum (SMF) also applies through June 5.  Register now to save: www.semiconwest.org/Participate/RegisterNow