Tag Archives: letter-ap-tech

Portable electronics – typically made of non-renewable, non-biodegradable and potentially toxic materials – are discarded at an alarming rate in consumers’ pursuit of the next best electronic gadget.

In an effort to alleviate the environmental burden of electronic devices, a team of University of Wisconsin-Madison researchers has collaborated with researchers in the Madison-based U.S. Department of Agriculture Forest Products Laboratory (FPL) to develop a surprising solution: a semiconductor chip made almost entirely of wood.

The research team, led by UW-Madison electrical and computer engineering professor Zhenqiang “Jack” Ma, described the new device in a paper published today (May 26, 2015) by the journal Nature Communications. The paper demonstrates the feasibility of replacing the substrate, or support layer, of a computer chip, with cellulose nanofibril (CNF), a flexible, biodegradable material made from wood.

“The majority of material in a chip is support. We only use less than a couple of micrometers for everything else,” Ma says. “Now the chips are so safe you can put them in the forest and fungus will degrade it. They become as safe as fertilizer.”

Zhiyong Cai, project leader for an engineering composite science research group at FPL, has been developing sustainable nanomaterials since 2009.

“If you take a big tree and cut it down to the individual fiber, the most common product is paper. The dimension of the fiber is in the micron stage,” Cai says. “But what if we could break it down further to the nano scale? At that scale you can make this material, very strong and transparent CNF paper.”

Working with Shaoqin “Sarah” Gong, a UW-Madison professor of biomedical engineering, Cai’s group addressed two key barriers to using wood-derived materials in an electronics setting: surface smoothness and thermal expansion.

“You don’t want it to expand or shrink too much. Wood is a natural hydroscopic material and could attract moisture from the air and expand,” Cai says. “With an epoxy coating on the surface of the CNF, we solved both the surface smoothness and the moisture barrier.”

Gong and her students also have been studying bio-based polymers for more than a decade. CNF offers many benefits over current chip substrates, she says.

“The advantage of CNF over other polymers is that it’s a bio-based material and most other polymers are petroleum-based polymers. Bio-based materials are sustainable, bio-compatible and biodegradable,” Gong says. “And, compared to other polymers, CNF actually has a relatively low thermal expansion coefficient.”

The group’s work also demonstrates a more environmentally friendly process that showed performance similar to existing chips. The majority of today’s wireless devices use gallium arsenide-based microwave chips due to their superior high-frequency operation and power handling capabilities. However, gallium arsenide can be environmentally toxic, particularly in the massive quantities of discarded wireless electronics.

Yei Hwan Jung, a graduate student in electrical and computer engineering and a co-author of the paper, says the new process greatly reduces the use of such expensive and potentially toxic material.

“I’ve made 1,500 gallium arsenide transistors in a 5-by-6 millimeter chip. Typically for a microwave chip that size, there are only eight to 40 transistors. The rest of the area is just wasted,” he says. “We take our design and put it on CNF using deterministic assembly technique, then we can put it wherever we want and make a completely functional circuit with performance comparable to existing chips.”

While the biodegradability of these materials will have a positive impact on the environment, Ma says the flexibility of the technology can lead to widespread adoption of these electronic chips.

“Mass-producing current semiconductor chips is so cheap, and it may take time for the industry to adapt to our design,” he says. “But flexible electronics are the future, and we think we’re going to be well ahead of the curve.”

United Microelectronics Corporation, a global semiconductor foundry, today unveiled its UMC Auto technology platform to target IC companies designing chips for automotive applications. UMC Auto is a comprehensive platform that consists of a broad portfolio of automotive AEC-Q100 qualified technology solutions ranging from 0.5um to 28nm nodes, backed by robust manufacturing processes that comply with rigorous ISO TS-16949 automotive quality standards for all UMC fabs. In addition, UMC is selectively developing certified design models, IP, and Foundry Design Kits specific to the UMC Auto platform in order to fulfill the increasing pace of evolvement of the auto industry supply chain, helping chip designers capture new market opportunities as Internet of Things (IoT) and increased use of sensors permeate into auto applications.

“With the rapid rise in silicon content within each new vehicle, many believe the automotive IC sector will experience the highest CAGR compared with other semiconductor segments,” said Po Wen Yen, CEO of UMC. “UMC has a successful history as an automotive IC supplier, being the first foundry to receive ISO 22301 certification for our business continuity management system and implementing a comprehensive “Automotive Service Package” that incorporates zero-defect practices within our manufacturing procedures. We look forward to enabling more customers to realize the opportunities within the automotive IC market through our innovative UMC Auto solutions platform.”

UMC is currently producing various key electronic components used in vehicles, including Advanced Driver Assistance Systems (ADAS), safety, body control, infotainment and under-hood applications. These ICs manufactured at UMC have been widely adopted by the world’s most well-known carmakers in Japan, Europe, Asia and the United States.

UMC’s auto IC manufacturing lines meet or exceed the automotive industry’s most stringent quality and reliability criteria, including the highest rated AEC-Q100 Grade-0 certification for its fab manufacturing. UMC was also the first foundry in Taiwan to provide IC manufacturing services that comply with ISO 15408 Common Criteria, joining the 1 percent of all companies and products worldwide to be certified ISO 15408 EAL6 or above. This security qualification signifies UMC’s ability to provide rigorous security protection during the manufacturing process, which is required by the majority of IC products deployed in sensitive applications that need to be highly secure such as automotive sensors for door locks, navigation, etc.

GaN Systems, a developer of gallium nitride power switching semiconductors, today confirmed the world’s smallest 650V, 15A gallium nitride transistor. With a footprint of just 5.0 x 6.5mm, the GS66504B – one of a family of 650V devices that spans 7A to 200A – is 50 percent smaller than competing devices.

Comments Jim Witham, CEO GaN Systems: “We were somewhat surprised to see announcements at last week’s PCIM power electronics exhibition and conference that trumpeted gallium nitride 600V, 15A devices in 8x8mm dual-flat no-lead (DFN) packaging as the ‘industry’s smallest’ enhancement mode devices – our part is clearly much smaller. But I suppose this is just an indication of how quickly the GaN market is moving, and a positive indication that silicon has reached its limits.”

He continued: “Our message to designers in applications as diverse as flat screen TVs, games consoles, washing machines, inverters, electric vehicles, motors and wider is the same: if you are not on-board with GaN, you will be left behind by your competitors.”

GaN Systems is the first company to have developed and brought a comprehensive product range of devices with current ratings from 7A to 250A to the global market – its Island Technology die design, combined with its extremely low inductance and thermally efficient GaNPX packaging and Drive Assist technology means the company’s GaN transistors offer a 40-fold improvement in switching and conduction performance over traditional silicon MOSFETs and IGBTs. Devices are available now through its worldwide distribution network.

Dow Corning, a developer of silicones, silicon-based technology and innovation, today unveiled new Dow Corning TC-3040 Thermally Conductive Gel, a next-generation thermal interface material (TIM 1). Developed through the help of IBM, this cutting-edge new material offers more effective and reliable thermal management, reduced stress and excellent under-die coverage for demanding flip chip applications. Dow Corning unveiled the new product technology here at the IEEE Electronic Components and Technology Conference (ECTC 2015). 

TIM-1 solutions are a class of high-purity, thermal interface materials that are applied between the chip surface and a heat spreader to help dissipate damaging heat to the exterior of a semiconductor package. However, as applications from data centers to consumer devices to automotive electronics all demand higher functioning integrated semiconductor devices with increasing processing power, the temperatures within chip packages are rapidly increasing and testing the limits of conventional TIM-1 solutions.

“A long-time member of IBM’s ecosystem, Dow Corning brought decades of expertise in advanced silicone technology to help formulate this break-through TIM-1 material for high-end chip packaging,” said Andrew Ho, global market segment leader, Semiconductor Packaging Materials at Dow Corning. “It is only the latest innovation on the ambitious roadmap of thermal management solutions that Dow Corning has planned for this rapidly evolving global market.”

The successful efforts of IBM and Dow Corning scientists have raised the bar for TIM-1 performance. Dow Corning TC-3040 Thermally Conductive Gel delivers nearly two times the thermal performance of other industry standard TIMs, as well as high thermal conductivity targeting 4W/mK with robust reliability. As a result, it offers chip-makers broader design options for high-performing yet more reliable ICs with improved thermal management.”

Semiconductor test equipment supplier Advantest Corporation announced today that it has developed a technology utilizing short-pulse terahertz waves for analysis of electrical circuits. The technology has 2 major applications – analysis of the transmission characteristics (S parameters) of devices using the sub-terahertz band (100GHz~1THz), and characterization and location of failures in chip circuits (TDT/TDR). The new technology overcomes the technical obstacles and prohibitive cost of existing technologies, and will contribute significantly to the development and wider adoption of these leading-edge devices.

Sub-terahertz transmission characteristics analysis technology

The popularity of smartphones and other mobile devices has driven enormous increases in wireless communications traffic, which now threatens to overwhelm the capacity of currently assigned frequencies. Hence, worldwide R&D efforts have begun to focus on the sub-terahertz band, a higher frequency range which has not been used for wireless communications to date.

In high-frequency device development, it is crucial to evaluate the frequency characteristics of the overall system, including active device gain and input and output impedance, as well as the board and connectors. Part of this process is measurement of the reflection and transmission characteristics of the amplitude and phase of signals emitted, known as S-parameters or scattering parameters. However, existing network analyzers can only measure frequency ranges up to 100GHz wide at one time, so when the signal characteristics of broader ranges must be evaluated, engineers have to repeatedly change the configuration of their equipment and measure again. This causes extra work, longer measurement times, and discontinuities in measured data. Measurement costs also rise proportionately to these drawbacks.

Advantest’s new technology promises to reduce these burdens significantly. It employs femtosecond optical pulsed laser as a signal source, enabling one-pass measurement of S-parameters up to 1.5THz with a broadband optical/electrical switching probe. The benefits of these efficiency gains will accrue to users in terms of time, labor, and cost savings.

High spatial resolution chip wiring quality analysis technology

Although continued shrinks of semiconductor circuits have facilitated generations of smaller, faster consumer electronics, Moore’s law is in danger of hitting a technological wall. To circumvent the physical limits of miniaturization, chipmakers are developing 3D semiconductors with multiple layers of circuits in a single package. However, wiring failure analysis is a major challenge in 3D chip development. With multiple boards stacked on top of each other, it is difficult to identify where wiring failures (open circuits, short-circuits, impedance mismatching) have occurred with X-ray inspection and other existing technologies. Generally, oscilloscope TDR (time domain reflectometry) and/or TDT (time domain transmissometry) is used to pinpoint these failures, but at these tiny geometries, extremely high spatial resolution is a must.

Because Advantest’s new technology uses a femtosecond optical pulsed laser as a signal source, it achieves superior spatial resolution of less than 5μm and a maximum measurement range of 300mm. With a successful track record of usage in the company’s terahertz spectroscopic and imaging systems, Advantest’s femtosecond optical pulsed laser boasts extremely high resolution. Moreover, the new technology provides a mapping function which can pinpoint the location of wiring failures on the device’s CAD data, making it an optimal tool for finding flaws in extremely complex, high-density circuits.

Advantest is planning to commercialize the new technology within its fiscal year 2015 (by the end of March, 2016).

Today, at the IEEE IITC conference, nano-electronics research center imec and Tokyo Electron Limited (TEL) presented a direct Cu etch scheme for patterning Cu interconnects. The new scheme has great potential to overcome resistivity and reliability issues that occur while scaling conventional Cu damascene interconnects for advanced nodes.

Aggressive scaling of damascene Cu interconnects leads to a drastic increase in the resistivity of the Cu wires, due to the fact that grain size is limited by the damascene trenches, which results in increased grain boundary and surface scattering. Additionally, the grain boundary negatively influences electromigration. When scaling damascene Cu interconnects, reliability issues occur because the overall copper volume is reduced and interfaces become dominant. Imec and TEL have demonstrated the feasibility of a direct Cu etch scheme to replace the conventional Cu damascene process. A key advantage of the direct Cu etch process is that it systematically results in larger grain sizes. Moreover, electromigration performance is preserved by applying an in-situ SiN cap layer that protects the Cu wires from oxidation and serves as the Cu interface.

Figure TEM section of copper etched lines encapsulated by SiN cap layer

Figure TEM section of copper etched lines encapsulated by SiN cap layer

The results were achieved in cooperation with imec’s key partners in its core CMOS programs GLOBALFOUNDRIES, Inc., Intel Corp, Micron Technology, Inc., Panasonic Corporation, Samsung Electronics Co., Ltd.,, Taiwan Semiconductor Manufacturing Co., Ltd., SK hynix Inc., Fujitsu Semiconductor Ltd., and SonyCorporation.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced it is offering a 28nm High-k Metal Gate (HKMG) radio frequency (RF) process technology that will provide power-efficient solutions for highly integrated mobile applications and connected devices. Based on GLOBALFOUNDRIES’ 28nm Super Low Power (SLP)technology with HKMG, the 28nm-SLP-RF process includes a comprehensive set of design capabilities enabling chip designers to integrate critical RF system-on-chip (SoC) functionality into their products.

“The proliferation of connected devices and IoT consumer applications has created an opportunity and demand for RF-enabled chips,” said Mike Mendicino, senior director of product management at GLOBALFOUNDRIES. “GLOBALFOUNDRIES’ RF-enabled 28nm process lowers design barriers and enables a broader range of customers to accelerate time-to-volume of leading-edge RF SoCs.”

The 28nm-SLP-RF process is built on the 28nm-SLP HKMG process. Silicon results have demonstrated high-frequency performance (Ft ~ 310GHz) and low flicker/thermal noise providing chip designers flexibility in optimizing core RF performance and functionality in a cost-effective logic platform. The 28nm-SLP-RF process technology is designed for the next generation of connected devices that require low standby power and long battery life integrated with RF/wireless functionality.  The technology is enabled with key RF features, including core and I/O (1.5V/1.8V) transistor RF models along with 5V LDMOS devices, which simplifies RF SoC design. For passive RF devices, 28nm-SLP-RF offers alternate polarity metal-oxide-metal (APMOM) capacitors up to 5V, deep n-well devices, diffusion, poly and precision resistors, inductors and an ultra-thick metal (UTM) layer.  All RF-enabled devices are scalable, hardware verified across the entire operating range, and have met industry standard reliability qualification requirements.  Volume production of the 28nm-SLP platform started in 2012.

GLOBALFOUNDRIES’ 28nm-SLP-RF technology utilizes the companies’ production-proven, 28nm-SLP silicon-validated design flows, which include a complete set of libraries, compilers, and complex IP. The company has collaborated with leading companies in the EDA/IP ecosystem to deliver an optimized process design kit (PDK) that supports highly accurate RF SPICE models and comprehensive technology files that are integral to RF designs. GLOBALFOUNDRIES’ enhanced 28nm-SLP-RF PDK and verification method is available now.

During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD) of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7nm node and below.

As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. imec’s industrial affiliation program on advanced interconnects is exploring novel metallization methods to solve these issues. One way to solve the problem is to identify integration and metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with Cobalt (Co) as an alternative metal to Copper (Cu). Moreover, the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

The results were achieved in cooperation with imec’s key partners as part of its core CMOS programs: GlobalFoundries, Intel, Samsung, SK hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.

Applied Materials, Inc. today announced its Applied Endura Cirrus  HTX PVD system with breakthrough technology for patterning copper interconnects at 10nm and beyond. As chip features continue to shrink, innovations in hardmask are required to preserve the pattern integrity of tightly packed, tiny interconnect structures.With the introduction of this technology, Applied enables scaling of the TiN metal hardmask – the industry’s material of choice – to meet the patterning needs of copper interconnects in advanced microchips.

“Precision engineering of metal hardmask films is key to addressing the patterning challenges for advanced interconnects,” said Dr. Sundar Ramamurthy, vice president and general manager of Applied’s Metal Deposition Products business unit. “The Cirrus HTX TiN product represents Applied’s decades of expertise in applying PVD technology for engineering TiN film properties. Incorporating our unique VHF-based technology offers customers the flexibility of tuning stress in TiN films from compressive to tensile to overcome their specific integration challenges.”

Today’s advanced microchips can pack 20 kilometers of copper wiring in a 100 square millimeter area, stacked in 10 layers with up to 10 billion vias or vertical connections between layers. The role of the metal hardmask is to preserve the integrity of these patterned lines and vias in soft ULK dielectrics. However, with scaling, the compressive stress from conventional TiN hardmask layers can cause the narrow lines patterned in ULK films to deform or collapse. The tunable Cirrus HTX TiN hardmask with high etch selectivity delivers superior CD line width control and via overlay alignment resulting in yield improvement.

This breakthrough in TiN hardmask is made possible by precision materials engineering at the wafer level to produce a high density, low-stress film. Combining exceptional film thickness uniformity with low defectivity on a proven Endura platform, the Cirrus HTX system addresses the stringent high volume manufacturing needs of patterning multiple interconnect layers.

Applied Materials, Inc. is a developer precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, through its Silicon Storage Technology (SST) subsidiary, and GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced the full qualification and availability of SST’s 55nm embedded SuperFlash non-volatile memory (NVM) on GLOBALFOUNDRIES’ 55nm Low Power Extended (LPx)/ RF enabled platform. The qualification of GLOBALFOUNDRIES’ 55nm, split-gate-cell SuperFlash technology-based process was performed according to JEDEC standards. This process technology also met the requirements of AEC-Q100 Grade 1 qualification with an ambient temperature range of -40°C to 125°C, and demonstrated endurance of 100K program/erase cycles with more than 20 years of data retention at 150°C.

According to global information company IHS, the automotive semiconductor market is forecast to reach $31B in 2015, with a strong 7.5 percent improvement over 2014. Embedded Flash-based semiconductors are a key component of this market segment.

“Embedded SuperFlash memory is a de-facto standard at foundries for microcontrollers, smartcards, and various system-on-chip devices,” said Mark Reiten, vice president of Technology Licensing for SST, a wholly owned subsidiary of Microchip. “GLOBALFOUNDRIES has been a great partner for building a 55nm embedded SuperFlash platform, and we are already engaged with several customers in various market segments. We are pleased to partner with GLOBALFOUNDRIES, to further strengthen our market leadership in embedded Flash-based devices.”

“GLOBALFOUNDRIES recognizes the need to provide a low-cost embedded Flash platform for secure ID, mixed-signal, NFC/RF and next-generation IoT applications,” said Gregg Bartlett, senior vice president of product management at GLOBALFOUNDRIES. “Our deep collaboration with SST has resulted in qualified, commercially available 55nm SuperFlash technology on GLOBALFOUNDRIES’ high-yielding 55nm low-power process platform, which will enable high-performance solutions for customers across key market segments.”

GLOBALFOUNDRIES’ 55nm LPx/RF platform, complete with eNVM technology, is available to customers now. This platform technology offers a fast path-to-product solution, with a custom library of off-the-shelf eNVM IP blocks that are optimized for specific MCU product applications.