Tag Archives: letter-ap-tech

New tests show in real-time that cracks can run on top of and through metal layers.

BY K. VANSTREELS, I. DE WOLF, H. ZAHEDMANESH, H. BENDER, M. GONZALEZ, J. LEFEBVRE, AND S. BHOWMICK, imec, Leuven, Belgium

Imec, with the help of equipment supplier Hysitron, developed a new test method to study crack formation in Cu/low-k back-end-of-line (BEOL) stacks. By combining a PicoIndenter, a scanning electron microscope (SEM) and unique sample preparation using a focused ion beam (FIB), it becomes possible to visualize in real-time crack initiation and propagation (See video). Insight into this reliability issue allows to optimize BEOL design, material choices and process steps to strengthen the BEOL.

Porosity of low-k materials affects the BEOL’s mechanical strength

Porous low-k materials are introduced in the BEOL of chips to improve its performance. More specifically, low-k materials prevent leakage between metal interconnections of the circuitry and minimize the time delay. In research, low-k materials with k-values lower than 2.0 are tested. These are very porous and reduce the mechanical strength of the BEOL stack.

SEM picture of crack formation in the back-end-of-line.

SEM picture of crack formation in the back-end-of-line.

Due to the reduced mechanical strength of Cu/ low-k BEOL stacks, cracks can be formed when local mechanical stresses become too high. This can occur during chip processing, during packaging, and during use of the end products. The stresses can be caused by temperature fluctuations, due to thermal mismatch of materials; or by shrinkage of materials during curing; by local forces during bonding; or even due to external mechanical impact caused by drop or shock. Since this crack formation is an important reliability issue for future technology nodes, tests are being developed to gain insight into this problem. For example, there is the four-point bending test and the BABSI test which measure the force at which cracking starts. However, with these tests it is not possible to follow in-situ and in real-time how the crack initiates and propagates through the BEOL stack. With the new test method, this hidden world reveals itself.

The new test

FIGURE 1. Schematic overview of the sample preparation. Using a Focus Ion Beam, a double clamped BEOL beam sample is made.

FIGURE 1. Schematic overview of the sample preparation. Using a Focus Ion Beam, a double clamped BEOL beam sample is made.

For the new test, a PicoIndenter is integrated into a SEM microscope. The sample has to be prepared in such a way that a beam is formed out of the back-end- of-line stack (see FIGURE 1). Imec was able to make such BEOL beams with the Focused Ion Beam (FIB) technique. This involved several steps as depicted in FIGURE 1. The sample is then placed in the SEM. With the PicoIndenter, a gradual force is applied on top of the beam while the SEM continuously images the cross-section of the BEOL (side view of the beam). In this way, a movie can be made revealing the crack initiation and propagation, while at the same time measuring the force that is applied (FIGURE 2).

FIGURE 2. Force-displacement curve and corresponding SEM pictures, as measured with the new test method. The pictures reveal beam bending (a to c), crack initiation (d) and crack growth (e to h).

FIGURE 2. Force-displacement curve and corresponding SEM pictures, as measured with the new test method. The pictures reveal beam bending (a to c), crack initiation (d) and crack growth (e to h).

Conclusions and future work

This new test has proven to be very relevant for further development of Cu/low-k BEOL stacks. In this phase, only a few BEOL beams – with different dimensions – were tested and measured. From these initial results it can be concluded that cracks run on top of metal layers in this device, and even through metal layers. This can point out that the interface at the top of metal layers should be strengthened for the studied technology, either by BEOL design, material choices or optimization of process steps (such as cleaning).

By setting up more experiments, a model can be made (FEM) to predict crack formation in specific BEOL stacks. The experiments will allow to validate the model. In this way, this new test method is an important tool in the development of reliable chips made in future technology nodes with copper and low-k materials in the back-end-of-line.

This article is based on the paper “In-situ scanning electron microscopy study of fracture events during back-end-of-line microbeam bending tests” which was published in Applied Physics Letters 105, 213102 (2014). AUTHORS: K. VANSTREELS, I. DE WOLF, H. ZAHEDMANESH, H. BENDER, M. GONZALEZ, J. LEFEBVRE, AND S. BHOWMICK

Synthetic diamond heat spreaders and GaN-on-Diamond wafers have emerged as a leading thermal-management technology for RF Power Amplifiers

BY THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER,
Element Six Technologies, Santa Clara, CA & MARTIN KUBALL AND JULIAN ANAYA, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, Bristol, U.K.

GaN-based transistors and their related RF Power Amplifiers (PAs) have emerged as the leading solid-state technology to replace traveling wave tubes in radar, EW (Electronic warfare) systems, and satellite communications, and to replace GaAs transistors in cellular base stations. However, significant thermal limitations prevent GaN PAs from reaching their intrinsic performance capability. Metallized synthetic diamond heat spreaders have recently been used to address this thermal management challenge, particularly in cellular base station and military radar applications.

This article covers several important issues that advanced thermal solutions, particularly for RF power amplifiers, must address. Here, we are presenting new materials, such as CVD (chemical vapor deposition) diamond as a heat spreader to reduce overall package thermal resistance compared to today’s more commonly used materials for thermal management. Also, mounting aspects and some new developments regarding the thermal resistance at the bonding interfaces to diamond heat spreaders are discussed.

CVD diamond

Diamond possesses an extraordinary set of properties including the highest known thermal conductivity, stiffness and hardness, combined with high optical transmission across a wide wavelength range, low expansion coefficient, and low density. These characteristics can make diamond a material of choice for thermal management to significantly reduce thermal resis- tance. CVD diamond is now readily commercially available in different grades with thermal conductivities ranging from 1000 to 2000 W/mK. Also very important is the fact that CVD diamond can be engineered to have fully isotropic characteristics, enabling enhanced heat spreading in all directions. FIGURE 1 shows a comparison of the thermal conductivity of CVD diamond with other materials traditionally used for heat spreading purposes.

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

On-going development in the technologies to synthesize CVD diamond has enabled it to become readily available in volume at acceptable costs. Unmetallized CVD diamond heat spreaders are available today at a typical volume cost of $1/mm3. Prices vary dependant on the thermal-conductivity grade used. In some instances, system operation at elevated temperatures can reduce both the initial cost of the cooling sub-system and the on-going operating cost as well. When applied with appropriate die-attach methods, diamond heat spreaders provide reliable solutions for semiconductor packages with significant thermal management challenges [1].

Application notes for the use of CVD Diamond

To obtain the most effective use of the extreme properties of CVD Diamond in overall system design, package integration issues need to be carefully considered. Failure to address any one of these issues will result in a sub-optimal thermal solution. Here are the most important points to be considered:

  • Surface preparation
  • Mounting techniques
  • Diamond thickness
  • Functional considerations
  • Metallizations and thermal barrier resistance

Surface preparation: The surfaces of die-level devices have to be machined in a suitable fashion to allow good heat transfer. Surface flatness for heat spreaders should typically be less than 1 micron/mm and the roughness better than Ra < 50 nm, which can be achieved by polishing techniques. Any deficiency in flatness must be compensated for by the mounting techniques which will cause higher thermal resistance.

Mounting techniques: Whereas in some advanced device applications, such as high-power laser diodes, atomic-force bonding techniques are being considered, most applications currently employ soldering techniques for die attachment to the heat spreader. Again, solder layers should be kept to minimum thickness, particularly for the primary TIM1 (thermal interface material (TIM) between die and heat spreader), to minimize thermal resistance. An important factor in applying solder joints is the expansion mismatch between the CVD diamond and the semiconductor material, as it can significantly influence performance and lifetime. GaAs (Gallium Arsenide) devices up to an edge length of 2.5 mm can be hard soldered to CVD diamond without CTE-mismatch problems. (Note that the CTE for CVD Diamond is 1.0 ppm/K at 300K). For edge lengths greater than 2.5 mm, using a soft solder can avoid excessive stresses in the device. TABLE 1 shows a wide range of solder materials commercially available to address various needs for soldering processes.

TABLE 1. Summary of soldering materials [2].

TABLE 1. Summary of soldering materials [2].

Diamond thickness: The thickness of the CVD diamond is important. For devices with small hot spots, such as RF amplifiers or laser diodes, a thickness of 250 to 400 microns is sufficient. Diamond’s isotropic characteristics effectively spread the heat to reduce maximum operation temperature at constant power output. However, applications with larger heat spots on the order of 1 to 10 mm in diameter require thicker diamond for better results. An example is disk lasers that can have an optical output power of several kW and a power density of about 2kW/cm2; a diamond thickness of several mm has proven to be beneficial to disk laser operation [3].

Functional considerations: There are also functional requirements that may be important. One is the electrical conductivity of the heat spreader. For devices such as laser diodes, it is easiest to run the drive current through the device and use the heat spreader for the ground contact. For other devices, the heat spreader is required to be insulating. As CVD diamond is an intrinsic insulator, this insulation can be maintained by keeping the side faces free of metallization. This could be required for RF amplifiers and transistors, especially at higher frequencies (f > 2 GHz).

Thermal simulation helps optimize the heat spreader configuration to find the best solution based on power output needs, material thickness, metallization scheme, heat source geometry and package configuration. For design optimization, it is important that the thermal simulation model includes the complete junction-to-case system, including the device details, all interfaces, materials and the subsequent heat sinking solution.

Metallizations and thermal barrier resistance

Metallizations are an essential component to the application of CVD diamond in RF Amplifier and similar applications. Typically, for reasons of adhesion, mechanical and thermal robustness, three-layer metallization schemes are used. An example of such a three-layer metallization scheme fundamentally comprises: a) a carbide forming metal layer which forms a carbide bonding to the diamond component; b) a diffusion barrier metal layer disposed over the carbide forming metal layer; and c) a surface metal bonding layer disposed over the diffusion barrier metal which provides both a protective layer and a wettable surface layer onto which a metal solder or metal braze can be applied to bond the diamond heat spreader to die and other device components. A particular example of such a three-layer metalli- zation scheme is Ti / Pt / Au.

High-quality, sputter-deposited, thin-film metallizations are strongly recommended for advanced thermal solutions. As thermal contact resistance between the device
and the heat spreader must be minimized, any additional metal interface being added to the system must be avoided. Sputtered layers, especially of titanium, can form a very effective chemical bond with CVD diamond to ensure long-term stability even at elevated temperatures. To separate the required gold attach layer from the titanium adhesion layer, a platinum or titanium/tungsten (TiW) barrier layer is recommended. The Ti/Pt/Au scheme is very commonly used in high-end devices and has excellent characteristics with regards to stability and endurance, even over extended lifetime periods under changing thermal loads. However, this scheme also has a drawback, as the thermal conductivities of the titanium and platinum are relatively low (Tc=22 W/ mK and Tc=70 W/mK respectively). In the search for improved materials to be applied, the use of chromium has been identified as a viable alter- native. Chromium forms a carbide with diamond and is also readily used as a barrier layer, enabling it to perform both functions at a relatively high thermal conductivity of Tc=93.9 W/mk. To test the thermal effectiveness of chromium, samples were prepared at the CDTR (Centre for Device Thermog- raphy and Reliability) at Bristol University comparing a standard Ti/Pt/Au (100/120/500nm) metallization with this novel Cr/Au (100/500nm) configuration. The measurements of the thermal conductivity revealed that the thermal conduc- tivity of the Cr/Au metallization is about 4 times higher as compared to the Ti/Pt/Au. Results are shown in FIGURE 2.

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

Application example

To demonstrate the impact of this Cr adhesion/ barrier layer advantage versus Ti/Pt/Au, high power GaN on SiC HEMT (High Electron Mobility Transistor) devices were mounted to a CVD Diamond heat spreader. A cap layer of AuSn with a thickness of 25 microns was chosen. To ensure comparable results for all samples prepared, these samples were placed on a temperature stable platform also made from high thermally conductive diamond material. Results are shown in FIGURE 3: In the left diagram, the base temperature is plotted for increasing power output from the device. As can be seen, the temperature for the Cr/Au configuration is significantly lower, at 9W device power output by about 10 degrees C. On the right hand side, the graph shows the temperature as measured on the transistor channel directly.

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

In this case, the lower thermal resistivity of the Cr-based metallization layer decreases the channel temperature by more than 20 degrees C at 9W power output.

This significant temperature reduction will result in as much as a 4 times longer lifetime of the device. Alternatively, such devices could be packaged in smaller footprints, at higher power densities, to make use of this increased effectiveness in heat spreading.

Outlook, future developments

One important finding from the above example is the need to modify device architecture for improved thermal management. The main temperature rise is within the device itself. Here, a thinning of the substrate, to bring it closer to the diamond heat spreader, would further enhance the thermal design. Also, mounting such devices with the active layers facing the diamond would provide even further benefit. An example would be the mounting laser diodes p-face down with the quantum well structures soldered directly against the heat spreader. Another way to bring the device gate junction closer to the diamond is the use of a different substrate altogether. This has been demonstrated by using GaN (Gallium Nitride) on diamond wafers, which remove both the Si substrate and transition layers, replacing them instead with CVD diamond [5]. The result brings the diamond material within 1 micron of the heat generating gate junctions. Initial users of GaN-on-diamond wafers for RF HEMT devices have demon- strated as much as 3 times the power density when compared to equivalent GaN/SiC (Silicon Carbide) devices, today’s leading technology for advanced power devices. [6]

Summary

As can be seen, significant thermal-management improvements to electronic systems can be realized by using advanced materials such as CVD diamond. The integration can be relatively straightforward as the diamond heat spreader can be a direct replacement to AlN (Aluminium nitride), BeO (Berillium oxide) or other advanced ceramics. Attention to detail at the interfaces, both in terms of the choice of metals and its thickness, is important to keep overall thermal resistance low and thereby optimizing the effectiveness of the diamond.

As CVD diamond becomes more attractive as a heat spreader through improved synthesis technology, advanced processing and on-going cost reduction efforts, its use in high power density applications has been increasing. It is expected that this trend will be continued in the years to come in line with the ever increasing need for smaller and more powerful electronic devices and systems.

References

1. R. Balmer, B. Bolliger “Integrating Diamond to Maximize Chip Reliability and Performance,“ in Chip Scale Review, July/August 2013, pp. 26 – 30.
2. Internal Element Six Technologies research and report.
3. Element Six internal thermal simulation, C. Bibbe, 2006.
4. GaN-on-Diamond High-Electron-Mobility Transistor – Impact of Contact and Transition Layers, J.Anaya, J.W. Pomeroy, M. Kuball, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, BS8 1TL Bristol, U.K.
5. G.D. Via, J.G. Felbinger, J. Blevins, K. Chabak, G. Jessen, J. Gillespie, R. Fitch, A. Crespo, K. Sutherlin,
B. Poling, S. Tetlak, R. Gilbert, T. Cooper, R. Baranyai, J.W. Pomeroy, M. Kuball, J.J. Maurer, and A. Bar-Cohen,
“Wafer-Scale GaN HEMT Performance Enhancement
by Diamond Substrate Integration” in 10th Interna- tional Conference on Nitride Semiconductors, ICNS-10, August 25-30, 2013, Washington DC, USA.
6. M. Tyhach, D. Altman, and S. Bernstein, “Analysis and Characterization of Thermal Transport in GaN HEMTs on SiC and Diamond Substrates”, in GOMACTech 2014, March 31-April 3, 2014, Charleston, SC, USA.

THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER, Element Six Technologies, Santa Clara, CA

MARTIN KUBALL AND JULIAN ANAYA, Center For Device Thermography And Reliability (Cdtr), H. H. Wills Physics Laboratory, University Of Bristol, Bristol, U.K. contact: [email protected]

By Pete Singer, Editor-in-Chief

Although the Xpedition was announced last week, it has been used in production for over two years. says five companies have been using it, two of which are extremely large semiconductor companies. “It’s a pretty mature technology,” he said.

Traditionally, chip, package and board designers have used relatively archaic means of communicating, including spreadsheets, whiteboard drawings and Microsoft’s VISIO (a diagramming and vector graphics application). Each group often uses different naming conventions as well, which further complicates co-design efforts.

“They try to use non-EDA technology to figure out an EDA problem,” said John Park, Methodology Architect, Systems Design Division at Mentor Graphics (Longmont, CO).

A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.

Xpedition allows designers to pull in existing data in whatever form they’re presently using and examine different design considerations such as connectivity across all three design domains. “We’re aggregating people’s existing flow. We’re not replacing them,” Park said.

Park said the development of Xpedition was driven by the general need to simplify co-design, but also to address news challenges created by the Internet of Things (IoT) and new technology such as 2.5 and 3D integration and through-silicon-vias (TSVs). “You’re talking fairly sophis- ticated connectivity management when dealing with multiple die, the interposer and modeling that connec- tivity all the way up to the boards,” Park said. “It’s a pretty challenging problem for most people who have historically tried to use spreadsheets to manage that cross-domain connectivity.”

The Xpedition Package Integrator product also provides the industry’s first formal flow for ball grid array (BGA) ball-map planning and optimization based on an “intelligent pin” concept, defined by user rules. In addition, a new multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic) provides cross-domain pin-mapping and system level cross-domain logical verification (FIGURE 1).

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in the design environment in which they are most comfortable.

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in
the design environment in which they are most comfortable.

A modern day CPU or GPU has three of four packaging options, such as package-on-package, micro-BGA, or package-on-package (PiP). People are also targeting multiple end form factors. “It’s not a single board anymore,” Park said. “A lot of customers want to look at the device in the context of smartphone platform, a tablet platform or a set-top box platform, for example.”

One of the main advantages of the new platform is cost reduction by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process. “What’s really changing with IoT and with TSVs and expensive packages is people now want to do cross-domain exploration or path finding,” Park said. People evaluate options largely based on cost, performance and reliability. For example, designers want to look at the pros and cons if they take DRAM off the board and move them into the package.

In 2013 James Hone, Wang Fong-Jen Professor of Mechanical Engineering at Columbia Engineering, and colleagues at Columbia demonstrated that they could dramatically improve the performance of graphene–highly conducting two-dimensional (2D) carbon–by encapsulating it in boron nitride (BN), an insulating material with a similar layered structure. In work published this week in the Advance Online Publication on Nature Nanotechnology‘s website, researchers at Columbia Engineering, Harvard, Cornell, University of Minnesota, Yonsei University in Korea, Danish Technical University, and the Japanese National Institute of Materials Science have shown that the performance of another 2D material–molybdenum disulfide (MoS2)–can be similarly improved by BN-encapsulation.

“These findings provide a demonstration of how to study all 2D materials,” says Hone, leader of this new study and director of Columbia’s NSF-funded Materials Research Science and Engineering Center. “Our combination of BN and graphene electrodes is like a ‘socket’ into which we can place many other materials and study them in an extremely clean environment to understand their true properties and potential. This holds great promise for a broad range of applications including high-performance electronics, detection and emission of light, and chemical/bio-sensing.”

Two-dimensional (2D) materials created by “peeling'” atomically thin layers from bulk crystals are extremely stretchable, optically transparent, and can be combined with each other and with conventional electronics in entirely new ways. But these materials–in which all atoms are at the surface–are by their nature extremely sensitive to their environment, and their performance often falls far short of theoretical limits due to contamination and trapped charges in surrounding insulating layers. The BN-encapsulated graphene that Hone’s group produced last year has 50× improved electronic mobility–an important measure of electronic performance–and lower disorder that enables the study of rich new phenomena at low temperature and high magnetic fields.

“We wanted to see what we could do with MoS2–it’s the best-studied 2D semiconductor, and, unlike graphene, it can form a transistor that can be switched fully ‘off’, a property crucial for digital circuits,” notes Gwan-Hyoung Lee, co-lead author on the paper and assistant professor of materials science at Yonsei. In the past, MoS2 devices made on common insulating substrates such as silicon dioxide have shown mobility that falls below theoretical predictions, varies from sample to sample, and remains low upon cooling to low temperatures, all indications of a disordered material. Researchers have not known whether the disorder was due to the substrate, as in the case of graphene, or due to imperfections in the material itself.

In the new work, Hone’s team created heterostructures, or layered stacks, of MoS2 encapsulated in BN, with small flakes of graphene overlapping the edge of the MoS2 to act as electrical contacts. They found that the room-temperature mobility was improved by a factor of about 2, approaching the intrinsic limit. Upon cooling to low temperature, the mobility increased dramatically, reaching values 5-50× that those measured previously (depending on the number of atomic layers). As a further sign of low disorder, these high-mobility samples also showed strong oscillations in resistance with magnetic field, which had not been previously seen in any 2D semiconductor.

“This new device structure enables us to study quantum transport behavior in this material at low temperature for the first time,” added Columbia Engineering PhD student Xu Cui, the first author of the paper.

By analyzing the low-temperature resistance and quantum oscillations, the team was able to conclude that the main source of disorder remains contamination at the interfaces, indicating that further improvements are possible.

“This work motivates us to further improve our device assembly techniques, since we have not yet reached the intrinsic limit for this material,” Hone says. “With further progress, we hope to establish 2D semiconductors as a new family of electronic materials that rival the performance of conventional semiconductor heterostructures–but are created using scotch tape on a lab-bench instead of expensive high-vacuum systems.”

The ability of materials to conduct heat is a concept that we are all familiar with from everyday life. The modern story of thermal transport dates back to 1822 when the brilliant French physicist Jean-Baptiste Joseph Fourier published his book “Théorie analytique de la chaleur” (The Analytic Theory of Heat), which became a corner stone of heat transport. He pointed out that the thermal conductivity, i.e., ratio of the heat flux to the temperature gradient is an intrinsic property of the material itself.

The advent of nanotechnology, where the rules of classical physics gradually fail as the dimensions shrink, is challenging Fourier’s theory of heat in several ways. A paper published in ACS Nano and led by researchers from the Max Planck Institute for Polymer Research (Germany), the Catalan Institute of Nanoscience and Nanotechnology (ICN2) at the campus of the Universitat Autònoma de Barcelona (UAB) (Spain) and the VTT Technical Research Centre of Finland (Finland) describes how the nanometre-scale topology and the chemical composition of the surface control the thermal conductivity of ultrathin silicon membranes. The work was funded by the European Project Membrane-based phonon engineering for energy harvesting (MERGING).

The results show that the thermal conductivity of silicon membranes thinner than 10 nm is 25 times lower than that of bulk crystalline silicon and is controlled to a large extent by the structure and the chemical composition of their surface. Combining state-of-the-art realistic atomistic modelling, sophisticated fabrication techniques, new measurement approaches and state-of-the-art parameter-free modelling, researchers unravelled the role of surface oxidation in determining the scattering of quantized lattice vibrations (phonons), which are the main heat carriers in silicon.

Both experiments and modelling showed that removing the native oxide improves the thermal conductivity of silicon nanostructures by almost a factor of two, while successive partial re-oxidation lowers it again. Large-scale molecular dynamics simulations with up to 1,000,000 atoms allowed the researchers to quantify the relative contributions to the reduction of the thermal conductivity arising from the presence of native SiO2 and from the dimensionality reduction evaluated for a model with perfectly specular surfaces.

Silicon is the material of choice for almost all electronic-related applications, where characteristic dimensions below 10nm have been reached, e.g. in FinFET transistors, and heat dissipation control becomes essential for their optimum performance. While the lowering of thermal conductivity induced by oxide layers is detrimental to heat spread in nanoelectronic devices, it will turn useful for thermoelectric energy harvesting, where efficiency relies on avoiding heat exchange across the active part of the device.

The chemical nature of surfaces, therefore, emerges as a new key parameter for improving the performance of Si-based electronic and thermoelectric nanodevices, as well as of that of nanomechanical resonators (NEMS). This work opens new possibilities for novel thermal experiments and designs directed to manipulate heat at such scales.

Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node. The new extensions include modeling of variation effects due to multi-patterning technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) (member list available at www.imtab.org), an IEEE-ISTO Federation Member Program, to define and ratify these new extensions. They will be available in the upcoming open-source ITF version 2015.06.

“Enabling productive design and analysis for a colored layout flow, while also providing a solution to model increased parasitic variation due to MPT approaches, is critical at 10nm,” said Bari Biswas, vice president of engineering for extraction solutions at Synopsys and chair of IMTAB. “Through our collaboration with IMTAB members and leading foundries, Synopsys developed an innovative solution that extended the existing variation models in ITF to become intrinsically color-aware to more accurately model mask dependency while fitting seamlessly into a designer’s existing flow.”

“ITF continues to be the cornerstone of parasitic modeling in the semiconductor industry,” said Marco Migliaro, President, IEEE-ISTO. “The new 10nm models represent the fourth successive generation of model extensions fostered by the IMTAB consortium.  IEEE-ISTO looks forward to continuing our support of the IMTAB mission to drive increased tool interoperability through the ITF common open-source modeling format.”

MPT is an evolution of the double patterning technology (DPT) first introduced by foundries at the 20nm process node, and it further extends the use of immersion lithography to 10nm and below. However, MPT imposes tighter requirements on design implementation and analysis to support layout decomposition into different masks (coloring) and manage increased variation due to misalignment of the multiple masks. Synopsys’ advanced MPT solution ratified by IMTAB for 10 nm includes color-aware models that cover all leading foundry manufacturing techniques including sequential litho-etch patterning, for example, triple patterning (LELELE) and quadruple patterning (LELELELE), as well as spacer-assisted/self-aligned patterning, for example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

In addition to MPT modeling, Synopsys has introduced other ITF extensions approved by IMTAB for more accurate via resistance and device capacitance extraction at advanced FinFET process nodes. At 10nm, via resistivity has increased significantly with growing conductor environment context, so the existing self-aligned via resistance variation model has been extended to include coverage from top and bottom conductors. In addition, new ITF models have been added to accurately extract the floating gate to diffusion contact capacitance for polycide on diffusion edge (PODE) devices and spacer dielectric between gate polycide and contact, both of which are critical to regulating device performance.

More information on the new ITF extensions for 10nm can be found in the ITF specifications version 2015.06, targeted for release in June 2015.

Additional proposals for 10nm and below process modeling are planned for review in the next IMTAB meeting scheduled for Tuesday, June 9, 2015 in San Francisco, CA, USA.

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products announced today that it has kicked-off an Internet of Things (IoT) task force and will offer diversified products with ultra-low power technology in anticipation of the fast growing IoT market. Gartner estimates that the processing, sensing and communications segments of the IoT market will grow at a compound annual growth rate (CAGR) of 29.2 percent from $7B in 2013 to $43B by 2020. This rapid growth rate outpaces the rest of the semiconductor industry which is predicted to grow at a rate of 4.6 percent over the same period.

MagnaChip offers a 0.18 micron ultra-low power technology that enables System-on-a-Chip (SoC) applications with low active and low stand-by power consumption. This new process features very low start-up voltage and enables DC-DC Boost Converters to be suitable for IoT applications. Another important technology feature is operational efficiency. This process allows for low electrical current draw, which is suitable for IoT devices such as solar cells, thermoelectric generators, vibration energy harvesters and electromagnetic harvesters.

Based on its already developed 0.18 micron ultra-low power technology, MagnaChip also plans to provide a diversified portfolio within the ultra-low power sector. This includes 0.13 micron ultra-low power EEPROM, Bipolar-CMOS-DMOS (BCD) and mixed-signal technologies. Ultra-low power technology is a key element for conserving energy usage within IoT devices. IoT applications demand an always on, low-power energy source and long battery life which are requirements that MagnaChip’s ultra-low power technology enables.

MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.

Furthermore, MagnaChip’s 0.13 and 0.18 micron BCD technologies support high-voltage (up to 100V) and high-efficiency power ICs such as voltage regulators and converters, Power-over-Ethernet and smart LED Lighting solutions, which are essential power elements in IoT applications. With the combination of power devices with lower Specific On-Resistance (Rsp, defined as drain-source resistance times device area, Rds*A), improved isolation and higher reliability, MagnaChip’s 0.13 and 0.18 micron BCD processes will help our foundry customers to design IoT products with smaller and more power efficient characteristics.

“We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets,” said YJ Kim, MagnaChip’s interim Chief Executive Officer. “MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”

Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830. Designed for characterization and monitoring of the diverse processes used in wafer-level packaging, CIRCL-AP enables all-surface wafer defect inspection, review and metrology at high throughput. The ICOS T830 provides fully automated optical inspection of integrated circuit (IC) packages, leveraging high sensitivity with 2D and 3D measurements to determine final package quality for a wide range of device types and sizes. Both systems help IC manufacturers and outsourced semiconductor assembly and test (OSAT) facilities address challenges, such as finer feature sizes and tighter pitch requirements, as they adopt innovative packaging techniques.

“Consumer mobile electronics continue to drive production of smaller, faster and more powerful devices,” stated Brian Trafas, chief marketing officer of KLA-Tencor. “Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency. The packaging production methods, however, are more complex—involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high aspect ratio etch, and unique processes, such as temporary bonding and wafer reconstitution. By combining our expertise in front-end semiconductor manufacturing process control with experience gained through collaborations at key R&D sites and industry consortia, we have developed flexible and efficient inspection solutions that can help address packaging challenges from wafer-level to final component.”

The CIRCL-AP includes multiple modules that utilize parallel data collection for fast, cost-efficient process control of advanced wafer-level packaging processes. It supports a range of packaging technologies, including wafer-level chip scale packaging, fan-out wafer-level packaging and 2.5D/3D IC integration using through silicon vias (TSVs). The industry-proven 8-Series serves as the CIRCL-AP’s front side defect inspection and metrology module, which couples LED scanning technology with automated defect binning to reduce nuisance and speed detection of critical packaging defects, such as TSV cracks and redistribution layer shorts. The CV350i module, based on KLA-Tencor’s VisEdge technology, enables leading detection, binning and automated review of wafer edge defects and metrology for critical edge trim and bonding steps in the TSV process flow. With multiple imaging and illumination modes, the Micro300 module can produce high precision 2D and 3D metrology for bump, redistribution and TSV processes. Utilizing a flexible architecture, the CIRCL-AP can be configured with one or more modules to address the requirements of specific packaging applications, while the handler supports bonded, thinned and warped substrates.

The ICOS T830 extends the industry-leading ICOS component inspection series to address yield challenges associated with advanced packaging types, including lead frame, fan-out wafer-level, flip-chip and stacked packages. Enhanced package visual inspection capability, xPVI, enables high sensitivity detection of top and bottom component surface defects, such as voids, scratches, pits, chips and exposed wires. To ensure quality standards are being met for leading-edge memory and logic packaged devices, the ICOS T830 offers high speed 3D ball, lead and capacitor metrology, package z-height measurement and component side inspection. The xCrack+ inspection station enables accurate detection of micro-crack defects—a key failure mechanism of thinner components used in mobile applications. The ICOS T830 incorporates high-throughput operation of four independent inspection stations and high-speed sorting of the inspected packaged components to achieve cost-effective component quality control.

Multiple CIRCL-AP systems in various configurations have been installed worldwide for use in development and production of TSV, fan-out wafer-level packaging and other wafer-level packaging technologies. ICOS T830 systems are in use at many worldwide IC packaging facilities, providing accurate feedback on package quality across a range of device types and sizes. To maintain the high performance and productivity demanded by semiconductor packaging providers, the CIRCL-AP and ICOS T830 systems are backed by KLA-Tencor’s global, comprehensive service network.

Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

Sponsored by Semiconductor Research Corporation (SRC), the Duke research focuses on testing of 3D integration since testing remains an obstacle that hinders mainstream adoption and mass manufacturing of 3D technology.

“Even though manufacturing processes for 3D integration are nearly mature, a barrier to technology adoption is our insufficient understanding of 3D testing issues and the need for design-for-testability (DFT) solutions,” said Krishnendu Chakrabarty, professor of Electrical and Computer Engineering at Duke. “Test challenges for 3D ICs must be addressed before high-volume production can be practical. Breakthroughs in  test technology will allow higher levels of silicon integration, fewer defect escapes, and commercial exploitation.”

The Duke research has introduced probing solutions that may enable pre-bond and post-bond testing of Through Silicon Vias (TSVs) and logic dies used in manufacturing semiconductor components. The Duke team has also introduced design-for-test (DFT) innovations for 3D stacked chip technologies.

Specifically, it is paramount to stack “known good dies” to ensure a high manfufacturing yield with stacked technology. However, due to the small feature sizes of TSVs and micro-bumps, it is extremely difficulty to probe wafers at a pre-bond stage. The Duke team has presented an innovative solution to this problem by probing multiple micro-bumps at the same time, thereby shorting TSVs and forming a TSV network. Aggregated measurements from TSV networks can then be used to detect defects in TSVs as well as in the die logic.

Furthermore, by developing the DFT structures that must be included on the die and the measurement infrastructure needed on the probe cards, the research demonstrates that the proposed approach is robust to process variations as well variations in contact resistance to the potentially non-uniform nature of probe contacts.

Next, in the area of post-bond testing, the Duke team developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The research included formal models based on integer linear programming as well as fast heuristic solutions. An especially innovative aspect of this research is its solution for recovering the delay overhead introduced by the DFT that is added for 3D stack testing.

“We have shown that retiming can be used to redistribute the slack on critical paths, whereby the delay overhead due to 3D DFT can be reduced to zero. This is a remarkable research breakthrough, which shows that there is something called a ‘free lunch’ after all,” said Brandon Noia, a Ph.D. student who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company, AMD, Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.

The Duke research has already led to three U.S. patents being granted in 2014, and multiple semiconductor and electronic design automation (EDA) companies are collaborating with the Duke team on incorporating the research into their test processes—with at least one company prepared to have measurement data on chips available this fall.

“Among all EDA challenges for 3D designs, tools and methodologies for 3D stacked IC testing are critical, and this research from Duke goes a long way toward removing these obstacles,” said William Joyner, SRC director of Computer-Aided Design and Test.

Synopsys, Inc. today announced that TSMC has concluded 16 nanometer FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10 nanometer (nm) certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys’ custom and digital design tools.  This certification enables mutual customers to deploy tools in Synopsys’ Galaxy Design Platform for 16nm production designs and 10nm early engagements. The certified platform delivers technologies including routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits (iPDKs) for FinFET processes. TSMC and Synopsys have collaborated to enhance new tool features based on both 16nm and 10nm technology requirements in Synopsys’ IC Compiler II place and route solution with TSMC validation.  This includes full-flow color enablement, support for connected poly on gate oxide and diffusion edge (CPODE) technology, layer optimization, low Vdd timing closure and support for signal electro-migration. The two companies are also working together to complete IC Compiler II certification for 16nm by the end of April and 10nm in June 2015.

“The combination of tool certification and our longstanding collaboration with Synopsys is enabling customers’ 16FF+ production ramp-up and early engagements at 10-nanometer,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.  “With a full suite of TSMC-certified digital, signoff, and custom implementation solutions from Synopsys, our mutual customers will achieve improved performance and lower power while attaining their time-to-market goals.”

“Our deep collaboration with TSMC on 16-nanometer and 10-nanometer FinFET processes allows our mutual customers to use silicon-proven FinFET tools to achieve predictable design closure with faster turnaround time,” said Bijan Kiani, vice president of product marketing in Synopsys’ Design Group. “With the latest certification for these two FinFET processes, designers can take advantage of this game-changing implementation technology for their next-generation chip designs.”