Tag Archives: letter-ap-tech

Micron Technology, Inc. and Intel Corporation today revealed the availability of their 3D NAND technology, the world’s highest-density flash memory. Flash is the storage technology used inside the lightest laptops, fastest data centers, and nearly every cellphone, tablet and mobile device.

3D_NAND_Die_with_M2_SSD

This new 3D NAND technology, which was jointly developed by Intel and Micron, stacks layers of data storage cells vertically with extraordinary precision to create storage devices with three times higher capacity than competing NAND technologies. This enables more storage in a smaller space, bringing significant cost savings, low power usage and high performance to a range of mobile consumer devices as well as the most demanding enterprise deployments.

Planar NAND flash memory is nearing its practical scaling limits, posing significant challenges for the memory industry. 3D NAND technology is poised to make a dramatic impact by keeping flash storage solutions aligned with Moore’s Law, the trajectory for continued performance gains and cost savings, driving more widespread use of flash storage.

“Micron and Intel’s collaboration has created an industry-leading solid-state storage technology that offers high density, performance and efficiency and is unmatched by any flash today,” said Brian Shirley, vice president of Memory Technology and Solutions at Micron Technology. “This 3D NAND technology has the potential to create fundamental market shifts. The depth of the impact that flash has had to date—from smartphones to flash-optimized supercomputing—is really just scratching the surface of what’s possible.”

“Intel’s development efforts with Micron reflect our continued commitment to offer leading and innovative non-volatile memory technologies to the marketplace,” said Rob Crooke, senior vice president and general manager, Non-Volatile Memory Solutions Group, Intel Corporation. “The significant improvements in density and cost enabled by our new 3D NAND technology innovation will accelerate solid-state storage in computing platforms.”

Innovative Process Architecture

One of the most significant aspects of this technology is in the foundational memory cell itself. Intel and Micron chose to use a floating gate cell, a universally utilized design refined through years of high-volume planar flash manufacturing. This is the first use of a floating gate cell in 3D NAND, which was a key design choice to enable greater performance and increase quality and reliability.

The new 3D NAND technology stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package. These capacities can enable gum stick-sized SSDs with more than 3.5TB of storage and standard 2.5-inch SSDs with greater than 10TB. Because capacity is achieved by stacking cells vertically, the individual cell dimensions can be considerably larger. This is expected to increase both performance and endurance and make even the TLC designs well-suited for data center storage.

M/A-COM Technology Solutions Inc., a supplier of high-performance analog RF, microwave and optical semiconductor products, today announced the new MAGX-000912-650L00 and MAGX-000912-650L0S, a 650 W gallium nitride (GaN) on silicon carbide (SiC) HEMT pulsed power transistor for L-band pulsed avionics applications. This transistor is available in standard flange or earless flange packaging.

The MAGX-000912-650L00/MAGX-000912-650L0S is a gold metalized, internally matched, GaN on SiC depletion mode RF power transistor. Operating in the 960 to 1215 MHz frequency range, the MAGX-000912-650L0x is a rugged and robust transistor, boasting a mean time to failure (MTTF) of 600 years.

The internally matched MAGX-000912-650L0x features 650 W of peak output power with 20 dB typical gain and 62 percent drain efficiency. The semiconductor structure is designed to achieve a high drain breakdown voltage (BVdss), which enables reliable and stable operation at 50V in extreme mismatched load conditions unparalleled with older semiconductor technologies. Other features include flat gain versus frequency performance and a common-source configuration for broadband class AB operation.

The MAGX-000912-650L0x was developed using wafer fabrication processes, and provides customers with high gain, efficiency, bandwidth and ruggedness to meet today’s demanding application needs. This transistor is optimized for civilian and military pulsed avionics amplifier applications in the 960 to 1215 MHz range, for Mode-S, TCAS, JTIDS, DME and TACAN operation.

“The transistor is a clear leader in high pulsed power GaN technology with 650 W of output power combined with excellent gain, efficiency and rugged performance,” said Gary Lopes, Senior Product Director, MACOM. “The device is an ideal candidate for customers looking to upgrade L-Band avionics systems to the next level of pulsed power performance and experience the solid reliability that is offered by MACOM GaN solutions.”

Microsemi Corporation, a provider of semiconductor solutions differentiated by power, security, reliability and performance, today introduced its second generation highly secure 64 gigabyte (GB) solid state drive (SSD). With data security threats increasing, Microsemi specifically designed its latest SSD for market applications where data protection is of the utmost importance. It overcomes malicious attack concerns with Microsemi’s unique factory firmware lockdown technology to prevent covert firmware repurposing. Offered in a 32mm x 28mm ball grid array (BGA) package, the new SSD is highly optimized for embedded computers in harsh environments.

Microsemi’s new 64GB SSD is a self-encrypting drive that delivers multiple key management methods and advanced security features based on the company’s proven Microsemi Armor III processor technology.  For sensitive applications, the encryption key can be erased in less than 30 milliseconds (ms) and a second security layer can be activated to erase the entire storage media in less than 10 seconds, virtually rendering data forensically unrecoverable.

“Embedded computing applications have increased the need for compact small form factor, highly secure and trusted data-at-rest protection,” said BJ Heggli, general manager for Microsemi’s memory and storage business. “We introduced this latest 64GB SSD in our BGA package to expressly meet the data security and extreme reliability requirements of a growing number of embedded applications. And because Microsemi owns the processor Armor III technology, customers are also assured of critical long-term availability.”

“Our latest 64GB SSD in the rugged BGA package continues to demonstrate Microsemi’s commitment to designing and delivering the world’s leading rugged and secure storage solutions,” said Charlie Leader, Microsemi vice president and executive manager. “In addition, this latest SSD is designed and assembled in the United States in Microsemi’s trusted facility, providing an extra level of confidence for our customers.”

CEA-Leti today announced the launch of its Silicon Impulse IC design competence center, a comprehensive IC technology platform offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles.

Silicon Impulse provides immediate access to Leti’s and CEA-List’s advanced IC technologies and systems expertise. It also leverages Leti’s extensive experience in technology transfer. Collaboration between Leti and List experts and ecosystem partners aims to shorten time to market from idea to production. This process includes prototyping and pre-production runs utilizing Leti’s advanced industrial infrastructure from concept to production hand-off.

Silicon Impulse offers its partners the full range of Leti and List’s expertise in analog, RF, digital and memory design and hardware/software-integrated solutions at the technology node that most cost-effectively meets their needs. The IC competence center combines Leti’s large portfolio of leading-edge technologies and novel low-power design solutions with a unique service for speeding integration of Fully Depleted Silicon-on-Insulator (FD-SOI) and many other more advanced technologies (ReRAM, MEMS, 3DVLSI, Silicon Photonics), enabling heterogeneous low-power co-integration. These services are targeted to enable the rapidly emerging third-generation information-acquisition and processing devices that are key to the Internet of Things (IoT).

“Pervasive wireless networking and groundbreaking low-power technologies are critical to the widespread adoption of the Internet of Things, because they improve the performance of portable devices and their network infrastructure,” said Leti CEO Marie–Noëlle Semeria. “With Silicon Impulse’s one-stop-shop platform, 28nm FD-SOI heterogeneous, low-power design becomes a reality for the IoT community. Silicon Impulse helps Leti’s partners introduce innovative products that deliver optimal performance for these applications, and benefit from the most advanced technologies.”

Silicon Impulse, in cooperation with a rich network of ecosystem partners, is set up to develop, produce and integrate innovative customized or standard systems that exploit advanced technologies for all of Leti’s industrial partners.

Specific features of the offer include:

  • Leti’s pool of expertise in advanced IC design and low-power technologies
  • Leading-edge IC technologies for application-oriented device, circuit and system solutions
  • Regularly scheduled MPW shuttles for silicon prototyping and small-volume runs
  • An established high-tech supply chain to accelerate production ramp-up and hand-off
  • Customized collaboration to fit partner needs

Leti’s experts will collaborate with partners from the feasibility-study stage through device design, prototyping, testing and production ramp up. The wide range of IC technologies available in the platform is further augmented by List’s comprehensive embedded software solutions.

Leti will showcase its new Silicon Impulse platform at major industry events this year: DATE, Silicon Impulse workshop during VLSI-DAT, DAC, LetiDays Grenoble, LetiDay San Francisco during SEMICON West, LetiDay Tokyo, Leti’s Devices Workshop at IEDM and SOI consortium events.

IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEMS, and involves wafer-level processing on dedicated runs.

The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

Engineers at The University of Texas at Dallas have created semiconductor technology that could make night vision and thermal imaging affordable for everyday use.

Researchers in the Texas Analog Center of Excellence (TxACE) in the University’s Erik Jonsson School of Engineering and Computer Science created an electronic device in affordable technology that detects electromagnetic waves to create images at nearly 10 terahertz, which is the highest frequency for electronic devices. The device could make night vision and heat-based imaging affordable.

Presently, night vision and thermal imagers are costly, in part because they are made with specialty semiconductor devices or need isolation from the environment.

The UT Dallas device is created using Schottky diodes in Complementary Metal-Oxide Semiconductor (CMOS) technology. CMOS is used to make affordable consumer electronic devices such as personal computers, game consoles and high-definition TVs. In addition to being affordable, these devices could be more easily incorporated into smartphones.

“There are no existing electronic detection systems operating in CMOS that can reach above 5 terahertz,” said Zeshan Ahmad, lead author of the work, electrical engineering doctoral candidate and a research assistant in TxACE. “We designed our chip in such a way that it can be mass produced inexpensively, has a smaller pixel and operates at higher frequencies.”

Dr. Kenneth O, professor of electrical engineering in the Jonsson School and director of TxACE, noted the time it took for the field to reach this frequency in CMOS.

“This is a truly remarkable accomplishment,” said Dr. O, holder of the Texas Instruments Distinguished Chair.

“Twenty years ago, we were struggling to build CMOS circuits operating at 1 gigahertz. Now we are building circuits working at frequencies that are 10,000 times higher.”

The device could eventually be used for imaging animals near a road while driving at night; imaging intruders in darkness; providing light for night hiking; and estimating how many people are in a room to better control heating, air conditioning and light. It also could be used for other tasks such as finding pipes covered by concrete or walls.

“This technology could provide a very superior means to use the infrared portion of the spectrum,” said Dr. Robert Doering, research strategy manager at Texas Instruments.” Electronic control of generating infrared directly from CMOS integrated circuits will enable a wide variety of important new applications.”

The next step in the research is to realize CMOS devices that can reach even higher frequencies, up to 40 terahertz

This week, at the 2015 International Solid State Circuits Conference (ISSCC), nanoelectronics research center imec, in collaboration with Tyndall National Institute, the University of Leuven (KULeuven) and the Ghent University, demonstrated a 4x20Gb/s wavelength division multiplexing (WDM) hybrid CMOS silicon photonics transceiver, paving the way to cost-effective, high-density single-mode optical fiber links.

Hybrid CMOS silicon photonics transceivers, transmitting and receiving data over single-mode optical fiber, are expected to play a key role in next-generation datacenter connectivity. By leveraging existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Combined with wavelength division multiplexing capability, highly scalable single-mode optical transceivers can be constructed, satisfying the growing need for interconnect bandwidth in next-generation cloud infrastructure.

Imec’s CMOS silicon photonics transceiver comprises a silicon photonics (SiPh) chip, flip-chip integrated with a low-power 40nm CMOS chip. The SiPh chip, fabricated on imec’s 25Gb/s Silicon Photonics Platform (iSiPP25G), comprises an array of four compact 25Gb/s ring modulators, coupled to a common bus waveguide to allow WDM transmission. On the receive side, a ring-based, low-loss (2dB) demultiplexing filter with 300GHz channel spacing is implemented and further connected to an array of four 25Gb/s Ge waveguide photodetectors. Both the ring modulators and the ring WDM filters include highly efficient integrated heating elements to tune their resonant wavelengths to the desired WDM channels. The CMOS chip includes four differential 20Gb/s ring modulator drivers and four 20Gb/s trans-impedance amplifiers. A 12 channel single-mode fiber array is packaged onto the grating coupler array on the chip, using a planar approach developed at Tyndall National Institute.

Error-free operation was demonstrated in a 20Gb/s loop-back experiment for all four WDM channels as well as with two channels running together. The dynamic power consumption of the transceiver, including the CMOS driver and receiver, was less than 2pJ/bit. Thermal tuning of the WDM channel wavelengths consumed only 7mW/nm per channel. The transceiver can be further scaled to higher bandwidth capacity by adopting more advanced CMOS technology and by adding more WDM channels, enabling optical modules for 100GbE, 400GbE and beyond for future datacenter interconnects.

imec transceiver

 

This work was supported by imec’s optical I/O core partner program. Imec’s iSiPP25G technology can be accessed through Europractice, while Si Photonics packaging services are available through Tyndall National Institute (Ireland).

At the SPIE Advanced Lithography conference in San Jose, Calif., Applied Materials, Inc., today announced the industry’s first in-line 3D CD SEM metrology tool for solving the challenges of measuring the high aspect ratio and complex features of 3D NAND and FinFET devices. The new Applied VeritySEM 5i system offers state-of-the-art high-resolution imaging and backscattered electron (BSE) technology that enable exceptional CD control in-line. Using the VeritySEM 5i system can speed up chipmakers’ process development and production ramp, and improve device performance and yield in high-volume production.

“Complex 3D structures require new measurement dimensions, increasing the demands placed on metrology technologies,” said Itai Rosenfeld, corporate vice president and general manager of Applied’s Process Diagnostics and Control group. “Continuing to rely on traditional CD SEM techniques to measure 3D devices is virtually impossible. Offering imaging innovations based on Applied’s expertise in advanced e-beam technology and image processing for fast, accurate on-device CD SEM metrology, allows our customers to see, measure and control their 3D device during R&D, ramp and volume production. Multiple customers using the tool are already benefiting from better yields with these new 3D devices. This system should continue to set the benchmark for the industry as chipmakers require new precision materials engineering capabilities to transition to 3D architectures and scale beyond the 10nm node.”

Innovations in metrology precision are needed to improve device performance, reduce variability and boost yields of increasingly intricate high-performance, high-density 3D devices. An advanced high-resolution SEM column, tilted beam and BSE imaging give the VeritySEM 5i system its unique 3D metrology capability to measure and monitor the most vital and challenging FinFET and 3D NAND structures in-line. Specifically, BSE imaging for via-in-trench bottom CD enables chipmakers to ensure connectivity between underlying and overlaying metal layers. For controlling FinFET sidewall, as well as gate and fin height, where the smallest variation impacts device performance and yield, the VeritySEM 5i tool’s tilt-beam provides exact, repeatable in-line measurements. High-resolution BSE imaging enables continued vertical scaling through enhanced sensitivity for measuring the asymmetrical sidewall and bottom CDs of 3D NAND devices with very high aspect ratios reaching up to 60:1 and beyond.

Applied Materials, Inc. (Nasdaq:AMAT) is the global leader in precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries. Our technologies help make innovations like smartphones, flat screen TVs and solar panels more affordable and accessible to consumers and businesses around the world. Learn more at www.appliedmaterials.com.

Cymer, an ASML company, a developer of lithography light sources used by chipmakers to pattern advanced semiconductor chips, today announced the shipment of its first XLR 700ix light source. Enabling higher scanner throughput and process stability for 14nm chip manufacturing and beyond, the XLR 700ix provides improvements in bandwidth, wavelength and energy stability to reduce process variability and increase yield through improvements in wafer critical dimension (CD) uniformity; software enhancements to increase light source predictability and availability; and reduction in helium and power consumption to decrease operating costs.

Cymer also introduced DynaPulse as a product upgrade option for OnPulse customers. DynaPulse enables chipmakers to extend their capital investment and achieve the same performance improvements standard in the XLR 700ix to their ArF immersion installed base. Essentially eliminating bandwidth as a source of variation to improve on-wafer critical dimension (CD) uniformity, the XLR 700ix and DynaPulse utilize the same patented technology to tightly control bandwidth specifications (300+5fm) and achieve stable on-wafer performance.

“Customers have recognized the new performance, process stability and sustainability improvements of the XLR 700ix to enable higher system efficiency for leading-edge manufacturing applications, and are eager to realize the same benefits within their installed base,” said Ed Brown, Chief Executive Officer of Cymer Light Source. “DynaPulse now makes it easier for chipmakers to achieve a high level of performance and productivity across their entire ArF immersion light source fleet.”

From enhanced service to product upgrade options, such as SmartPulse and DynaPulse, OnPulse customers experience reduced cost of operation, enhanced productivity and predictable costs that scale directly with wafer production. For example, the SmartPulse data capture and analysis tool enables chipmakers to better monitor key light source parameters in real-time, with field-to-field resolution, prevent excursions and make adjustments to achieve a high level of performance, and ultimately increase wafer output per tool. SmartPulse enables chipmakers to better monitor and keep light sources within tighter bandwidth control achieved with DynaPulse.

As the newest additions to the family, XLR 700ix and DynaPulse demonstrate Cymer’s continued investment in research and development to support DUV technology extensions for 14nm chip manufacturing and beyond.

Thermal performance of 3DICs


February 20, 2015

By PHIL GARROU, Contributing Editor

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.
An increase in power density may come from higher power dissipation and/or from a reduction of the
chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissi- pation when compared to single-die implementations.

At the 2014 IEEE 3DIC Conference recently in Cork, Ireland, Leti and ST Micro presented two papers on the thermal performance of Packaging 3DICs. Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to poor thermally conductive layers such as BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin SiO2 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2 dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.