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ON Semiconductor has successfully characterized and demonstrated its first fully-functional stacked CMOS imaging sensor featuring a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs. The technology has been successfully implemented and characterized on a test chip with 1.1-micron (µm) pixels and will be introduced in a product later this year.

Conventional sensor designs in a monolithic substrate process require separate die area to support both the pixel array and supporting circuitry. With 3D stacking technology, the pixel array and the supporting circuitry are manufactured on separate substrates and then stacked with connections between the two made with through silicon vias (TSVs). This allows the pixel array to overlay the underlying circuitry and result in a more efficient die floorplan. With this approach, design engineers can optimize each part of the sensor for imaging performance, cost, power and die size. With the optimization of the pixel array, sensors can have improved pixel performance with lower noise levels and enhanced pixel response. The underlying circuitry can use more aggressive design rules to lower power consumption as well. The smaller overall footprint supports today’s advanced camera modules that integrate Optical Image Stabilization (OIS) and additional data storage in the same module footprint.

“3D stacking technology is an exciting breakthrough that enhances our ability to optimize ON Semiconductor’s future sensors,” said Sandor Barna, vice president of Technology for ON Semiconductor’s Image Sensor Group. “This technology provides manufacturing and design flexibility to ensure continued performance leadership across our entire sensor product portfolio.”

ON Semiconductor will be demonstrating its latest image sensor technology and products at CES 2015 in Las Vegas from Jan. 6-8.

Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

By TESHIMA, LatticeGear, Beaverton, OR and JAMIL J. CLARKE, Hitachi High Technologies America, Inc., Clarksburg, MD 

In order to develop and manufacture new materials and processes, the cross section is essential (FIGURE 1). Cross sections allow one to visualize, measure, and characterize the chemistry of the film stack or device structures. This allows engineers to verify the integrity of devices and to make critical decisions about the process. To be able to provide this data, manufacturers and equipment suppliers invest close to a billion dollars annually [1] to purchase equipment for off-line use and out- of-fab support labs.

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

Because such labs are not considered a “make wafer” function, lab managers are under constant pressure to reduce costs, both per sample and for lab operations. This paper demonstrates cross section sample preparation using a workflow that combines High Accuracy Cleaving (HAC) and Broad Ion Beam (BIB) milling. Coupling these techniques, which are relatively low in cost when compared to Focused Ion Beam (FIB) or automated polishing or cleaving [2], reduces sample preparation time, complexity, and cost without sacrificing cross-section quality. The LatticeAxTM HAC and the Hitachi IM4000 BIB milling tools were used to demonstrate this process and are also described.

Preparing cross sections for SEM analysis

Characterization of semiconductor structures and material properties commonly begins with sample preparation. Semiconductor samples are inspected either as a cross section or “top down.” Cross-section samples are needed to inspect layers of subsurface features. As shown in FIGURE 2, if a cross-section view is required and the original sample is a wafer or a die, cleaving is typically the first step in the sample preparation procedure.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

In many cases, the sample can proceed directly to the Scanning Electron Microscope (SEM) as shown in the Single-Tool workflow. For fully processed devices and those with large metal structures, improving surface quality with another method enhances the results (see Multi-Tool workflow).

Advanced techniques used in the multi-tool workflow, such as FIB and automated polishing, have benefits in terms of submicron—or in the case of FIB, nanometer—targeting accuracy, but the tradeoff is high cost, long cycle time, and the need for skilled operators.

Methods

The following sections describe the techniques used to perform multi-tool, cross-section sample prepa- ration workflow using HAC and BIB milling.

High Accuracy Cleaving An accurate and high quality cleave is critical to preparing a cross section for SEM imaging regardless of whether it follows the single- or multi-tool workflow. Manual cleaving, in which you scribe a line and then break the sample along the fracture over a raised edge or pin, has inherent problems with accuracy and repeatability. In addition, because the user handles the sample with fingers that are often gloved, great skill is required to achieve good results. FIGURE 3a shows traditional scribing hand tools used in manual cleaving. Cleaving results using these tools are obviously dependent on the hand-eye coordination of the operator.

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

Figure 3b

Figure 3b

The LatticeAx process overcomes these disadvantages by controlling the indent location and depth, as well as the cleaving operation, with fine-positioning knobs on the LatticeAx high magnification digital microscope. This new machine-assisted Indent and Cleave[3] approach bridges both manual scribing and fully automated cleaving or polishing, and increases success rates while keeping costs down.

The accurate, repeatable indent and slow, controlled cleaving that results from this hybrid tool (FIGURE 3b) speeds preparation time and produces high accuracy, quality results—regardless of user experience—and with greater flexibility of sample size and dimensions.

Broad Ion Beam Milling The BIB milling system is a specimen preparation device (FIGURE 3c) for SEM and surface analysis (EDX[4], EBSP[5], etc.). The device uses a defocused beam of argon ions that sputter material from the target specimen at a rate up to 2-500μm/hour, depending on the mode used. The BIB milling system uses a simple, repeatable process to remove surface layers of a specimen and for final finish of specimens in cross section. It is advantageous compared to mechanical polishing methods, which require well-trained operators to polish the specimen to a flat and mirror-like surface and hit a specific target. In addition, complex material composites that contain materials varying in hardness pose challenges when mechanically prepared using polishing wheels and compounds. This mechanical approach can lead to cracks, stress, relief (pull-out effects), and smearing. These adverse effects are minimized when using the low voltage (0-6kV) argon beam to remove material.

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

Flat Milling Mode Using the BIB’s “Flat Milling” mode yields a high quality cross section in a short amount of time. It requires the initial high accuracy cleave to be through or within a few 100nms of the area of interest and the face of the cross section to be at 90 degrees to the sample surface. With a high quality cleave, the BIB’s Flat Milling mode quickly polishes the cross-section face. Material is removed at a rate of 2μm/hr. Using the flat milling holder, the milling process can uniformly sputter an area approximately ~5mm across around the center of rotation of the specimen (FIGURE 3d). Typical operating parameters for the Hitachi IM4000Plus are 3kV accelerating voltage and a tilt of 70 degrees, with sample stage oscillation set to ±90 degrees and 10rpm. The best quality surface is achieved with a minimum mill time, thus the importance of cleaving through, or very close to, the region of interest. Otherwise, variations in the milling rates of different materials produce artifacts, often called “curtaining.”

Figure 3d

Figure 3d

Cross-section Mode When more than a few microns of material need to be removed, the BIB system is operated in “Cross-section” mode. This is commonly used when exposing a sub-surface target structure. Mechanical grinding causes mechanical artifacts and deformation from stress, making it difficult to obtain a smooth surface for SEM analysis. When using the cross-section milling holder, the BIB IM4000Plus shields part of the argon ion beam with the mask arranged on the specimen, and produces a cross section along the trailing edge of the mask into the sample. For Cross-section mode, targeting accuracy is approximately +/- 15μm.

Backside Milling Backside (as opposed to topside) milling mode can be used in both flat milling and cross-section modes. Backside milling is effective and necessary to alleviate curtaining effects[6] that can occur when traditional top-down ion milling induces striations. These striations are caused by the milling differential from neigh- boring materials that are atomically denser than the surrounding area. FIGURE 4 shows the direction of the ion beam during backside milling and the trench milled by the ion beam.

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

Case Study 1. Quick 5-minute HAC and Flat Milling for Cross Section Final Polish

In this example, a cross section was prepared of an Intel microprocessor removed from its package. The size of the sample available after deprocessing was 8 x 8mm. To prepare the cross section, the sample was cleaved parallel to 15μm contacts visible on the sample surface. The Hitachi IM4000 was then used to prepare the final surface using flat milling mode. Approximately 100nm of material was removed in 10 minutes to achieve the polished surface of the final cross section.

The cross-section process included:

1. Indenting the 15μm area of interest (AOI) with the LatticeAx (FIGURE 5a) (3 min)
2. Cleaving through the AOI using the small sample cleaving accessory[7] (2 min) (FIG 5b-c)
3. Mounting the sample for the IM4000Plus and backside milling using flat milling mode (15 min)

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5b. View of sample after cleaving with the small sample cleaver

FIGURE 5b. View of sample after cleaving with the small sample cleaver

 

FIGURE 5c. Optical view of the cross section after cleaving

FIGURE 5c. Optical view of the cross section after cleaving

Results

This demonstrates a rapid (15-minute) method to obtain a damage-free cross section from a fully processed microprocessor over a very large area (5mm in diameter). A comparison of the results before and after milling shows the clear improvement in surface quality and SEM imaging results (FIGURE 5d and e). Using other methods such as mechanical polishing or FIB can take several hours to achieve a comparable size produced by the large flat-milled region. The best results were obtained when removing a minimum of material (nms), demonstrating the importance of an accurate, high quality cleave prior to BIB milling. FIGURE 5f shows a high-magnification view of the resulting cross section after flat milling that is high quality and without curtaining.

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

 

FIGURE 5f. SEM image showing planar cross section after flat milling

FIGURE 5f. SEM image showing planar cross section after flat milling

Case Study 2. Using HAC and BIB Milling in Cross-section Mode to Prepare Cross Sections of Solder Bumps

Cross sections are required to inspect solder bump reliability for interconnect problems during development and production, or for electromigration failure after aging. Creating these cross sections in a targeted location is critical for effective fault isolation and SEM analysis. With the advent of large Through Silicon-Via (TSV) and solder bump structures—often 100μm in depth or width—high throughput methods are necessary to make cross sections efficiently and effectively.[8]

In this case study, the solder bumps were prepared for SEM in a two-step process. In step 1, the LatticeAx cleaver was used to cleanly cross-section close to, and parallel to, a specific row of copper bumps. The copper bumps had a diameter of 85μm and were cleaved 30 μm from the center of a bump. Time to cleave was 5 minutes and yielded the results shown in FIGURE 6a and FIGURE 6b.

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

In step 2, a broad argon ion beam instrument, the Hitachi IM4000, was used to prepare the final imaging surface within the copper bump. The backside milling method was used; no further preparation was performed.

Results

FIGURES 6c and 6d, taken after ion milling, plainly show the improved surface quality and copper grain structures, as well as fine details at the interface between the bump and adjacent structures. By cleaving close to the center of the copper bumps, the milling time on the BIB was reduced to less than 2 hours versus tens of hours for large cross-section areas (multiple bumps).

This two-step sample preparation process described has been implemented in production by a large semiconductor manufacturer. The technique described reduces turn-around time and repeatedly results in artifact-free cross sections of copper solder bumps.

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

Conclusion

For “off-line” laboratories, using HAC and BIB together for creating high quality cross sections is a compelling, low-cost alternative to investments in FIBs or automated polishing or cleaving equipment. High accuracy cleaving reduces sample preparation time, complexity, and cost without sacrificing cross- section quality. Combining this with a broad argon ion beam instrument for quick removal of minimal amounts of material or for milling of large flat areas, HAC presents effective, accurate results critical to product or failure analysis, while keeping both equipment and per-sample costs low.

Whether for final polish or in sample preparation of solder bumps, the results from the machine-assisted high accuracy Indent and Cleave approach combined with broad ion beam milling rival those of fully automated cleaving or polishing systems

References

1. Per industry sources
2. Approximate costs: FIB/SEM at $1-2 million; Automated HAC at $300,000; HAC+BIB milling tool at $160,000.
3. Cleaving Breakthrough: A New Method Removes Old Limitations, E. Moyal, E. Brandstädt, EDFAAO (2014) 3:26-31
4. Energy-dispersive X-ray spectroscopy
5. Electron backscatter pattern
6. CAVolkert and AM Minor, MRS Bull 32(5) (2007) 389–99.
7. The small sample cleaving accessory is used to clamp samples as small as 4mm wide for indenting with the LatticeAx and cleaving using a separate cleaving base. 8. Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology, Microscopy Today, September 2013, Teshima et al., 56-59.

J. TESHIMA is with LatticeGear, LLC., 1500 NW Bethany Blvd., Suite 200, Beaverton, OR 97006, USA. JAMIL J. CLARKE is with Hitachi High Technologies America, Inc., Nanotechnology Systems Division, 22610 Gateway Center, Dr. Clarksburg, MD 20871, USA

LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices. 

By YUN WANG, Ph.D., Ultratech, San Jose, CA

Sub-20nm system-on-chip and FinFET devices have specific manufacturing challenges that can be resolved with laser spike annealing (LSA) technology. Over the last decade, new process technologies and materials have emerged, such as strained silicon, high-k/metal gate (HKMG) and advanced silicide. Meanwhile transistor structures have evolved significantly, from bulk planar and PDSOI to 3D FinFET. With dimensions approaching atomic scales, the need for low thermal budget processes offered by millisecond annealing (MSA) becomes more important to precisely control the impurity profiles and engineer interfaces. This article will explain how LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

LSA and MSA

The European semiconductor equipment market is expected to grow along with the world market. Global capital spending on semiconductor equipment is projected to grow 21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

In this article the terms LSA and MSA are used interchangeably. MSA can be implemented either by a scanning laser or a bank of flash lamps (FIGURE 1). In both cases, a reduced volume of substrate is heated to high temperature by a powerful light source, which results in fast temperature ramping compared to conventional RTP. Surface cooling in the millisecond time scale is dominated by conductive heat dissipation through the lower temperature substrate, which is several orders of magnitude faster than radiation heat loss or convection cooling through surfaces. The wafer backside is typically heated by a hot chuck or lamps to reduce the front surface peak temperature jump, and in some cases, to reduce the flash lamp power requirement or facilitate laser light absorption. Flash usually requires higher backside heating temperature than the laser option.

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

There are important differences between flash and laser approaches. The flash system provides global heating where the top surface of the entire wafer is heated at the same time. Hence heat dissipation occurs only in one dimension (1D – vertical direction). In addition, the backside needs to be floated to relieve the stress caused by global wafer bending due to the vertical thermal gradient. The laser system, on the other hand, provides localized heating around the scanning beam. The heat dissipation is between two-dimensional (2D) and three-dimensional (3D) (2D for an infinitely long line beam, and 3D for a point source). Since the thermal stress is localized, the backside can be chucked to facilitate heat sinking.

The difference in heat dissipation has a significant impact on the cooling rate, in particular, when long annealing or high intermediate (preheat) temperature is used. FIGURE 2 compares the temperature (T) profiles between laser and flash systems for the same peak surface temperature (Tpk) and dwell time (tdwell— defined as the full-width-half-maximum duration when a fixed point on the wafer sees the laser beam or flash pulse). The latter shows much slower ramp down. This is because once the flash energy is dissipated through the wafer thickness, the cooling is limited by the same radiation loss mechanism as in RTP. For applications relying on non-equilibrium dopant activation, the extra thermal budget due to the slow ramp down could be a concern for deactivation.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

LSA technology uses a long wavelength p-polarized CO2 laser with Brewster angle incidence. Previous studies have shown that such configuration has benefits of reduced pattern density effect compared to short wavelength with near normal incidence. A second beam can be added to form a dual beam system that allows more flexibility to adjust the temperature profiles, and expands the process capability to low T and long dwell time.

FIGURE 3 shows different LSA annealing temperature-time (T-t) regimes that can be used to meet various application needs. Standard LSA used in front-end applications has Tpk ranging from 1050~1350°C and tdwell from 0.2~2ms. Short dwell time is beneficial for reducing wafer warpage and litho misalignment, especially for devices with high strain. Long dwell time (2~40ms) adds more thermal budget for defect curing. It can also be used to improve activation and fine tune the junction depth. The low T regime enables applications that require lower substrate and peak annealing temperatures, such as annealing of advanced silicide or new channel/gate stack materials that have poor thermal stability.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

High-k/metal gate (HKMG)

The impact of MSA on HKMG is thinner equivalent oxide thickness (EOT) due to reduced interfacial layer growth from a lower thermal budget. Lower leakage and better surface morphology are also observed in hafnium-based, high-k films when annealed by a laser.

Incorporating nitrogen into a high-k dielectric film can improve thermal stability, reliability, and EOT scaling. Post nitridation anneal with MSA provides opportunities to stabilize the film with a more precisely controlled nitrogen profile, which is important since excessive nitrogen diffusion can increase interface trap and leakage. Oxygen has a strong impact on the characteristics of HKMG and it is important to control the ambient environment during the gate annealing. Full ambient control capability has been developed for LSA to accommodate this need. FIGURE 4 shows the schematics of our patented micro-chamber approach that allows ambient control to be implemented in a scanning system using non-contact gas bearing. Different process gas can be introduced to accommodate various annealing and material engineering needs.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

Advanced silicide

Conventional NiSi processing involves two RTA steps. The 1st RTA (200~300°C) forms Ni-rich silicide, and the 2nd RTA (400~500°C) after selective etch of un-reacted Ni forms the desired low resistance NiSi phase. By replacing the 2nd RTA with a high temperature MSA (700~900°C), it can reduce leakage as well as improve performance. The improvement in leakage distribution results from the statistical reduction of Ni pipe defects due to the low thermal budget of MSA.

High temperature promotes phase mixing of Si-rich Ni silicide at the silicide/Si interface and lowers Schottky barrier height (SBH). In conventional RTA, this requires T > 750°C; such high T would lead to morphology degradation, excess diffusion, and higher resistivity. With MSA, because of the short duration, agglomeration does not occur until ~900°C.

To maximize the performance gain, anneal at high T close to the agglomeration threshold is desired. In such a case, minimizing within-die pattern effects and implementing within-wafer and wafer to-wafer temperature control becomes very important.

FinFETs

As FinFETs shrink, interface contact resistance, Rc, becomes more critical (FIGURE 5). A promising path to lower Rc is interface engineering by dopant segregation using pre or post silicide implantation.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

 

Thermal annealing is necessary to repair implant damage and activate dopants in pre silicide implantation scheme, and to drive-in dopants in post silicide case. Using MSA instead of RTA results in more precise dopant profile control, higher dopant concentration at the interface and less potential silicide defectivity, due to the lower thermal budget.

Recently, Ti re-emerged as an option for contact metal because of better thermal stability and potential lower SBH. LSA can be applied to form low Rc Ti/Si contact. In advanced FinFET flow where contacts are formed after source/drain activation and gate stack, low thermal budget process is beneficial to minimize dopant deactivation and unintentional gate work function shift.

In-situ doped selective epitaxial growth is increasingly used to form the raised source/drain for FinFET. There is, however, a limitation in the maximum activation level it can achieve. Activation can be improved using MSA in combination with additional implantation. Drastic FinFET performance improvement has been achieved with co-optimization of conformal doping, selective epitaxial growth, implantation and MSA. In addition to front-end and middle-of-line applications, there are also opportunities at the back-end. One example is low-k curing. For FinFET, low-k is important not only as an inter-Cu dielectric, but also as a transistor-level dielectric to minimize the parasitic capacitance arising from 3D topography. The modulus and hardness of the low-k films can be improved without adversely impacting the k value using MSA.

New channel materials

Below the 10nm technology node, new materials with enhanced transportation, such as SiGe/Ge and III-V compounds, may be needed to meet the performance requirements. These materials have low thermal stability and are lattice mis-matched with the Si substrate, as a result physical integrity during thermal annealing is a very big concern. Low thermal budget processing by MSA provides a way to alleviate this issue. For example, studies on SiGe/Si heterostructures have shown that MSA can enable a higher annealing temperature than RTA, without strain relaxation or structural degradation. This results in improved activation. With MSA, junctions with enhanced activation and reduced diffusion can be obtained.

Summary

We have reviewed various applications of millisecond annealing for advanced device fabrication. As new materials emerge and device dimensions approach the atomic scale, precise thermal budget control becomes critical. This opens new opportunities for short time scale annealing. In addition to the traditional dopant activation and impurity profile control, MSA can also be used for interface engineering and material property modifications (structural, electrical, chemical, and mechanical). In general, if a desired process has higher thermal activation energy than an undesired process, application of high temperature, short duration annealing is beneficial.

YUN WANG, Ph.D., is Senior Vice President and Chief Technologist of Laser Processing Ultratech, San Jose, CA.

CEA-Leti will present its latest results on CoolCube, the technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a Dec. 14 workshop in San Francisco, Calif. The workshop precedes IEDM 2014, Dec. 15-17.

“The technology is designed to allow a connection of the stacked active layers on a nanometric scale, with a very high density, due to their alignment by a standard lithographic process,” said Maud Vinet, Leti’s advanced CMOS laboratory manager, who will give the presentation. “This 3D concept should allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation ​​in classic 2D – gains comparable to those expected in the next generation.”

Under development for eight years, CoolCube aims at cutting in half the thermal budget in manufacturing transistors, while maintaining their performance. This low-temperature fabrication allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

During the continuation of the project over the next three years, Leti and its industrial partners will target development of a silicon component prototype of CoolCube.

In addition to the CoolCube overview, the workshop for invited guests will include summaries of:

  • Leti’s innovative route with industry
  • Emerging material for future market opportunities
  • Leti’s vision towards 10nm and below
  • Embedded NVM for the future
  • Going further with disruptive designs and architectures
  • Electronic medicine: a new market needing new medical methodologies

Leti also will present 17 papers, including four invited papers, at IEDM 2014.

Intel announces IoT platform


December 11, 2014

Intel Corporation today announced the Intel IoT Platform, an end-to-end reference model designed to unify and simplify connectivity and security for the Internet of Things (IoT). Intel also introduced integrated hardware and software products based on the new platform and new relationships with an expanded ecosystem of system integrators that promise to move IoT from infancy to mass deployment.

The new offerings and relationships will make it easier for solution providers to move IoT from pockets of pilots to mainstream deployments with a repeatable foundation of building blocks that can be customized for limitless solutions. Data will be unlocked faster to extract meaningful information and value for consumers and businesses.

For example, Rudin Management, a New York City real estate company who developed its own system software called DiBoss, has demonstrated that it can intelligently manage energy and other systems in its buildings. In one year, in one building, the company saved nearly $1 million to its bottom line, which would translate to a savings of 50 cents for every square foot of real estate it owns and manages.

“The power of IoT on our company’s business will have significant impact,” said John Gilbert, COO, Rudin Management. “We are a real estate company that used to dabble in technology, but now because of IoT, we are a technology company that dabbles in real estate.”

Horizontal Approach to IoT
The Intel IoT Platform helps deliver innovations to market faster, reducing solution complexity, and delivering actionable intelligence faster by offering a defined, repeatable foundation for how devices will connect and deliver trusted data to the cloud.

“With this platform we are continuing to expand our IoT product family beyond silicon with enhancements to our pre-integrated solutions that make IoT more accessible to solution providers,” said Doug Davis, vice president and general manager, Internet of Things Group, Intel. “IoT is a rapidly growing market but faces scalability hurdles. By simplifying the development process and making it easier to deploy new solutions that address market needs, we can help accelerate innovation.”

Expanding IoT Ecosystem
IoT has enormous potential to drive economic value and social change, but no company can do it alone. A robust ecosystem is needed to scale. To that end, Intel announced new solutions and relationships to boost the IoT ecosystem. Accenture, Booz Allen Hamilton, Capgemini, Dell, HCL, NTT DATA, SAP, Tata Consultancy Services Ltd., Wipro and others are joining together with Intel to develop and deploy solutions using their building blocks on the Intel IoT Platform. These solutions will help provide a repeatable foundation for IoT and free up developers’ time to focus on building solutions that expertly address specific customer pain points.

“Accenture is focused on helping clients realize the business value of the IoT as quickly and easily as possible,” said Mike Sutcliff, group chief executive, Accenture Digital. “Our combined capabilities can help us achieve that, and can also help clients get around some of the biggest roadblocks to IoT adoption by offering a simpler, faster way to roll out end to end IoT solutions than currently exists. Together, we can enable clients to define a clear value strategy for the IoT, and by using Accenture’s industry experience and digital assets to complement Intel’s IoT platform, we can create robust, end-to-end frameworks designed to overcome challenges associated with security, scalability and interoperability in IoT implementations.”

Integrated Hardware and Software
Intel is also delivering a roadmap of integrated hardware and software products to support the Intel IoT Platform. Spanning from edge devices out to the cloud, the roadmap includes API management and service creation software, edge-to-cloud connectivity and analytics, intelligent gateways, and a full line of scalable IA processors. Security is fundamental to the roadmap with both dedicated security products and security features embedded into hardware and software products.

Intel is evolving and optimizing this product roadmap to work seamlessly together with building blocks from the ecosystem to address the key challenges solution providers are facing when implementing IoT, including interoperability, security and connectivity.

The new products from Intel include:

  • Wind River Edge Management System provides cloud connectivity to facilitate device configuration, file transfers, data capture and rules-based data analysis and response. This pre-integrated technology stack enables customers to quickly build industry-specific IoT solutions and integrate disparate enterprise IT systems, utilizing API management. The cloud-based middleware runs from the embedded device up through the cloud to reduce time to market and total cost of ownership.
  • The latest Intel® IoT Gateway will integrate the Wind River Edge Management System via an available agent so gateways can be rapidly deployed, provisioned and managed throughout the life cycle of a system to reduce costs and time to market. In addition, the gateway includes performance improvements, support for lower cost memory options and a broader selection of available communication options. Intel IoT Gateways are currently available from seven ODMs with 13 more releasing systems in early 2015.
  • To get value out of the data generated in deployments using the Intel® IoT Platform, developers need a powerful yet easy-to-use approach to big data analytics. Intel is expanding its cloud analytics support for IoT Developer Kits to include the Intel® IoT Gateway series, in addition to Intel® Galileo boards and Intel® Edison Modules. Cloud analytics enables IoT application developers to detect trends and anomalies in time series at big data scale.
  • McAfee, a part of Intel Security, announced Enhanced Security for Intel IoT Gateways in support of the Intel IoT Platform. This pre-validated solution adds advanced security management for gateway devices.
  • Intel Security also announced that its Enhanced Privacy Identity (EPID) technology will be promoted to other silicon vendors. EPID has anonymity properties, in addition to hardware-enforced integrity, and is included in ISO and TCG standards. The EPID technology provides an on-ramp for other devices to securely connect to the Intel IoT Platform.
  • The Intel API and Traffic Management solution utilizes Intel Mashery solutions to enable creation of building blocks that make it easy to build new software applications. Customers of the Intel IoT Platform today have access to the Intel Mashery API management tools to create data APIs that can be shared internally, externally with partners or monetized as revenue-generating data services for customers.
INTEL_01_scalingiot-01

Intel is working to create a robust, scalable IoT ecosystem.

Soitec and CEA-Leti, along with the Fraunhofer Institute for Solar Energy Systems ISE, announced a new world record for the direct conversion of sunlight into electricity has been established. The record multi-junction solar cell converts 46 % of the solar light into electrical energy. Multi-junction cells are used in concentrator photovoltaic (CPV) systems to produce low-cost electricity in photovoltaic power plants, in regions with a large amount of direct solar radiation. The achievement of a new world record one year after the one previously announced in September 2013 by these French and German partners shows the strong competitiveness of the European photovoltaic research and industry.

Multi-junction solar cells are based on a selection of III-V compound semiconductor materials. The world record cell is a four-junction cell, and each of its sub-cells converts precisely one quarter of the incoming photons in the wavelength range between 300 and 1750 nm into electricity. When applied in concentrator PV, a very small cell is used with a Fresnel lens, which concentrates the sunlight onto the cell. The new record 46.0% efficiency was measured at a concentration of 508 suns and has been confirmed by the Japanese AIST (National Institute of Advanced Industrial Science and Technology), one of the leading centers for independent verification of solar cell performance results under standard-testing conditions.

A special challenge that had to be met by this cell is the exact distribution of the photons among the four sub-cells. This has been achieved by precise tuning of the composition and thicknesses of each layer inside the cell structure. “This is a major milestone for our French-German collaboration. We are extremely pleased to hear that our result of 46% efficiency has now been independently confirmed by AIST in Japan”, explains Dr. Frank Dimroth, project manager for the cell development at the German Fraunhofer Institute for Solar Energy Systems ISE. “CPV is the most efficient solar technology today and suitable for all countries with high direct normal irradiance.”

Jocelyne Wasselin, Vice President Solar Cell Product Development for Soitec, a company headquartered in France and a world leader in high performance semiconductor materials, said: “We are very proud of this new world record. It confirms we made the right technology choice when we decided to develop this four-junction solar cell, and clearly indicates that we can demonstrate a 50% efficiency in the near future”.

She added: “To produce this new generation of solar cells, we have already installed a line in France. It uses our bonding and layer-transfer technologies and already employs more than 25 engineers and technicians. I have no doubt that this successful cooperation with our French and German partners will drive further increase of CPV technology efficiency and competitiveness.”

New record solar cell on a 100 mm wafer yielding approximately 500 concentrator solar cell devices. ©Fraunhofer ISE/Photo Alexander Wekkeli

New record solar cell on a 100 mm wafer yielding approximately 500 concentrator solar cell devices. ©Fraunhofer ISE/Photo Alexander Wekkeli

The Hybrid Memory Cube Consortium (HMCC), dedicated to the development and establishment of an industry-standard interface specification for Hybrid Memory Cube (HMC) technology, announced the finalization and public availability of its HMCC 2.0 specification (HMCC 2.0).

The new HMCC 2.0 specification advances data rate speeds from 15 Gb/s up to 30 Gb/s, establishing a new threshold for memory performance. HMCC 2.0 also migrates the associated channel model from short reach (SR) to very short reach (VSR) to align with existing industry nomenclature.

“With 150 members, the Hybrid Memory Cube Consortium has gained considerable momentum since its inception and, as a result, has more and better inputs on how the interface can best fit tomorrow’s applications,” said Jim Handy, director, Objective Analysis. “The release of the HMCC 2.0 specification shows a commitment to evolving a family of specifications targeting all high-performance computing applications.”

The HMCC was founded in October 2011 by co-developers Altera, Micron, Open-Silicon, Samsung Electronics and Xilinx. The HMCC finalized and released its first specification in May 2013, demonstrating consensus among leading semiconductor developers to drive adoption of HMC into next-generation systems. Since its establishment, the HMCC has grown to include more than 150 OEMs, enablers and integrators who regularly participate in the development and discussion of HMC standards. Finalization of the second generation of HMCC specifications is a key milestone in the development of this innovative memory technology and an indication of its continued adoption.

“HMCC 2.0 gives designers a mature solution for breaking through memory bottlenecks and delivering a new generation of systems with unprecedented memory performance,” said Hans Boumeester, Open-Silicon’s vice president of IP and engineering operations. “Ratification of the new standard means that these designers will have access to standards-compliant IP for immediate integration into chips and systems that meet the growing bandwidth demands of next-generation data center and high-performance computing applications.”

Applied Materials, Inc. today announced it collaborated with Samsung Electronics Co., Ltd. and PSK Inc., a Korea-based leader in photoresist removal, to develop an advanced patterning solution for the manufacture of future generations of NAND and DRAM device designs. The new solution, available now, consists of the unique Saphira(TM) APF hardmask deposited on the Applied Producer® XP Precision CVD* system, and the Saphira removal process supported on the PSK OMNIS Asher tool. This comprehensive solution represents a breakthrough in precision materials engineering for complex patterning applications.

“This collaboration allows us to demonstrate and enhance the Saphira film’s deposition qualities and removal process,” said Dr. Mukund Srinivasan, vice president and general manager of the Dielectric Systems and Modules Group at Applied Materials. “A new superior class of hardmask films, such as the Saphira APF, is needed as the extendibility of traditional films to support high aspect ratio patterning is a major barrier to NAND and DRAM scaling. Teaming with industry experts on this new hardmask solution gives Applied a strong advantage to set the pace for advanced memory manufacturing.”

“We are very pleased to work with Applied Materials on developing a highly productive, enabling technology that helps solve tomorrow’s patterning challenges,” said JJ Lee, SVP and chief marketing officer of PSK. “With the unprecedented complexities in patterning future device designs, we believe it is through cooperative efforts that the industry can achieve novel solutions to meet customer requirements. The combination of systems from Applied and PSK provide the industry with an efficient, readily integrated, comprehensive solution.”

The Saphira APF deposition and PSK OMNIS Asher systems resolve major issues to improve patterning of more complex device structures at advanced technology nodes. For emerging high aspect ratio and dense patterning requirements, the Saphira APF process introduces new film properties that include greater selectivity and transparency. The high-productivity PSK OMNIS Asher system is capable of completely removing the Saphira hardmask layer while preserving the patterned shapes and underlying materials. Together, these leading-edge processes have demonstrated the capabilities to meet the patterning demands of next-generation devices.

Applied has exclusively licensed its proprietary removal process for the Saphira APF hardmask to PSK. 

Kandou Bus has announced the Glasswing family of chip interconnects targeted for in-package chip-to-chip links. Kandou introduced Chord Signaling in February 2014 and outlined how signals can be correlated across more than two wires to achieve higher bandwidth and lower power with excellent signal integrity and low latency. The Glasswing architecture optimizes Chord Signaling to address the unique challenges of both substrate and interposer in-package solutions.

For the first time in history, the cost to manufacture a transitor in the most advanced silicon process has increased compared to the previous generation. As a result, system architects are looking for more cost effective ways to partition and package silicon devices for optimal performance. Integrating several chips into a shared package can be attractive, but only if the in-package communication between chips allows for extremely high bandwidth and very low power.

“Architectures that combine multiple chips into a single package are not new,” said Kandou Founder and CEO Amin Shokrollahi, “but increasing bandwidth and improving signal integrity while maintaining very low power in an affordable package is a daunting task. Glasswing delivers on the promise of 2.5D integration by providing a cost-effective solution that offers unprecendented, in-package, chip-to-chip bandwidth at very low power.”

Glasswing Architecture and Applications

The core of Kandou’s Glasswing technology is a chordal code that delivers five bits over six correlated wires within each clock cycle. Through a simple yet elegant comparator network, signals are received and translated into bits resulting in much higher overall link throughput.

Depending on the application the link can run at up to 25 GBaud and deliver up to 20.8 Gbps per wire at less than 0.5pJ/bit in a 28nm logic process. These benefits are ideal for very short links (less than 10mm) such as the connnection inside a package between a DRAM stack and a controller, the link to an out-boarded high speed SerDes, or the coherency buses of a partitioned multi-core processor. The link can also work over channels up to 25mm in length with slightly more power.

To fully realize the benefits of the Glasswing architecture, Kandou has developed optimized circuits and architectures for all parts of the transmission chain including serializers, drivers, receivers, CDR units, skew mitigators, equalizers, deserializers and test circuits.

Kandou’s Glasswing product development is underway for the first instantiation of the PHY optimized for in-package links between processor cores. A comprehensive 28nm PHY evaluation package will be available Q3 2015.

What does it take to fabricate electronic and medical devices tinier than a fraction of a human hair? Nanoengineers at the University of California, San Diego recently invented a new method of lithography in which nanoscale robots swim over the surface of light-sensitive material to create complex surface patterns that form the sensors and electronics components on nanoscale devices. Their research offers a simpler and more affordable alternative to the high cost and complexity of current state-of-the-art nanofabrication methods such as electron beam writing.

Led by distinguished nanoengineering professor and chair Joseph Wang, the team developed nanorobots, or nanomotors, that are chemically-powered, self-propelled and magnetically controlled. Their proof-of-concept study demonstrates the first nanorobot swimmers able to manipulate light for nanoscale surface patterning. The new strategy combines controlled movement with unique light-focusing or light-blocking abilities of nanoscale robots.

“All we need is these self-propelled nanorobots and UV light,” said Jinxing Li, a doctoral student at the Jacobs School of Engineering and first author. “They work together like minions, moving and writing and are easily controlled by a simple magnet.”

State-of-art lithography methods such as electron beam writing are used to define extremely precise surface patterns on substrates used in the manufacture of microelectronics and medical devices.  These patterns form the functioning sensors and electronic components such as transistors and switches packed on today’s integrated circuits. In the mid-20th century the discovery that electronic circuits could be patterned on a small silicon chip, instead of assembling independent components into a much larger “discrete circuit,” revolutionized the electronics industry and set in motion device miniaturization on a scale previously unthinkable.

Today, as scientists invent devices and machines on the nanoscale, there is new interest in developing unconventional nanoscale manufacturing technologies for mass production.

Li was careful to point out that this nanomotor lithography method cannot completely replace the state-of-the-art resolution offered by an e-beam writer, for example. However, the technology provides a framework for autonomous writing of nanopatterns at a fraction of the cost and difficulty of these more complex systems, which is useful for mass production. Wang’s team also demonstrated that several nanorobots can work together to create parallel surface patterns, a task that e-beam writers cannot perform.

The team developed two types of nanorobots: a spherical nanorobot made of silica that focuses the light like a near-field lens, and a rod-shape nanorobot made of metal that blocks the light. Each is self-propelled by the catalytic decomposition of hydrogen peroxide fuel solution. Two types of features are generated: trenches and ridges. When the photoresist surface is exposed to UV light, the spherical nanorobot harnesses and magnifies the light, moving along to create a trench pattern, while the rod-shape nanorobot blocks the light to build a ridge pattern.

“Like microorganisms, our nanorobots can precisely control their speed and spatial motion, and self-organize to achieve collective goals,” said professor Joe Wang. His group’s nanorobots offer great promise for diverse biomedical, environmental and security applications.

UC San Diego is investing heavily in robotics research while leveraging the partnership opportunities afforded by regional industry expertise in supporting fields such as defense and wireless technology, biotech and manufacturing. The Contextual Robotics Technologies International Forum was hosted by the Jacobs School of Engineering, the Qualcomm Institute and the Department of Cognitive Science.

Joe Wang is the director of the Center for Wearable Sensors at UC San Diego Jacobs School of Engineering and holds the SAIC endowed chair in engineering.