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Belgian nanoelectronics research center imec has announced a joint development project with Coventor, a supplier of semiconductor process development tools. The collaboration will enable faster and more optimized development of advanced manufacturing technology in the 3D device architecture era, extending down to imec’s 10- and 7-nanometer (nm) processes.

To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimize process step performance and control methodology. Using Coventor’s SEMulator3D platform, engineers from imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies. The SEMulator3D platform is an integrated set of modeling tools with enhanced visibility, accuracy and performance that enables engineers to interactively model and simulate a wide range of manufacturing effects in software before committing to expensive test chips.

At imec, process and integration experts have connected optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using  Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions. Moreover, a Spacer-Assisted Quad Patterning scheme for 7nm dense interconnect was devised using SEMulator3D, and process window marginalities for an immersion based multiple block patterning solution were analyzed. Additional collaboration will focus on the predictive modeling of Directed Self-Assembly for advanced patterning.

An Steegen, senior vice president process technology at imec said:  “A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available.  The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”

“Imec is the premier semiconductor research center, and this collaboration allows us to synchronize our modeling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology,” said David Fried, Chief Technical Officer, Semiconductor, at Coventor. “Working together with imec on novel integration schemes, designing SEMulator3D-specific structures for imec’s testsites, and then calibrating advanced models to imec’s wafer processing is an extremely effective and valuable way for Coventor to optimize our virtual fabrication platform for emerging market requirements.”

imec&conventor

Samsung today announced that it is mass producing the industry’s most advanced 8-gigabit (Gb) DDR4 memory and 32-gigabyte (GB) module, both of which will be manufactured based on a new 20-nanometer (nm) process technology, for use in enterprise servers.

“Our new 20nm 8Gb DDR4 DRAM more than meets the high performance, high density and energy efficiency needs that are driving the proliferation of next-generation enterprise servers,” said Jeeho Baek, Vice President of Memory Marketing at Samsung Electronics. “By expanding the production of our 20nm DRAM line-ups, we will provide premium, high-density DRAM products, while handling increasing demand from customers in the global premium enterprise market.”

With its new 8Gb DDR4, Samsung now offers a full line-up of 20nm-based DRAM to lead a new era of 20nm DRAM efficiency that also includes the 20nm 4Gb DDR3 for PCs and the 20nm 6Gb LPDDR3 for mobile devices.

Using the new 8Gb DDR4 chip, Samsung began producing the 32GB registered dual in-line memory module (RDIMM) earlier this month. The new module’s data transfer rate per pin reaches up to 2,400 megabits per second (Mbps), which delivers an approximately 29 percent performance increase, compared to the 1,866 Mbps bandwidth of a DDR3 server module.

Beyond the 32GB modules, the new 8Gb chips will allow production of server modules with a maximum capacity of 128GB by applying 3D through silicon via (TSV) technology, which will encourage further expansion of the high-density DRAM market.

The new high density DDR4, also boasts improved error correction features, which will increase memory reliability in the design of enterprise servers. In addition, the new DDR4 chip and module use 1.2 volt, which is currently the lowest possible voltage.

The development of increasingly sophisticated and energy-efficient CMOS technology for mobile, client and cloud computing depends on a continuing stream of advances in the process technologies with which the complex integrated circuits are built. Among the most promising chip technologies are transistors called FinFETs, which have attracted significant R&D investment and have begun to appear in commercial products.

But the technology is complex and the path forward isn’t settled, and in two late-news papers to be given at this December’s IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present dueling approaches to the development of FinFET technology for the 14nm technology node, the semiconductor industry’s next big hurdle.

The IEDM is the forum where top technical experts in micro- and nanoelectronics gather to disclose, discuss and debate breakthrough technologies in the field. The 60th annual IEDM will be held at the Hilton San Francisco Union Square Hotel from December 15-17, 2014, preceded by day-long short courses on Sunday, Dec. 14 and a program of 90-minute tutorials on Saturday, Dec. 13.

All modern transistors have a channel to conduct electricity and one or more gates to turn the current on and off. FinFETs have long, thin fin-like channels (hence the name) surrounded by multiple gates. This design leads to greater performance and enhanced energy efficiency. Both Intel and IBM will present fully integrated 14nm FinFET technologies at the IEDM.

Intel, which began using FinFET transistors commercially in its “Ivy Bridge” and “Haswell” processors at the 22nm node, will detail the second generation of that technology.[i] Made on a standard bulk silicon substrate, the new “Broadwell” 14nm technology has been released commercially and is in production as part of Intel’s latest family of microprocessors.

Among the technical features Intel will discuss at the IEDM are: a novel doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in improvement in variation; two levels of air-gap-insulated interconnects (electrical connections) at ultra-narrow 80 and 160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588µm2; and saturated drive currents significantly higher than for Intel’s 22nm first-generation FinFETs (improvements of 15% and 41% for NMOS and PMOS transistors, respectively). The transistors operate with a supply voltage of only 0.7 Volts.

The researchers also will discuss how aggressive design rules enabled the production of very high aspect ratio rectangular fins (8nm wide and 42nm high) at unprecedented levels of uniformity.

IBM, meanwhile, will describe a very different approach to 14nm FinFET transistors.[ii] The IBM devices are made not from a standard bulk silicon substrate but from an insulating substrate known as SOI, a more expensive material but one which simplifies manufacturing in terms of device isolation. These devices are more than 35% faster than IBM’s 22nm planar (i.e. standard, non-FinFET) transistors, with an operating voltage of just 0.8 volts.

The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. IBM also designed an elegant way to make the technology suitable for both low-power and high-speed applications, using a unique dual-workfunction process that optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel.

Because the technology is envisioned for use in system-on-a-chip (SoC) applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom that ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

Making transistors smaller, or scaling them according to Moore’s Law, is what has traditionally driven exponential progress in nanoelectronics and information technology. With today’s nanoscale-sized devices that has become difficult and expensive, which is why new transistor architectures such as FinFETs have become so appealing.

[i] Paper #3.7, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size,” S. Natarajan et al, Intel

[ii]  Paper #3.8, “High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization,” C.-H. Lin et al, IBM

Element Six this week announced the development of a new thermal grade of diamond grown by chemical vapor deposition (CVD), DIAFILM TM130. DIAFILM TM130 has a thermal conductivity in excess of 1300 W/mK and is available in both metallized and un-metallized wafers form.  Similar to Element Six’s material grades in its DIAFILM TM range, TM130 offers full isotropic heat spreading in both planar and through plane directions. Element Six now provides a total of five material grades spanning five levels of performance ranging from 1000 W/mK to 2000 W/mK.

“CVD diamond is the most thermally conductive material at room temperature, far surpassing the thermal conductivity of copper. With this new offering, we’re continuing to build our extensive portfolio of thermal grade materials to meet the needs of those in the microelectronics and electronics packaging industry,” said Director of Element Six Technologies, Adrian Wilson. “Recognizing a ‘one-size fits all’ approach is not effective, we’re committed to providing a full range of options and specifications to effectively address thermal management challenges, including specific requirements for surface flatness, low roughness and metallization.”

CVD diamond is uniquely suited for advanced thermal management in applications such as advanced packaging, due to its exceptional combination of properties including high thermal conductivity, mechanical strength, electrical insulation, low weight and chemical inertness. In this role, CVD diamond enables system size reductions, improved reliability and the opportunity to design higher power systems within an existing module footprint.

With a focus on customizability, Element Six’s solid thermal products are available up to three millimeters thick and in diameters up to 140 millimeters that can be laser cut to any required size. Furthermore, metallization solutions enable die bonding with low thermal barrier resistance, consistent with industry standard soldering and brazing.

At the IMAPS 47th International Symposium on Microelectronics, Element Six will present on “Advanced Thermal Dissipation in GaN-on-Diamond Transistors,” developed in conjunction with the University of Notre Dame, on Wednesday, Oct. 15 at 8 a.m. PT. This presentation will discuss the thermal barriers that stand in the way of achieving the intrinsic performance potential of gallium nitride (GaN) semiconductors. In reviewing challenges, the presentation will share details about a recent solution which replaces GaN’s entire host substrate—such as silicon (Si) or silicon carbide (SiC)—with a synthetic diamond substrate, resulting in a more than 40 percent reduction of peak device temperature.

A system is described that mitigates unintended oxide growth for bare wafers while in-process storage and potentially post process at tools using nitrogen purge. 

BY SURESH BILIGIRI, Rorze Automation, Fremont, CA 

Unintended oxide growth on wafers while in storage or while in process is an important cause of excess process variability that can lead to poor yield and product quality.

To understand and eliminate the undesired oxide growth on wafers while in storage or between processes, we evaluated and compared wafers storied in a nitrogen-based environment to wafers stored in normal cleanroom environment. Important issues to consider:

  • A typical wafer goes through a clean cycle prior to wafer moves.
  • There are waste chemical handling costs involved in the handling, treatment and disposal of waste chemicals.
  • If the oxide growth are uncertain, then metrology of these wafer before wafer move has to be performed and this adds more cost to the process.
  • If the oxide growth has exceeded the specification, then a second re-cleaning cost is added to the process.
  • Due to stringent environmental controls and corporate responsibility in green initiatives the cost of handling the waste chemicals will have an impact of greater than twice the first cleaning.
  • Each time a wafer is handled, the risk of loss increases causing an impact on yield.
  • In a high demand situation where the fab utilization is approaching the high numbers, the re-clean adds costs and a negatively impacts production volumes.

In order to assess the impact of the unintended oxide growth, tests were conducted at a semiconductor manufacturing fab using a standard bare wafer stocker (BWS600 by Rorze) and a nitrogen purge type stocker (BWS1600 N2 by Rorze). The wafers were removed from each to test for oxide growth and returned to storage after measuring. The tests were repeated with the same set of wafers and data is shared here.

The Rorze BWS1600 N2 consists of wafer PODS (about the size of a FOUP) that are stacked on a carousal. Each POD with 25 wafers is purged with N2 continually. In order to minimize the use of nitrogen and to create a very low O2 level, the POD has independent access door for each wafer slot on the POD (9mm door). This method (Rorze patent pending) offers N2 environment for wafers inside even during the wafer transfer from and to the POD with minimum ambient air interaction. The system and the storage method is shown in FIGURE 1.

FIGURE 1. The design is executed for minimal consumption of N2 as well as to mitigate the hazards of excess N2 in the fab.

FIGURE 1. The design is executed for minimal consumption of N2 as well as to mitigate the hazards of excess N2 in the fab.

FIGURES 2 and 3 shows the N2 and O2 purging sequence data. Note that:

  1. When the shutter is open, O2 density will be increased because of mixture of air of mini- environment (FFU) is forced into the POD/ container environment.
  2. When the shutter is open, N2 gas supply volume will be increased from 5 L/min to 20 L/min from the POD that helps to reduce O2 density inside the POD.
  3. At any given time, when the shutter is open, even with the strong FFU flow as the wafer on end-effector directs flow from FFU the N2 concentration in the POD does not go above 5000 PPM
FIGURE 2. O2 density during wafer handling.

FIGURE 2. O2 density during wafer handling.

FIGURE 3. N2/oxygen density data during storage conditions.

FIGURE 3. N2/oxygen density data during storage conditions.

The results of the oxide growth measurements on wafers stored in N2 environment (Rorze BWS1600 N2) were obtained on a regular frequency (Day 1, 3, 6, 7 10, 14 & 21).

Measurements were made using “Rudolph S3000A” metrology thicknesstool.Toensure the effect is uniform across the stored area, wafers were placed in different PODS inside (C8 is at top on the carousal close to FFU and C1 is farthest from FFU at the bottom).

An identical test method was executed by storing wafers in a bare wafer storage unit where wafer was exposed to the fab environment but in a clean storage area. (Rorze BWS600)

Results of the tests are shown in FIGURE 4. Wafers were set at different locations in the stocker to test the influence of storage location on rate of oxide growth. We found no noticeable difference in oxide growth for different cassettes. Even after 21 days with intermittent extraction to monitor growth (every three days), all wafers had less than 1.7 Anstrom thickness oxide growth. The impact of oxide growth without intermittent exposure could be much smaller.

FIGURE 4. Oxide growth is small even after 21 days.

FIGURE 4. Oxide growth is small even after 21 days.

Cost analysis

As per an earlier Sematech model that takes into account the cost of materials, capital tool costs, uptime in the fab etc. for wafer clean per wafer pass following were the costs estimated and noted below. (Data reference provide by Mr. Rob Randhawa, Founder & CEO of Planar Semiconductor)

  • Single wafer cleaning cost per wafer using DI water based cleaning only: $1.90 per wafer – 300mm wafer
  • Single wafer cleaning cost per wafer using standard chemicals without the IPA: $2.30 per wafer – 300mm wafer
  • Single wafer cleaning cost per wafer using standard chemicals + IPA: $ 3.60 per wafer – 300mm wafer – This includes the reprocess cost of IPA

Based on the initial results we see, there is a substantial benefit to employ this technology that will help to make strides in continuing to help on cost controls while the technology node advances. The opportunity to eliminate the risk of oxide growth can potentially go beyond the wafer clean and to “in-process storage” where a wafer lot is in queue for the next step. There is a risk of delay where the wafer could continue to gain oxide growth resulting in potential yield loss and a domino effect of reduced productivity and a risk of not meeting demand.

As technology proceeds to smaller nodes, the tolerance for variations within atomic layers are not acceptable as it will impact performance and yield, necessitating such products and technologies to keep the cost down.

Tools such as the N2 purged bare wafer stocker can save anywhere from about $900,000 to about $1.7 million per year and easily pay off the cost of the system within a year or two.

Acknowledgements

Rob Randhawa, Founder and CEO of Planar semicon- ductor for sharing wafer cleaning costs, K.Sakata, Design Engineering Manager, at Rorze Corporation for technical details of the BWS1600/BWS3200 N2 purge system.

Albert Theuwissen, CEO of Harvest Imaging and professor at Delft University of Technology, is the recipient of the European SEMI Award 2014. The Award, which recognizes Theuwissen’s outstanding contribution to the continuing education of engineers, was presented during the SEMICON Europa Executive Summit in Grenoble today.

Albert Theuwissen is a highly regarded specialist in solid-state image sensors and digital imaging. He worked for nearly 20 years at Philips Research and then at DALSA in lead engineering and management roles. In 2001, Theuwissen became a part-time professor at Delft University of Technology.  In 1995, he wrote the textbook “Solid-State Imaging with Charge-Coupled Devices” which is now a standard reference work in the field of solid-state imaging.

After “retiring” in 2007, Theuwissen founded Harvest Imaging and has played a major role in the continuing education of engineers in the field of solid-state imaging and digital cameras. He has taught and trained over 3,000 engineers at image sensor companies (such as Kodak, Sony, Samsung, Aptina, ST Microelectronics, Micron, Intel, Philips, Canon, DALSA, and Panasonic) and consumer product companies (such as Nokia, Sony-Ericsson, Motorola, Siemens, Research InMotion, Thomson, and many others).  In addition, he has conducted short courses at IEEE’s IEDM, ISSCC, ICIP and SPIE’s Electronic Imaging Conference.

Solid-state image sensors such as the Charge-Coupled Device (CCD) and CMOS Image Sensor (CIS) are complex electron devices.  About one billion image sensor chips are fabricated and sold each year and represent a multi-billion dollar per year IC business segment.  Understanding the fabrication and device physics operation of these devices is difficult and is rarely taught in universities at either the undergraduate or graduate level.

Theuwissen has had a major impact on both the continuing education of engineers and the advancement of consumer digital imaging.  Continuing education — outside of the scope of university professors operating as part-time short-course instructors — within the industry is critical.  By educating technologists and application specialists, Theuwissen created a successful model for future technological education: the entrepreneur-educator.

“Albert recognized the need for technical education and created a successful continuing education offering that navigates and conforms to the competitive and proprietary IP environment, benefitting thousands of electron-device engineers and also the industry,” said Heinz Kundert, president of SEMI Europe. “It is an honor to recognize Albert for his outstanding contributions to the European semiconductor and microsystems industry.”

The European SEMI Award was established more than two decades ago to recognize individuals and teams who made a significant contribution to the European semiconductor and related industries. Prior award recipients hailed from these companies: Infineon, Semilab, Deutsche Solar, STMicroelectronics, IMEC, Fraunhofer Institute, and more.

FlipChip International (FCI), a developer of flip chip bumping and advanced wafer level packaging technologies, announced that their engineering team had completed design and production of the 250th Multi-Product Wafer Bump design since January 2013.

Multi-Product Wafer (MPW) Bump Designs are complex and challenging to create but provide a way for customers to quickly test multiple IC designs and provide samples to customers. MPW wafers have many different ICs fabricated on the same wafer. These can be design variations of a single base IC, to help optimize functional performance, or many completely different ICs with different die sizes. FCI has created thousands of product and MPW designs for customers around the world, and partners with many semiconductor manufacturers and foundries to enable them to test out hundreds of new IC designs and sample their customers with bumped ICs without going to the cost of creating individual mask sets for each new IC. FCI’s ability to design, manufacture, and inspect a large number of MPW designs, as well as full-production designs, places them at the cutting edge of advanced Wafer Level Package development.

Doug Scott, FlipChip’s Sr. Director of Engineering, said, “This is an important milestone for FlipChip, reaching the 250 MPW designs in such a short time frame. I’m very proud of the technical team at FCI in achieving this accomplishment. Our dedication to supporting the engineering requirements of all of our customers is an important strength of FCI. We strive to find the best technical solution for our customers, and we’re very pleased to be such an important part of our customers’ development strategy.”

David Wilkie, FlipChip’s CEO, said, “I’d like to congratulate the team for this important milestone. The dedication of the Engineering group in supporting customers around the world in finding the best technical solution to their wafer level packaging challenges remains a core strength of FCI. We’re very proud of our engineering team, and we remain committed to supporting our customers at the highest technical levels.”

Researchers from The University of Texas at Dallas have created technology that could be the first step toward wearable computers with self-contained power sources or, more immediately, a smartphone that doesn’t die after a few hours of heavy use.

This technology, published online in Nature Communications, taps into the power of a single electron to control energy consumption inside transistors, which are at the core of most modern electronic systems.

Researchers from the Erik Jonsson School of Engineering and Computer Science found that by adding a specific atomic thin film layer to a transistor, the layer acted as a filter for the energy that passed through it at room temperature. The signal that resulted from the device was six to seven times steeper than that of traditional devices. Steep devices use less voltage but still have a strong signal.

“The whole semiconductor industry is looking for steep devices because they are key to having small, powerful, mobile devices with many functions that operate quickly without spending a lot of battery power,” said Dr. Jiyoung Kim, professor of materials science and engineering in the Jonsson School and an author of the paper. “Our device is one solution to make this happen.”

Tapping into the unique and subtle behavior of a single electron is the most energy-efficient way to transmit signals in electronic devices. Since the signal is so small, it can be easily diluted by thermal noises at room temperature. To see this quantum signal, engineers and scientists who build electronic devices typically use external cooling techniques to compensate for the thermal energy in the electron environment. The filter created by the UT Dallas researchers is one route to effectively filter out the thermal noise.

Dr. Kyeongjae “K.J.” Cho, professor of materials science and engineering and physics and an author of the paper, agreed that transistors made from this filtering technique could revolutionize the semiconductor industry.

“Having to cool the thermal spread in modern transistors limits how small consumer electronics can be made,” said Cho, who used advanced modeling techniques to explain the lab phenomena. “We devised a technique to cool the electrons internally — allowing reduction in operating voltage — so that we can create even smaller, more power efficient devices.”

Each time a device such as a smartphone or a tablet computes it requires electrical power for operation. Reducing operating voltage would mean longer shelf lives for these products and others. Lower power devices could mean computers worn with or on top of clothing that would not require an outside power source, among other things.

To create this technology, researchers added a chromium oxide thin film onto the device. That layer, at room temperature of about 80 degrees Fahrenheit, filtered the cooler, stable electrons and provided stability to the device. Normally, that stability is achieved by cooling the entire electronic semiconductor device to cryogenic temperatures — about minus 321 degrees Fahrenheit.

Another innovation used to create this technology was a vertical layering system, which would be more practical as devices get smaller.

“One way to shrink the size of the device is by making it vertical, so the current flows from top to bottom instead of the traditional left to right,” said Kim, who added the thin layer to the device.

Lab test results showed that the device at room temperature had a signal strength of electrons similar to conventional devices at minus 378 degrees Fahrenheit. The signal maintained all other properties. Researchers will also try this technique on electrons that are manipulated through optoelectronic and spintronic — light and magnetic — means.

The next step is to extend this filtering system to semiconductors manufactured in Complementary Metal-Oxide Semiconductor (CMOS) technology.

“Electronics of the past were based on vacuum tubes,” Cho said. “Those devices were big and required a lot of power. Then the field went to bipolar transistors manufactured in CMOS technology. We are now again facing an energy crisis, and this is one solution to reduce energy as devices get smaller and smaller.”

Researchers from the Lam Research Corporation in California, Nankai University in China, the University of Michigan and the University of Texas at Arlington contributed to this work.

Electrical engineers at the Technische Universität München (TUM) have demonstrated a new kind of building block for digital integrated circuits. Their experiments show that future computer chips could be based on three-dimensional arrangements of nanometer-scale magnets instead of transistors. As the main enabling technology of the semiconductor industry – CMOS fabrication of silicon chips – approaches fundamental limits, the TUM researchers and collaborators at the University of Notre Dame are exploring “magnetic computing” as an alternative. They report their latest results in the journal Nanotechnology.

In a 3D stack of nanomagnets, the researchers have implemented a so-called majority logic gate, which could serve as a programmable switch in a digital circuit. They explain the underlying principle with a simple illustration: Think of the way ordinary bar magnets behave when you bring them near each other, with opposite poles attracting and like poles repelling each other. Now imagine bringing several bar magnets together and holding all but one in a fixed position. Their magnetic fields can be thought of as being coupled into one, and the “north-south” polarity of the magnet that is free to flip will be determined by the orientation of the majority of fixed magnets.

Gates made from field-coupled nanomagnets work in an analogous way, with the reversal of polarity representing a switch between Boolean logic states, the binary digits 1 and 0. In the 3D majority gate reported by the TUM-Notre Dame team, the state of the device is determined by three input magnets, one of which sits 60nm below the other two, and is read out by a single output magnet.

The latest in a line of advances

This work builds on capabilities the collaborators have developed over several years, ranging from sophisticated simulations of magnetic behavior to innovative fabrication and measuring techniques. It also represents not an end point but a milestone in a series of advances.

For example, they reported the world’s first “domain wall gate” at last year’s International Electron Devices Meeting. The scientists use focused ion-beam irradation to change the magnetic properties of sharply defined spots on the device. So-called domain walls generated there are able to flow through magnetic wires under the control of surrounding nanomagnets. This 2D device, TUM doctoral candidate Stephan Breitkreutz explains, “enables signal routing, buffering, and synchronization in magnetic circuits, similar to latches in electrical integrated circuits.”

A fork in the industry roadmap

All players in the semiconductor business benefit from one industry-wide cooperative effort: developing long-range “roadmaps” that chart potential pathways to common technological goals. In the most recent issue of the International Technology Roadmap for Semiconductors, nanomagnetic logic is given serious consideration among a diverse zoo of “emerging research devices.” Magnetic circuits are non-volatile, meaning they don’t need power to remember what state they are in. Extremely low energy consumption is one of their most promising characteristics. They also can operate at room temperature and resist radiation.

The potential to pack more gates onto a chip is especially important. Nanomagnetic logic can allow very dense packing, for several reasons. The most basic building blocks, the individual nanomagnets, are comparable in size to individual transistors. Furthermore, where transistors require contacts and wiring, nanomagnets operate purely with coupling fields. Also, in building CMOS and nanomagnetic devices that have the same function – for example, a so-called full-adder – it can take fewer magnets than transistors to get the job done.

Finally, the potential to break out of the 2D design space with stacks of 3D devices makes nanomagnetic logic competitive. TUM doctoral candidate Irina Eichwald, lead author of the Nanotechnology paper, explains: “The 3D majority gate demonstrates that magnetic computing can be exploited in all three dimensions, in order to realize monolithic, sequentially stacked magnetic circuits promising better scalability and improved packing density.”

“It is a big challenge to compete with silicon CMOS circuits,” adds Dr. Markus Becherer, leader of the TUM research group within the Institute for Technical Electronics. “However, there might be applications where the non-volatile, ultralow-power operation and high integration density offered by 3D nanomagnetic circuits give them an edge.”

This research was supported by the German Research Foundation (DFG).

TSMC today announced that its has successfully produced the foundry segment’s first fully functional ARM-based networking processor with FinFET technology, through its collaboration with HiSilicon Technologies Co, Ltd.

TSMC’s 16FinFET process promises impressive speed and power improvements as well as leakage reduction. All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology. It has twice the gate density of TSMC’s 28HPM process, and operates more than 40 percent faster at the same total power, or reduces total power over 60% at the same speed.

“Our FinFET R&D goes back over a decade and we are pleased to see the tremendous efforts resulted in this achievement,” said TSMC President and Co-CEO, Dr. Mark Liu. “We are confident in our abilities to maximize the technology’s capabilities and bring results that match our long track record of foundry leadership in advanced technology nodes.”

TSMC’s 16FinFET has entered risk production with excellent yields after completing all reliability qualifications in November 2013. This paves the way for TSMC and customers to engage in more future product tape-outs, pilot activities and early sampling.

Built on TSMC’s 16FinFET process, HiSilicon’s new processor enables a significant leap in performance and power optimization supporting high-end networking applications. By leveraging TSMC’s heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) 3D IC packaging process, HiSilicon integrates its 16-nanometer logic chips with a 28-nanometer I/O chip for a cost-effective system solution.

“We are delighted to see TSMC’s FinFET technology and CoWoS solution successfully bringing our innovative designs to working silicon,” said HiSilicon President Teresa He.”This industry’s first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz. This networking processor’s performance increases by three fold compared with its previous generation. Such a highly competitive product can support virtualization, SDN and NFV applications for next-generation base stations, routers and other networking equipment, and meet our time-to-market goals.”