Tag Archives: letter-ap-tech

Contour Semiconductor, Inc., a developer of non-volatile memory technologies, today announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.The three new patents recognize Contour’s achievements in the field of low-mask count/reduced process step memory, and bring the company’s total issued patents to 45.

The new patents focus on better and more cost effective approaches to phase-change and resistive non-volatile memory, 3D memory, and embedded memory applications – concepts that are “top of the list” for memory manufacturers and their customers.

“Contour’s patent portfolio seeks to return Moore’s Law to the non-volatile discussion, and enable the next big thing,” said Contour CEO Saul Zales. “DTM technology will overcome production and CapEx challenges that stymie NAND manufacturers, and deliver significant technical advantages over traditional NAND flash memory, to support emerging and future technologies like wearables, Internet connected devices and the Internet of Things.”

Contour estimates the production cost of its DTM to be 60-65 percent lower than today’s NAND memory, while maintaining or improving on NAND’s performance and endurance.

NAND is currently used in a wide range of products from digital photography to smartphones and solid-state drives. However, in recent years, the high costs associated with production tools and fabrication facilities have slowed NAND bit growth rate from 70-80 percent to 25-30 percent annually.

ProPlus Design Solutions, Inc. today announced Samsung Electronics has extended its partnership with ProPlus through the deployment of ProPlus’ BSIMProPlus modeling platform for its 14nanometer (nm) FinFET SPICE modeling.

Additionally, Samsung has adopted the 9812D system, the latest generation 1/f noise characterization system, for advanced node process technology development after being a user of 9812B, formerly the industry’s de facto standard 1/f measurement system.

ProPlus’ BSIMProPlus modeling solutions, the 20-year de facto golden modeling solution, has been used by Samsung for more than 15 years to generate SPICE models for its advanced process technologies, including Samsung’s 14nm FinFET technology offerings.

“Samsung has already completed 14LPE FinFET process qualification and started risk production,” remarks Dr. Steve Kwon, vice president of Design Service team at Samsung Electronics. “Based on successful collaboration with our ecosystem partners including ProPlus, we overcame technological challenges in 14nm FinFET technology, and are currently providing our customers with complete SPICE modeling support.”

As the global leader for SPICE modeling solutions and the leading technology provider for Design-for-Yield (DFY) applications, ProPlus provides advanced modeling solutions to all leading foundries and integrated device manufacturers (IDMs). With 20 years’ continuous investment, its BSIMProPlus modeling platform provides the most complete support for all mainstream and leading-edge technologies and is widely used for baseband, RF, noise, reliability, statistical and stress modeling in more than 100 semiconductor companies worldwide.

ProPlus launched 9812D in 2013 for low-frequency noise characterization and process quality monitoring at advanced nodes such as 28nm bulk CMOS, 14nm FinFET and beyond. 9812D offers the highest accuracy, true 10 megahertz (MHz) bandwidth for on-wafer measurement and greatly improved performance with its multiple low-noise amplifiers (LNAs), and a built-in dynamic signal analyzer (DSA) with multi-threaded processing.

“As a valued partner, Samsung has offered us invaluable feedback on our tools and technology roadmap,” comments Dr. Zhihong Liu, chairman and CEO of ProPlus Design Solutions. “As a result, we made a significant investment in BSIMProPlus, including increased performance and capability with a full parallel statistical SPICE engine we call NanoSpice.

“BSIMProPlus, with its full variation modeling capabilities, laid the foundation for ProPlus’ unique position and focus on DFY and support for advanced process nodes, such as FinFET,” adds Dr. Liu.

Scientists have developed what they believe is the thinnest-possible semiconductor, a new class of nanoscale materials made in sheets only three atoms thick.

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors.

The University of Washington researchers have demonstrated that two of these single-layer semiconductor materials can be connected in an atomically seamless fashion known as a heterojunction. This result could be the basis for next-generation flexible and transparent computing, better light-emitting diodes, or LEDs, and solar technologies.

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors. Photo credit: U of Washington

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors. Photo credit: U of Washington

“Heterojunctions are fundamental elements of electronic and photonic devices,” said senior author Xiaodong Xu, a UW assistant professor of materials science and engineering and of physics. “Our experimental demonstration of such junctions between two-dimensional materials should enable new kinds of transistors, LEDs, nanolasers, and solar cells to be developed for highly integrated electronic and optical circuits within a single atomic plane.”

The research was published online this week in Nature Materials.

The researchers discovered that two flat semiconductor materials can be connected edge-to-edge with crystalline perfection. They worked with two single-layer, or monolayer, materials – molybdenum diselenide and tungsten diselenide – that have very similar structures, which was key to creating the composite two-dimensional semiconductor.

Collaborators from the electron microscopy center at the University of Warwick in England found that all the atoms in both materials formed a single honeycomb lattice structure, without any distortions or discontinuities. This provides the strongest possible link between two single-layer materials, necessary for flexible devices. Within the same family of materials it is feasible that researchers could bond other pairs together in the same way.

A high-resolution scanning transmission electron microscopy (STEM) image shows the lattice structure of the heterojunctions in atomic precision. Photo credit: U of Warwick

A high-resolution scanning transmission electron microscopy (STEM) image shows the lattice structure of the heterojunctions in atomic precision. Photo credit: U of Warwick

The researchers created the junctions in a small furnace at the UW. First, they inserted a powder mixture of the two materials into a chamber heated to 900 degrees Celsius (1,652 F). Hydrogen gas was then passed through the chamber and the evaporated atoms from one of the materials were carried toward a cooler region of the tube and deposited as single-layer crystals in the shape of triangles.

After a while, evaporated atoms from the second material then attached to the edges of the triangle to create a seamless semiconducting heterojunction.

“This is a scalable technique,” said Sanfeng Wu, a UW doctoral student in physics and one of the lead authors. “Because the materials have different properties, they evaporate and separate at different times automatically. The second material forms around the first triangle that just previously formed. That’s why these lattices are so beautifully connected.”

With a larger furnace, it would be possible to mass-produce sheets of these semiconductor heterostructures, the researchers said. On a small scale, it takes about five minutes to grow the crystals, with up to two hours of heating and cooling time.

“We are very excited about the new science and engineering opportunities provided by these novel structures,” said senior author David Cobden, a UW professor of physics. “In the future, combinations of two-dimensional materials may be integrated together in this way to form all kinds of interesting electronic structures such as in-plane quantum wells and quantum wires, superlattices, fully functioning transistors, and even complete electronic circuits.”

This photoluminescence intensity map shows a typical piece of the lateral heterostructures. The junction region produces an enhanced light emission, indicating its application potential in optoelectronics. Photo credit: U of Washington

This photoluminescence intensity map shows a typical piece of the lateral heterostructures. The junction region produces an enhanced light emission, indicating its application potential in optoelectronics. Photo credit: U of Washington

The researchers have already demonstrated that the junction interacts with light much more strongly than the rest of the monolayer, which is encouraging for optoelectric and photonic applications like solar cells.

Other co-authors are Chunming Huang and Pasqual Rivera of UW physics; Ana Sanchez, Richard Beanland and Jonathan Peters at the University of Warwick; Jason Ross of UW materials science and engineering; and Wang Yao, a theoretical physicist of the University of Hong Kong.

This research was funded by the U.S. Department of Energy, the UW’s Clean Energy Institute, the Research Grant Council of Hong Kong, the University Grants Committee of Hong Kong, the Croucher Foundation, the Science City Research Alliance and the Higher Education Funding Council for England’s Strategic Development Fund.

Renesas Electronics Corporation, a supplier of advanced semiconductor solutions, today announced that it has obtained IEC 61508 (Functional Safety) certification for the RX631, RX63N Safety Package, featuring a robust self-diagnostic software and a safety manual for microcontrollers (MCUs) necessary to implement functional safety in industrial equipment. An RX631, RX63N Safety Solution Evaluation Kit will be available in September 2014, providing a hardware evaluation board with the RX63N MCU, the evaluation version of the self-diagnostic software library, and a Users Guide.

“Renesas is committed to the quality and the inherent functional safety of our devices, and we understand the complexity that comes with stringent standards like the IEC 61508,” said Ritesh Tyagi, vice president of marketing, Renesas Electronics America. “Our Functional Safety Package solution provides customers one less thing to worry about, reducing their risk in certifying their own safety solutions and allowing them to focus on their core areas of expertise.”

Functional safety has become a growing reality for factories, equipment manufacturers, and automation OEMs to reduce economic losses due to equipment failures production losses, and more importantly threats to personnel safety. The European Machinery Directive 2006/42/EC1 mandates support for functional safety, and efforts to bring relevant industrial equipment into compliance with functional safety standards such as IEC 61508 have been moving forward. Functional safety is now implemented on multiple industrial equipment such as industrial motor drives, control equipment, industrial networking equipment as well as sensors.

Compliance with the IEC 61508 functional safety standard not only requires system designers to perform tasks referred to as safety analysis, such as failure analysis of safety-related hardware and study of failure diagnostic methods and their diagnostic yields, but also to meet defined regulations aimed at reducing specification and design errors in the development process of safety-related systems that can result in malfunctions. In particular, maintaining conformance at all stages of the software development process is a key issue.

Of the tasks that need to be performed by system developers, such as safety analysis and study of failure diagnostic methods and diagnostic yields, Renesas has already carried out the aspects related to the MCU. For the testing process, Renesas leveraged IAR Systems’ IAR Embedded Workbench for RX certified for Functional Safety, which fulfilled the requirement for proof of tools safety certification. It offers a complete and high-performance C/C++compiler and debugger toolchain together with comprehensive documentation. In addition, the Safety Manual includes the vital information such as FIT rates and SFF (Safe Failure Fraction) computation that can be passed on to a certifying body to reduce complexity in conformance.

Renesas Electronics America, a leading supplier of advanced semiconductor solutions, today expands its portfolio of Simple Power Supply ICs, with innovative 16V input capable synchronous buck regulators that deliver up to 3A continuous current to loads at voltages as low as 0.8V. The new power supply ICs are ideal for systems requiring even lower power consumption in standby mode, and systems requiring backup power in case of power outage. The devices target applications in the industrial, office equipment, consumer, networking, smart grid, and other fields.

By reducing the power supply design workload, the new devices lower power consumption and improve the compactness of the overall system for improved power efficiency and lower BOM cost. The new Simple Power Supply ICs are available in four series with different DC/DC converter output counts and output voltages. Battery backup functionality is availability in the: RAA23012X series, RAA23013X series, RAA23022X series, and the RAA23023X series. Each series comprises three product versions, for a total of 12 new devices.

“Power semiconductor advancements have created a dynamic environment for energy saving innovations that boost the efficiency of existing applications, the electrification of more applications, and improve energy transmission,” said William Keeley, senior director product marketing at Renesas Electronics America. “Engineers and designers can confidently look to these types of power devices we are announcing today as a source of opportunity as they design their next generation energy efficient systems and products.”

As systems become more power efficient and compact in recent years, demand has grown for power supply blocks with improved power efficiency delivered in a compact form factor. One commonly used method of reducing power consumption is to incorporate a low-power mode in which only the functions needed in the microcontroller’s (MCU) standby state continues to operate. Unlike MCUs, however, such measures are rarely implemented within the power supply block itself. The common method of using a pair of diodes to implement a battery backup circuit for devices such as SRAM and MCUs, which require power even when the system is powered down, makes it difficult to maintain a compact system. What is more, in systems that require two or more voltages, the usual method is to employ multiple single-output power supply ICs or electronic components, which also presents a barrier to compactness.

MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world’s first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology. The technology breakthrough in combining the 3D IC sensor with full WLP translates directly to a 60% reduction in cost and a 50% reduction in size, enabling a new generation of mobile consumer devices including phones, tablets, toys and wearable devices.

The key to this breakthrough is MEMSIC’s proprietary and patented thermal accelerometer technology, in which the MEMS sensor structure is etched directly into standard CMOS wafers, enabling the world’s only CMOS monolithic solution. This technique uses thermal convection of heated gas molecules inside a sealed cavity to sense acceleration or inclination, and has been used for many years in MEMSIC’s products for automotive stability control and rollover detection, digital cameras, projectors and many other applications. MEMSIC’s designers have now taken the technology to a new level by combining 3D sensing with full WLP while keeping the same small size and low cost.

The MXC400xXC offers a number of benefits to system designers of space- and cost-sensitive consumer devices. In addition to offering the world’s lowest cost, the device provides 12-bit resolution on all three axes, programmable FSR of ±2g/±4g/ ±8g, an 8-bit temperature output, plus orientation/shake detection. With a package size of 1.2 x 1.7 mm, board space is reduced by 50% over industry-standard 2×2 mm solutions. And like all MEMSIC thermal accelerometers, the MXC400xXC has no moving parts, making the sensor structure extremely robust to shock and vibration (withstands shock in excess of 200,000g with no change in sensor performance). This is critically important to wearable and many consumer applications.

Dr. Yang Zhao, MEMSIC CEO and Founder, commented “While we have been supplying thermal accelerometers for more than a decade, the MXC400xXC is a real breakthrough in sensor design, signal processing architecture and MEMS WLP. This is the industry’s first and only monolithic 3D accelerometer with full WLP technology, enabling us to achieve a new level of size and cost, which are critical for mobile consumer devices.”

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

With most previous studies focused on metallic magnetic materials and their alloys due to well-established processing steps and high Curie temperatures, challenges still remain in manipulating parameters such as the type of domain walls formed, their position within the nanowires and their controlled movement along the length of the nanowires.

The UC Davis research investigates the use of complex oxides, such as La0.67Sr0.33MnO3 (LSMO), and heterostructures with other complex oxides as candidate materials. Complex oxides are part of an exciting new class of so-called “multifunctional’ materials that exhibit multiple properties (e.g. electronic, magnetic, etc.) and may thereby enable multiple functions in a single device. For the case of LSMO, it is a half metal, exhibits colossal magnetoresistance (CMR), meaning it can dramatically change electrical resistance in the presence of a magnetic field, and undergoes a simultaneous ferromagnetic-to-paramagnetic and metal-to-insulator transition at its Curie temperature.

In addition, these properties are sensitive to external stimuli, such as applied magnetic/electric fields, light irradiation, pressure and temperature. These attributes may allow researchers to better manipulate the position and movement of the magnetic domain walls along the length of the nanowires.

“While still in the early stages, the innovative research from the UC Davis team is helping the industry gain a better fundamental understanding linking the chemical, structural, magnetic and electronic properties of next-generation memory materials,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

A “valley of death” is well-known to entrepreneurs–the lull between government funding for research and industry support for prototypes and products. To confront this problem, in 2013 the National Science Foundation (NSF) created a new program called InTrans to extend the life of the most high-impact NSF-funded research and help great ideas transition from lab to practice.

Today, in partnership with Intel Corporation, NSF announced the first InTrans award of $3 million to a team of researchers who are designing customizable, domain-specific computing technologies for use in healthcare.

The work could lead to less exposure to dangerous radiation during x-rays by speeding up the computing side of medicine. It also could result in patient-specific cancer treatments.

Led by the University of California, Los Angeles, the research team includes experts in computer science and engineering, electrical engineering and medicine from Rice University and Oregon Health and Science University. The team comes mainly from the Center of Domain-Specific Computing (CDSC), which was supported by an NSF Expeditions in Computing Award in 2009.

Expeditions, consisting of five-year, $10 million awards, represent some of the largest investments currently made by NSF’s Computer, Information Science and Engineering (CISE) directorate.

Today’s InTrans grant extends research efforts funded by the Expedition program with the aim of bringing the new technology to the point where it can be produced at a microchip fabrication plant (or fab) for a mass market.

“We see the InTrans program as an innovative approach to public-private partnership and a way of enhancing research sustainability,” said Farnam Jahanian, head of NSF’s CISE Directorate. “We’re thrilled that Intel and NSF can partner to continue to support the development of domain-specific hardware and to transition this excellent fundamental research into real applications.”

In the project, the researchers looked beyond parallelization (the process of working on a problem with more than one processor at the same time) and instead focused on domain-specific customization, a disruptive technology with the potential to bring orders-of-magnitude improvements to important applications. Domain-specific computing systems work efficiently on specific problems–in this case, medical imaging and DNA sequencing of tumors–or a set of problems with similar features, reducing the time to solution and bringing down costs.

“We tried to create energy-efficient computers that are more like brains,” explained Jason Cong, the director of CDSC, a Chancellor’s Professor of computer science and electrical engineering at UCLA, and the lead on the project.

“We don’t really have a centralized central processing unit in there. If you look at the brain you have one region responsible for speech, another region for motor control, another region for vision. Those are specialized ‘accelerators.’ We want to develop a system architecture of that kind, where each accelerator can deliver a hundred to a thousand times better efficiency than the standard processors.”

The team plans to identify classes of applications that share similar computation kernels, thereby creating hardware that solves a range of common related problems with high efficiency and flexibility. This differs from specialized circuits that are designed to solve a single problem (such as those used in cell phones) or general-purpose processors designed to solve all problems.

“The group laid out a different way of presenting the problem of domain-specific computing, which is: How to determine the common features and support them efficiently?” said Sankar Basu, program officer at NSF. “They developed a framework for domain-specific hardware design that they believe can be applied in many other domains as well.”

The group selected medical imaging and patient specific cancer treatments–two important problems in healthcare–as the test applications upon which to create their design because of healthcare’s significant impact on the national economy and quality of life.

Medical imaging is now used diagnose a multitude of medical problems. However, diagnostic methods like x-ray CT (computed tomography) scanners can expose the body to cumulative radiation, which increases risk to the patient in the long term.

Scientists have developed new medical imaging algorithms that lead to less radiation exposure, but these have been constrained due to a lack of computing power.

Using their customizable heterogeneous platform, Cong and his team were able to make one of the leading CT image reconstruction algorithms a hundred times faster, thereby reducing a subject’s exposure to radiation significantly. They presented their results in May 2014 at the IEEE International Symposium on Field-Programmable Custom Computing Machines.

“The low-dose CT scan allows you to get a similar resolution to the standard CT, but the patient can get several times lower radiation,” said Alex Bui, a professor in the UCLA Radiological Sciences department and a co-lead of the project. “Anything we can do to lower that exposure will have a significant health impact.”

In theory, the technology also exists to determine the specific strain of cancer a patient has through DNA sequencing and to use that information to design a patient-specific treatment. However, it currently takes so long to sequence the DNA that once one determines a tumor’s strain, the cancer has already mutated. With domain-specific hardware, Cong believes rapid diagnoses and targeted treatments will be possible.

“Power- and cost-efficient high-performance computation in these domains will have a significant impact on healthcare in terms of preventive medicine, diagnostic procedures and therapeutic procedures,” said Cong.

“Cancer genomics, in particular, has been hobbled by the lack of open, scalable and efficient approaches to rapidly and accurately align and interpret genome sequence data,” said Paul Spellman, a professor at OHSU, who works on personalized cancer treatment and served as another co-lead on the project.

“The ability to use hardware approaches to dramatically improve these speeds will facilitate the rapid turnarounds in enormous datasets that will be necessary to deliver on precision medicine.”

Down the road, the team will work with Spellman and other physicians at OHSU to test the application of the hardware in a real-world environment.

“Intel excels in creating customizable computing platforms optimized for data-intensive computation,” said Michael C. Mayberry, corporate vice president of Intel’s Technology and Manufacturing Group and chair of Corporate Research Council. “These researchers are some of the leading lights in the field of domain-specific computing.

“This new effort enables us to maximize the benefits of Intel architecture. For example, we can ensure that Intel Xeon processor features are optimized, in connection with various accelerators, for a specific application domain and across all architectural layers,” Mayberry said. “Life science and healthcare research will undoubtedly benefit from the performance, flexibility, energy efficiency and affordability of this application.”

The InTrans program not only advances important fundamental research and integrates it into industry, it also benefits society by improving medical imaging technologies and cancer treatments, helping to extend lives.

“Not every research project will get to the stage where they’re ready to make a direct impact on industry and on society, but in our case, we’re quite close,” Cong said. “We’re thankful for NSF’s support and are excited about continuing our research under this unique private-public funding model.”

Tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. 

BY SHRINIVAS SHETTY, DAVID M. OWEN and SCOTT ZAFIROPOULO Ultratech, Inc., San Jose, CA 

Control of overlay in multi-layer devices structures has always been important in semiconductor fabrication. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. As devices shrink, the overlay require- ments become more and more stringent (FIGURE 1). The tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. The overlay budget includes contributions from the lithographic scanner, the reticle and the wafer. The wafer represents the largest source of overlay variability during high-volume manufacturing. Therefore, the development of an inspection strategy to control within-wafer and wafer-to-wafer variability may provide the key to meeting the challenges associated with future generations of devices.

Traditional wafer warpage or distortion measurements have typically used point-by-point measurements to generate low-density maps of the wafer geometry with a few hundred data points across the wafer. Depending on the specific technique, a higher density map may be possible at the expense of throughput or limiting the measurement to a small portion of the wafer. The trade-off of point density and throughput has meant that the use of wafer distortion characterization for overlay control has been limited to off-line process development and not to improve yields.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

The Superfast system based on the Coherent Gradient Sensing (CGS) interferometer uniquely provides high-density front-side pattern wafer maps (>3,000,000 data points) with fast data acquisition (seconds per wafer). The high throughput along with small foot print leads to a low cost of ownership relative to competing technologies.

This article discusses using deformation data from the front-side of a patterned wafer on the Superfast, we are able to understand the relationships between surface displacements, stress and overlay. It also reviews a case study evaluating the role of millisecond annealing parameters on overlay and stress.

Superfast (CGS) technology description

The CGS interferometer is a type of lateral shearing interferometer. The interference is generated in a self-referencing manner using two parallel diffraction gratings. This self-referencing approach eliminates the need for an independent reference beam from, for example, a flat mirror and ensures excellent fringe contrast regardless of the reflectivity of the surface under investigation. This is a key differentiator to accurately measure patterned wafers.

The interferometer essentially compares the relative heights of two points on the surface that are separated by a fixed distance, called the shearing distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography.

Application to thin film stress measurement

The Superfast inspection system is designed for semiconductor manufacturing based on the CGS interferometer. The Superfast tool features a collimated probe beam of >300mm in diameter that is expanded from a relatively low power HeNe laser. The probe beam illuminates the entire wafer at once and the wafer is supported on three lift pins, which are then subtracted from the final analysis. The beam that reflects off of the wafer surface is distorted in accordance with the local height variations of the wafer. The distorted beam is steered through the two parallel diffraction gratings to generate an interference pattern that is imaged on to a CCD array. As a result, the wafer surface is mapped with high resolution (>3,000,000 data points) with measurement times of seconds.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

Data integrity on patterned wafers is further enhanced through the implementation of phase shifting. Phase shifting is achieved by moving the gratings in the direction parallel to the shearing direction. Phase shifting provides several advantages and for the measurement of patterned wafers. The most notable being that fringe contrast in the interference fringes, that modulate with phase shifting can effectively be separated from pattern contrast, which is static with phase shifting. Phase shifting along with the inherent self-referencing nature of the CGS technique results in relatively high measurement integrity on patterned wafers without the need for dedicated or distinct targets, pads or other specialized features in the layout. Typical results are shown in FIGURE 2.

Compared to other techniques, Superfast has several distinct advantages.

  • Front Side Pattern Wafer Measurement: Core CGS 3G technology has been used to measure front-side of pattern wafers for over a decade.
  • High Data Density: Superfast generates high density maps of surface displacements that feature more than 3,000,000 points of data. In this manner, detailed within-die, die-to- die and wafer-to-wafer process variations that lead to overlay errors can be characterized.
  • High Throughput/Low Cost: The Superfast data set consists of interferometric images of the full wafer. These images can be captured rapidly using CCD camera, providing system throughputs of 100-150 wafers per hour.
  • Flexible Implementation: Superfast is capable of evaluating overlay at any step in the process flow and does not rely on dedicated overlay targets. In this manner, Superfast provides the ability to catch potential overlay problems due to process excursions upstream of lithography, thereby reducing material- at-risk and the need for subsequent scrap or rework. 
FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

Case study: millisecond anneal characterization

This section describes a case study to illustrate the application of Superfast technology to characterize a millisecond anneal process. Four wafers of a full-flow 65nm device were annealed using Laser Spike Annealing (LSA). The device contained silicon germanium with 20% Ge. The four wafers were processed at peak annealing temperatures of 1235 or 1270oC and annealing times of 200 or 400 microseconds. Process-induced deformation information was collected by measure pre-anneal and post-anneal wafer topography using the Superfast system. After millisecond annealing, the wafers were processed through to contact patterning. Overlay data was collected post-lithography for all four wafers. The overlay was measured at 9 sites per shot for 28 shots. Surface displacement data was extracted at the same nominal locations on the wafer and displacement residuals were computed using linear inter-field and intra-field correction.

The displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction are shown in FIGURE 3. Inspection of Fig. 3 reveals that the vector maps for the 1235oC temperature conditions (Figs. 3a & 3b) as well as the 1270oC / 200μs condition (Fig. 3c) all exhibit similar features such that the displacement vectors are generally in the same direction at a particular location in those three vector maps with the same relative vector magnitudes within-wafer. On the other hand, the vector map for the 1270oC / 400μs anneal (Fig. 3d) shows a fundamentally different distortion characteristic, indicating perhaps a change in deformation mechanism associated with the higher thermal budgets. This data suggests that wafer distortion measurements may provide a relatively efficient way to study transitions in mechanisms that occur under different processing conditions.

The correlation between the surface displacement residuals and the overlay residuals is shown in FIGURE 4. The data in Fig. 4 is based on the |mean|+3 sigma values of both quantities as evaluated at the locations shown in the vector maps of Fig. 3. There are several features of the plot in Fig. 4 that are notable. First, the corre- lation between overlay residuals and displacement residuals is excellent with a correlation coeffi- cient, r=0.985. Second, the extrapolation of the best-fit straight line to a displacement value of zero indicates a corresponding finite and positive overlay value of ~0.2. This result is not unexpected, since it is anticipated that other factors such as pattern placement error, lens errors and wafer distortion from other processes will contribute to the total overlay error. As such the overlay axis intercept provides an estimate of those other factors. Third, the slope of overlay versus displacement line is <1. A slope of less than 1 is consistent with the concept discussed in section 3, that the non-uniform stress component of the displacement field is related to the force acting along the interface or potential for mis-alignment. In this respect, it represents perhaps the maximum expected mis-alignment and the resulting overlay error will be some fraction of the ‘potential’ (i.e. slope <1). In addition, the slope value indicates that surface displacement is a more sensitive metric than overlay in that for the same process variability, surface displacement will change more rapidly than overlay.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

Summary and conclusions

The tightening of overlay budgets at advanced technology nodes has led to a greater importance in understanding and when possible controlling wafer distortion. This paper has provided a description of a novel measurement and analysis approach to quickly and efficiently evaluate the effect of process-induced deformation on surface displacement and its relation to overlay errors. The millisecond annealing case study showed excellent correlation between the displacement residuals and overlay residuals with the correlation coefficient of 0.985. Utilizing the fundamental advantages of the CGS technology, the superfast is well suited for front- side patterned wafer topography measurement. The system allows for rapid measurement of wafer distortion and surface displacement with very high system throughputs. Data maps consisting of >3,000,000 data points can be acquired in seconds on patterned wafers without the need for special targets or dedicated structures.

Interest in magnetic random access memory (MRAM) is escalating, thanks to demand for fast, low-cost, nonvolatile, low-consumption, secure memory devices. MRAM, which relies on manipulating the magnetization of materials for data storage rather than electronic charges, boasts all of these advantages as an emerging technology, but so far it hasn’t been able to match flash memory in terms of storage density.

In the journal Applied Physics Letters, from AIP Publishing, a France-U.S. research team reports an intriguing new multi-bit MRAM storage paradigm with the potential to rival flash memory.

Increasing the density of memory devices is highly desirable and can be accomplished via a variety of methods. One way is by reducing the patterning dimensions, which leads to an increased number of memory cells per unit surface. Another approach involves increasing the storage capacity of each individual cell — aka “multi-bit storage.”

“Multi-bit storage is typically achieved in MRAM technology by measuring the multiple voltage levels corresponding to various magnetic configurations,” explained Quentin Stainer, lead author of the paper and a Ph.D. student at SPINTEC/CEA, a research institute for electronics and information technologies located in Grenoble, France, and also affiliated with Crocus Technology, a France- and U.S.-based firm that develops magnetically enhanced semiconductor technologies.

At the heart of the team’s work is Crocus Technology’s proprietary Magnetic Logic Unit (MLU) technology, which enables the researchers to remotely control a sensor to probe these configurations. “By identifying key features of the electrical responses we obtain, typically known as ‘extrema points,’ we can infer the stored information,” Stainer said.

The highlight of their work was the “unambiguous demonstration of the feasibility of our method, with as much as 3 bits per unit cells, and recently up to 4 bits, obtained on 110-nanometer-wide devices,” he noted.

It’s also worth noting that the team says their storage paradigm should be able to provide an increased robustness and tolerance to process variability, which will make it easier to produce devices based on this technology for industrial applications.

“Our work will enable the development of products for a wide range of applications including, but not limited to, secure data storage for connected devices — such as smart card, content-addressable memory for Internet routers, as well as high-performance, high-density, and high-temperature memory,” Stainer said.

The team’s next step? Developing a fully functional multi-bit MLU memory product to further demonstrate the industrial viability of their storage paradigm. “New memory paradigms derived from this work are also under development — with potential multi-bit capacities of up to 8 bits per single cell,” he added.