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OMRON and Holst Centre/imec have unveiled a prototype of an extremely compact vibrational energy harvesting DC power supply with worlds’ highest efficiency. The prototype will be demonstrated at the TECHNO-FRONTIER2014 exhibition in Tokyo from July 23rd till July 25th. Combining OMRON’s electret energy harvester with a Holst Centre/imec power management IC, it can convert and store energy from vibrations in the µW range with high efficiency to the driving voltage of general sensors. The prototype measures just 5 x 6 cm – with potential to shrink as small as 2 x 2 cm. Its small size, light weight (15.4 gram) and user-variable output voltage are ideal for a wide-range of autonomous wireless sensor node applications in the industrial and consumer domains, particularly in inaccessible locations.

Small, autonomous wireless sensors that can simply be installed and then left to collect and share data are attracting huge interest. They are the foundation of the emerging, Internet of Things. And they could enable new levels of automation and equipment monitoring in industrial applications. The ongoing miniaturization and reduction of power consumption of sensors and microelectronics make these devices possible. However, a key question has been how to power them.

“Energy harvesting – extracting unused or waste energy from the local environment – is perfect for autonomous sensor nodes. It does away with the need for cables and changing batteries, allowing true “fix-and-forget” systems. The combination of OMRON’s robust electrostatic vibration harvester and our efficient power management technology enables an extremely compact design that can be installed in even the most inaccessible places – whereas today’s vibrational harvester power supplies are too large and too heavy,” says René Elfrink, Senior Researcher Sensors & Energy Harvesters at Holst Centre/imec.

“The vibration in the environment of customers are various and volatile. Under such an environment, our harvester can produce energy even just a little. But so far, we could not use our harvester as a stable DC power supply. Before developing this compact vibrational harvesting power supply, we benchmarked power management technologies from many potential partners and found Holst Centre/imec’s offering to be the most mature. The resulting power supply meets all the requirements for small, low-power wireless sensors, particularly industrial applications such has equipment control and predictive maintenance systems,” adds Daido Uchida, General manager of Technology Produce & Start-up division of OMRON Corporation.

Working closely with OMRON, researchers from Holst Centre/imec integrated the electrostatic harvester and power management electronics into a power-optimized module just 5 cm x 6 cm. Initial feedback from potential customers suggests this is already small enough for industrial application. However, the module has potential for further miniaturization down to 2 cm x 2 cm.

The supply’s output can be set to anything between 1.5 V and 5 V, giving users complete flexibility to replace any kind of battery in existing designs or create brand new products. The module contains an ON/OFF signal for efficient duty cycling with low power sensor systems.

OMRON is currently putting the prototype through a number of field tests with customers to gather further input before entering volume production.

OMRON

Solid State Equipment LLC (SSEC), a provider of single-wafer wet processing systems for advanced packaging (including 2.5D and 3D ICs), MEMS, and compound semiconductor markets, was awarded a 2014 3D InCites Award in the category of 2.5D/3D Manufacturing Equipment. The 3D InCites Awards recognize achievements to further the commercialization of 2.5D and 3D IC technologies. SSEC received the award for the WaferEtch TSV Revealer tool, which is a single wafer wet processing platform for 3D IC and interposer wet etching applications designed to reduce process and capital equipment costs. The WaferEtch features superior uniformity of silicon thickness (as low as -/+ 0.7%) and high throughput. 

“Bringing 3D ICs to high-volume manufacturing is a requirement for the industry to move forward into the next technology node,” said Erwan Le Roy, Marketing Vice President at SSEC. “SSEC’s WaferEtch TSV Revealer helps to achieve this through integrating a low-cost wet etch process with metrology for performing thickness measurement. Our system replaces four tools with one (CMP, silicon thickness measurement, plasma etch, and clean), so we are able to achieve this at the lowest cost to the manufacturer.”

The 3D InCites Awards were established in 2013 to recognize achievements to further the commercialization of 2.5D and 3D IC technologies. The 2014 3D InCites Awards were presented at a breakfast ceremony hosted by Impress Labs on Thursday, July 10, 2014, at the Impress Lounge during SEMICON West. The event featured guest speaker Bryan Black, Senior Fellow, AMD, who has led AMD¹s die stacking program for the past seven years. Black talked about the future of die stacking and where the benefits lie within the context of mainstream computing CPUs, APUs, and GPUs.

This year’s event was co-promoted by 3D InCites, the premier online content source for reliable 3D technology information; SEMI, the global industry association serving the nano- and microelectronics manufacturing supply chains; and TechSearch International, the leading market research firm for advanced semiconductor packaging technology.

SSEC

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the GEMINI FB XT—its next-generation fusion wafer bonding platform, which combines several performance breakthroughs to move the semiconductor industry closer to the goal of high-volume manufacturing (HVM) of 3D-ICs with through-silicon vias (TSVs).  Featuring up to a three-fold improvement in wafer-to-wafer bond alignment accuracy as well as a 50 percent increase in throughput over the previous industry benchmark platform, the GEMINI FB XT clears several key hurdles to the industry’s adoption of 3D-IC/TSV technology in order to drive continuous improvements in device density and performance without the need for increasingly costly and complex lithography processing.

ev group

Wafer-to-wafer bonding is an essential process step to enable 3D devices such as stacked DRAM, memory-on-logic and future CMOS image sensors.  At the same time, minimizing the dimensions of TSVs, which serve as the electrical contacts between the bonded wafers, is a key requirement for bringing down the cost of 3D devices and supporting higher levels of device performance and bandwidth, as well as lower power consumption.  However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.

Alignment is key for fusion-bonded 3D-ICs

According to the 2012 edition of the International Technology Roadmap for Semiconductors (ITRS), high-density TSV applications will require wafer bonding alignment accuracy of 500 nm (3 sigma) by 2015.  To enable high process yields for hybrid bonding, even tighter specifications are needed.  The GEMINI FB XT incorporates EVG’s newly introduced SmartView NT2 bond aligner, which enables dramatically improved wafer-to-wafer alignment accuracy to below 200nm (3 sigma).  This corresponds to up to a three-fold improvement over EVG’s widely adopted SmartView NT platform—the previous industry benchmark for bond aligners—and exceeds the latest ITRS Roadmap requirements, thereby filling a critical gap faced by device manufacturers that are considering adopting 3D-IC/TSV designs as part of their product roadmaps.  An integrated metrology module validates alignment after pre-bonding to enable customers to quickly fine-tune the bonding process for HVM processing if necessary.

Leveraging EVG’s XT Frame platform, which is utilized across the spectrum of the company’s industry-leading systems, the GEMINI FB XT is optimized for ultra-high throughput and productivity.  Additional pre- and post-processing modules have been added for wafer cleaning and surface preparation, plasma activation and wafer bond alignment that enable increases in throughput by up to 50 percent.  This significantly increased throughput combined with the tighter alignment specifications supports IC manufacturers’ efforts to move wafer stacking upstream in the manufacturing value chain from mid-end-of-line (MEOL) and back-end-of-line (BEOL) processing to front-end-of-line (FEOL) processing.  This, in turn, enables device manufacturers to integrate more functionality into their product at the wafer level, where higher levels of parallel processing can significantly drive down 3D-IC/TSV manufacturing costs.

“While EUV lithography continues to face delays, 3D-IC/TSV integration has emerged as one of the most promising approaches to extending Moore’s Law for future device generations.  Yet enabling 3D-IC/TSV integration for emerging memory and logic applications is impossible without the ability to achieve tight wafer-to-wafer alignment,” stated Paul Lindner, executive technology director at EV Group.  “EVG is continuing to drive improvements across our suite of solutions for 3D-IC/TSV applications to help bring our customers closer to the goal of commercializing 3D-IC technology.  Our new GEMINI FB XT platform marks a major milestone along that path, and we look forward to working with our customers to make the promise of 3D-IC high-volume manufacturing a reality for them.”

By Pushkar P. Apte

Research forms the DNA of the semiconductor industry — few other industries invest as much as a percentage of revenue.  Semiconductor research has always driven the Moore’s Law Mantra of continuously making things “cheaper, better, faster, and smaller.”  This brought the industry into the realm of nanotechnology, where manipulation of just a few atoms yields complex quantum effects.   This requires multi-faceted innovation — in materials, processing and characterization techniques, and advanced patterning to fabricate these tiny devices.  To explore the various dimensions of this innovation, SEMICON West 2014 features a session on “Breakthrough Research Technologies.”

Dr. Thorsten Lill from Lam Research, who will present at this session, explains, “As device dimensions and their allowed tolerances approach the same order of magnitude as inter-atomic distances, atomic scale processing will soon be a necessity. We will discuss the framework of developing production-worthy atomic layer etch (ALE) to achieve layer-by-layer removal with atomic fidelity.”   This is nanotechnology at its best — where we are engineering materials by each atomic layer.  Precision engineering also requires precision simulation and modeling, as Dr. Peter Ventzek of Tokyo Electron will describe for plasma chemistries used in etching and other processes.

We also need novel techniques to characterize materials at the atomic level.  Dr. John Mardinly of ASU, also presenting at this session, describes one such technique: “Aberration-Corrected Transmission Electron Microscopy provides numerous advantages over conventional Field-Emission Transmission Electron Microscopes. Resolution is improved by 2-3 times, and imaging and analysis can be conducted with lower accelerating voltages so that specimen damage is reduced.” In conventional bright field imaging, delocalization is eliminated so that interfaces between materials are imaged precisely. In Scanning Transmission Electron Microscopes, the beam current density can be 8-10 times higher than in a convention Field-Emission Scanning Transmission Electron Microscope. This dramatically improves the visibility of features and enables chemical mapping through Electron Energy Loss Spectroscopy (EELS) or Energy-dispersive X-ray Spectroscopy (EDS) with atomic resolution.

Aside from technology drivers, new market forces are now re-shaping the industry: the rise of the individual consumer as the dominant end-user; the application of technology to diverse fields such as energy, transportation and healthcare; and the rapid proliferation of the Internet of Things.  These entail complex functionality, which often requires complementing nanoscale digital devices with “More-than-Moore” functions like biological sensors, better analog and power devices other silicon.  Prof. Oliver Brand will describe research advances in the “More-than-Moore” areas of chemical microsensors, inertial sensors and micromachined ultrasonic transducers at the Center for Microelectromechanical Systems (MEMS) and Microsystem Technologies on the Georgia Tech campus.

This multi-dimensional, fast-paced research requires academia, research institutes, and the industry to work closely together, not just to push the research, but also to implement it in the “real world” successfully.  Prof. Douglas A. Keszler from OSU will describe how the Center for Sustainable Materials Chemistry focuses on breakthrough research to enable next-generation capabilities in semiconductor and display manufacturing, highlighting the technologies of spin-outs Inpria and Amorphyx.  Dr. Michael Khbeis of the Washington Nanofabrication Facility (WNF) at the University of Washington will describe advances in packaging/3D integration, silicon photonics, magnetic materials, superconductivity, photovoltaics, and quantum information systems.

It is exciting to imagine what capabilities such breakthrough research will enable in the future. From cramming more than a billion electronic transistors on a thumbnail, decoding the human genome, and placing a powerful computer in everyone’s pocket, how will technology change the world?  Besides richer computing, communications, and entertainment, we can now also tackle large and meaningful topical challenges, such as climate change, energy and water conservation, implementation of renewables, and affordable, effective healthcare.  Information Technology and the Internet of Things are already making a dent in these challenges and enabling research as discussed will accelerate this and help us improve our lives and our planet.

University and research institutions are increasingly important to help accelerate technology advances. Learn more about the latest — from speakers working in research at Arizona State University, Georgia Institute of Technology, Lam Research/KU Leuven/imec Joint Project, Oregon State University, TEL, U. of Washington — at the Breakthrough Research Technologies session at SEMICON West 2014.

By Shannon Davis, Web Editor

Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

Monday’s research and development panel discussion at The ConFab 2014 started on that optimistic note as Moderator Scott Jones of AlixPartners led a discussion on Optimizing R&D Collaboration. Panelists Chris Danely of JP Morgan, Lode Lauwers of imec, Rory McInerney of Intel and Mike Noonen of Silicon Catalyst discussed where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm. The panel also touched on the role startups will play and how increased collaboration can benefit the industry.

Here are highlights from Monday’s discussion.

How do you feel about the semiconductor cycle – is that at a positive point for innovation and small, start-up companies?

Mike Noonen: I feel the best about I’ve felt about semi since 2009. Without a doubt. When you combine that situation that we’re in with a couple driving forces, all of that has fundamental benefits to the semiconductor business at large. You take those mega trends that are not leading edge applications with the challenge of Moore’s Law – those are developing a whole host of innovation. We think this is a great time to think about how to reinvigorate startups – this is the best time to think about innovation.

From left to right: Panelists Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst, Lode Lauwers of imec, and Rory McInerney of Intel

From left to right: Panelists Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst, Lode Lauwers of imec, and Rory McInerney of Intel

Consolidation is a big theme right now. Is this something that’s holding us back the industry?

Rory McInerney: I don’t think the industry is consolidating for us as much as we think. The big players are still HP, Lenovo, etc. The new players are Google, Facebook, Amazon, etc. – many didn’t exist 10 years ago. Within our world, there’s the traditional space, but there’s a ton of new stuff in the cloud and server segment.

Tell us some of the most exciting areas Intel is participating in.

Rory McInerney: On the data center side, we do want our 10 and 7nm, but one of the drivers of our business is the massive amount of data being generated around the world. There are tens of billions of devices that will be connected to the Internet in the few years. The only commonality in the [IoT] numbers is that they go up. All of them will have some element of connectivity and with that comes data. And that drives a virtual cycle. In our business, we love this – my point is, there’s a huge room for innovation. The innovation isn’t just the device but the software and application side.

How do investors view the emerging markets and trends? Do they see the opportunities or are they still focusing on traditional markets?

Chris Danely: From a broad perspective, the thing that an analyst looks at – are they playing to their strengths? You might have a company that starts out very successful, but they don’t play to their strengths and start to waste money. For example, Texas Instruments has taken their R&D down, but still outgrow the industry, because they play to their strengths. Another example is Intel – in the last 3 years, they were in the foundry business – we see a lot of potential to upset the apple cart in the foundry business. Nobody else could do this, but this is an area where we see them exploiting their strengths. Is the company playing to its strengths? We also look at ARM on servers – we don’t know if this is going to work or not, but I don’t think this changing the landscape of the industry. There’s still a bright future with semiconductor stocks.

How can executives communicate their R&D strategy better?

Chris Danely: I’ll use my personal experience – you want to keep that message very simple. Identify the growth trends. Make sure the message goes out continuously. Don’t be afraid to use a few buzz words/charts.

Lode Lauwers: If I may, Wall Street is looking in the short term. Time scale [for R&D] is close to 15 years. I don’t know if Wall Street has that visibility. I think a company should consider R&D as a long term investment. We go for long term engagements.

Rory McInerney: It’s a portfolio question in terms of R&D – you’re going to have your short term and your long term investments. I don’t think Wall Street is looking at all the details of investments. I think that our investments on the product side go out 10 years, but they’re small compared to our other investments.

Chris Danely: Wall Street has to consider about things on a six month basis.

Mike Noonen: Biotech, which has a very long time to market, is the second largest venture capital in the US. Biotech has remained lucrative and interesting in the US. In this area, companies go after a single application or problem, and it’s a vibrant and healthy investment. The take away is – it’s all about the economics. It might enable small start ups to innovate and then be acquired.

How should the industry leverage a company like imec?

Lode Lauwers: More than ever, you need to build partnerships. In this industry, we used to say, “Our company can work on its own.” Now, your ecosystem needs to become wider. Ten years ago, people were still sponsoring R&D. Now we are assessed in every individual area, deliverable by deliverable, on does it benefit, is there ROI. You need to be able to deliver relevant work. A company on its own doesn’t always have these abilities in house. Using imec, it’s like building on competences.

Do you see differences in how you approach partnerships?

Chris Danely: The CEOs and CFOs of semi companies are under pressure to not increase expenses, and that’s stifled risk-taking. Some are now approaching R&D through acquisition of startups with personnel – rather than partnerships.

Do you think these companies are larger – semi is a part of a much larger landscape – do you think this might drive the industry/change the landscape?

Rory McInerney: About 70-80 percent of cloud computing today is driven by the social media. That didn’t exist 5 years ago. There is a direct link between that and the changing semi landscape.

What is the biggest risk in the industry right now?

Chris Danely: Saturation. Semi companies are profitable, but we’re starting to see a lot of them, especially as fablite and fabless models are catching on.

Moderator Scott Jones of AlixPartners

Moderator Scott Jones of AlixPartners

Root cause deconvolution is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone.

BY GEIR EIDE, Mentor Graphics, Wilsonville, OR

With 22nm FinFET-powered laptops now available and foundries announcing timelines for single-digit manufacturing nodes, it’s clear not everybody got the memo declaring Moore’s law dead and obsolete. While each new manufacturing node introduces new defect mechanisms, one notable trend is the dramatic increase in number and complexity of design-sensitive defects. This means that in addition to the low yield seen initially as a new manufacturing process is introduced, variability from design to design makes yield a continuing challenge even as the process matures.

The obvious question to ask when you stare at a pile of failing devices is: Why are these devices failing? The pile can represent a number of different defect mechanisms (or root causes). Some may be familiar, while others are new. Some may be easy to find, while others are virtually invisible. Physical failure analysis (PFA) is used to find defects in failing devices, but this is a very costly and time consuming process. Determining what to submit to PFA is therefore a balancing act between controlling expense and finding the relevant defect. Wouldn’t it be great if you could determine the underlying root causes early, and pick the die for PFA that represents the causes of interest in an effective and low cost manner? This is the promise of a new scan test diagnosis technology called root cause deconvolution.

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

Software-based diagnosis of test failures is an established method for localizing defects in digital semiconductor devices. Diagnosis software determines the defect type and location for each failing device based on the design description, scan test patterns, and tester fail data. But diagnosis results contain ambiguity or noise. The diagnosis result for one specific die may point to more than one possible location. Each location may in turn have multiple properties or root causes. For example, the suspect location can span multiple layers (metal3, via4, metal4) while the true root cause is an open defect in just one of these layers. You may observe that many diagnosis results call out net segments that include a particular via type. What you cannot see from the diagnosis results alone is whether that is to be expected or not, i.e. whether this is a common via type or not. This means that plain diagnosis results cannot be used to determine the underlying root cause distribution. Similarly, you may see more bridges in metal3 than metal4, not knowing whether that is to be expected or if it points to a systematic defect. A method called zonal analysis manages this noise by finding relative differences in the diagnosis reports. This method is most effective for identifying hidden systematic defects at fairly high yields, such as the last 1%-2% in high volume manufacturing [1].

But until now there has not been a way to effectively eliminate the noise in the diagnosis results and determine the underlying root causes represented in a population of failing devices. The new root cause deconvolution (RCD) technology is based on Bayesian probability analysis, which is well-known in machine learning applications. It leverages design statistics such as critical area per net segment per metal layer and count of tested cells per cell type. The technology uses a probabilistic model that calculates the proba- bility of observing a set of diagnosis results for a given defect distribution. This model is then used to determine the most likely defect distribution for a given set of diagnosis results.

A typical application of RCD is shown in FIGURE 1. For one wafer, the failing cycles are recorded for devices that failed scan test patterns, and then layout- aware diagnosis is performed (1). RCD analysis is done on the diagnosis results, identifying the under- lying root cause distribution (2). This result can then be compared with equivalent distributions from the same design or comparable designs. Having this data available before any devices are submitted to PFA significantly accelerates the analysis time. You can then select the root cause of interest, in this case the most significant contributor. The RCD analysis will then identify the die that have the largest probability of failing because of this defect mechanism. Before submitting a die to PFA (4), you know where to look for the defect, and also what to look for.

In a comprehensive experiment [3], RCD results for four lots of failing devices correlated to the conclusions reached through inline inspection, failure analysis, and known process changes. RCD is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone. This provides significant value to the yield and failure analysis process at fabless semiconductor companies.

References

1. W. Yang, C. Hao, “Diagnosis-Driven Yield Analysis Improves Mature Yield”, Chip Design Magazine, Fall 2011.

2. M. Sharma, et.al., “Efficiently Performing Yield En- hancements by Identifying Dominant Physical Root Cause from Test Fail Data”, IEEE International Test Conference, 2008

3. B. Benware, et.al., “Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results”, IEEE D&T of Computers, Volume 29, Issue 1.

Ultrathin glass is well suited for use as interposers in semiconductor packaging applications.

BY JUILA GOLDSTEIN, Senior Associate Analyst, NanoMarkets, Glen Allen, VA

Flexible glass seemed like a natural fit for the display industry, combining the impermeability of glass with the flexibility of plastic. In 2012 it appeared as though flexible and ultrathin glass companies were going to benefit from the explosion of touchscreens in displays of all sizes, but the market made an abrupt turnaround. Now suppliers of ultrathin and flexible glass are looking for applications beyond displays to bring in revenue in the next few years, and one of the places they are looking is in semiconductor packaging.

For those who approach flexible glass from the point of view of a display, an application where the glass is hidden between layers of silicon and other materials may not seem to make a lot of sense. As far as NanoMarkets can tell, no one really thought about semiconductor packaging as a use for flexible glass until the display application began to fail. The flexible glass sector itself was firmly focused on displays until then and the semiconductor packaging sector had probably never considered flexible glass as an option.

Nonetheless, using ultrathin glass in semiconductor packaging may actually be a very good idea, even though its optical properties and flexibility may be irrelevant in this application.

The Role of glass in interposers

For many years the semiconductor packaging industry has been developing packages that are smaller, thinner, and lighter than what has come before. Ultrathin glass, 30 to 100 μm, may be able to further progress toward this goal.

The target application is 2.5D or 3D multi-chip or chip scale packages (CSP), where semiconductor chips are placed in close proximity or stacked on top of each other to provide a space-saving configuration. Such packages traditionally use a layer of thinned silicon as an interposer to connect chips to each other and to the underlying organic substrate. Silicon has the advantage of being a familiar material with a well-established infrastructure in the semiconductor packaging industry, but it does have some drawbacks, the major one being cost.

FIGURE 1. A 30 μm thick flexible glass interposer made by Schott Glass.

FIGURE 1. A 30 μm thick flexible glass interposer made by Schott Glass.

Glass may be preferable to silicon as an interposer because it is a less expensive material, it can be provided in thin sheets (silicon has to be ground and polished to the proper thickness) and it is thermally insulating. Silicon is a semicon- ductor, not an electrical insulator, which can cause problems with crosstalk between chips. FIGURE 1 shows a 30 μm thick flexible glass interposer made by Schott Glass.

Silicon conducts heat better than glass, making the semiconductor industry a bit suspicious of the ability of glass to conduct heat sufficiently to avoid hot spots in sensitive ICs. The answer is in the through-glass vias (TGV), channels drilled through the interposer that are filled with metal (usually copper) and form electrical connections between the chip and the organic substrate. Solid filled vias act like heat pipes to provide a path for heat conduction.

The potential cost advantages of glass can best be achieved using large sheets of glass, thus allowing facilities to process more units in parallel than is possible with silicon wafers. The largest possible cost savings of using flexible glass is realized if it can be integrated into a roll- to-roll production process. Several suppliers are producing flexible glass on rolls, but the semiconductor industry is not necessarily prepared to process it.

Re-evaluating the supply chain

While glass may be a compelling interposer material from the point of view of glass makers, lack of infra- structure in this application is a real problem. In order for glass to be useful as an interposer, someone needs to drill vias through the glass and metallize them, and it is not yet clear who that would be. Several industries could participate in the supply chain, but there are barriers in all cases:

  • Semiconductor packaging houses: The industry is not used to working with glass and is not inclined to do so. It is very resistant to change and may be especially averse to implementing R2R processing. Convincing semiconductor packaging facilities to process glass will clearly be an uphill battle.
  • Flat-panel display manufacturers: These companies have experience with glass but have not historically had anything to do with semiconductor packaging. It may be possible to build awareness in this sector, but the flat panel display industry prefers to sell large pieces of glass.
  • Printed circuit board manufacturers: The PCB industry currently makes organic interposers, geared toward applica- tions where fine pitch is not required. Glass suppliers might be able to work with the PCB industry, which is used to large panels, if they want to supply sheets of glass. It still may be difficult, however, to implement very thin glass using this approach. It also will probably be difficult to integrate TGV production into a PCB-like process flow.

Organizations that are promoting ultrathin glass interposers are attempting to address the infrastructure challenge:

  • Georgia Tech: The Packaging Resource Center at Georgia Tech has been working with industry partners on glass interposers since 2010 and has moved from initial trials with 180-μm thick glass down to the thinnest products that today’s glass suppliers are producing. The PRC is working with major glass suppliers such as Corning and Schott, who are interested in flexible glass interposers.

The PRC has been working on transferring the technology from prototype to low volume, and perhaps eventually high volume, commercial production. It has made some real progress in developing the technology and moving proto- typing from labs into industry, but admits that the greatest challenge in moving forward is lack of infrastructure to support the transition.

nMode solutions that is partially funded by Asahi Glass Company, is providing some missing segments in the supply chain. Triton has developed a production process to create through glass vias (TGVs) that is sufficient for today’s 2.5D applications and it is making interposers for MEMS, RF, and optics at its manufacturing facility in Carlsbad, CA. According to Triton, the major advantage it provides over silicon is the ability to produce solid filled, hermetic TGVs.

Existing commercial products use glass interposers from Triton, but this is much thicker glass, typically 0.3mm or greater. The glass is cut into wafers, matching the form factor of silicon but not requiring backgrinding. This provides the convenience of a process that fits easily into existing manufacturing lines but doesn’t take advantage of glass’ potential to provide thinner interposers at much lower cost than silicon. Triton can make large panels of 0.1-mm glass with TGVs, but customers do not know how to handle it and may not be inclined to learn.

NanoMarkets understands the potential advantage thin glass would have as an interposer, but is not especially optimistic about its future, especially in the near term. It seems very unlikely that flexible glass will be able to generate large revenues in this space, even if penetration rates get large. Each product uses a very small amount of glass compared to what would be needed for even a smart phone display.

The semiconductor packaging industry may be an even more difficult environment for introducing new processes than the display industry, and we know flexible glass has had challenges there. Still, we feel this sector is worth keeping an eye on to see if glass has an opportunity to succeed where silicon has not.

Storing gas on a sorbent provides an innovative, yet simple and lasting solution.

BY KARL OLANDER, Ph.D. and ANTHONY AVILA, ATMI, Inc., an Entegris company, Billerica, MA

The period following the introduction of subatmospheric pressure gas storage and delivery was punctuated by continuous technical innovation.

Even as the methodology became the standard for supplying ion implant dopants, it continued to rapidly evolve and improve. This article reflects on the milestones of the last 20 years and considers where this technology goes from here.

From the beginning, the semiconductor industry’s concern over using highly toxic process gases was evident by the large investment being made in dedicated gas rooms, robust ventilation systems, scrubbers, gas containment protocols and toxic gas monitoring. While major advances have been made in the form of automated gas cabinets and valve manifold boxes, gas line components, improved cylinder valves and safety training, the underlying threat of a catastrophic gas release remained.

Risk factors targeted

The underlying risk with compressed gases is twofold: high pressure, which provides the motive force to discharge the contents of a cylinder, and secondly, a relatively large hazardous production material inventory, which can be released during a containment breach. Pressure also is a factor in component failure and gas reactivity, e.g., corrosion. Mitigating these issues would considerably increase safety.

FIGURE 1. The stages of developing a new chemical precursor for use in commercial IC production.

FIGURE 1. The stages of developing a new chemical precursor for use in commercial IC production.

Analysis of the risks suggested an on-demand, point-of-use gas generator would improve safety by both reducing operating pressure and gas inventory[1]. The challenges associated with this approach include complexity of operation and gas purity, especially in a fab or process tool setting. Chemical generation of arsine, while possible, per equation [A], also substituted a highly reactive toxic solid for arsine[2]. Considerable safety and environmental issues accompanied the operation of such a generator. An on-demand, point-of-use electrochemical approach for supplying arsine, per equation [B], would also eliminate the need for high pressure storage if the associated operational issues could be overcome. Numerous attempts at developing a commercial electrochemical generator just never proved successful[3].

[A] KAsH2 + H2O —> AsH3/H2O + KOH
[B] As(s) + 3H2O + 3e(-) —> AsH3(g) + 3OH(-)

Innovation from a simple(r) solution

Pressure swing adsorption processes utilize the selective affinity between gases and solid adsorbents, and are widely used to recover and purify a range of gases. Under optimal conditions, the gas adsorption process releases energy and produces a material that behaves mores like a solid than a gas.

Early work at reversibly adsorbing toxic materials on a highly porous substrate showed promise. In 1988, the Olin Corporation described an arsine storage and delivery system where the gas was [reversibly] adsorbed onto a zeolite, or microporous alumino- silicate, material[4]. A portion of the stored gas could be recovered by heating the storage vessel to develop sufficient arsine pressure to supply a process tool. In 1992, ATMI supplied a prototype system based on the Olin technology to the Naval Research Lab in Washington, D.C.

The breakthrough that lead to the first commercial subatmospheric pressure gas storage and delivery system occurred when ATMI reported the majority of the adsorbed gas could be supplied to the process by subjecting the storage vessel to a strong vacuum. Using vacuum rather than thermal energy simplified the process, providing the means for an on-demand system[5]. Using a sorbent had the effect of turning the gas into something more akin to a “solid.” That characteristic, coupled with the absence of a pressure driver, delivered an inherently safe condition. The vacuum delivery condition also helped define where the technology would find its first application: ion implantation[6].

Safe and efficient gas storage and delivery

In 1993, prototype arsine storage and delivery cylinders based on vacuum delivery were beta tested at AT&T in Allentown, PA[g] [f]. The system was trademarked Safe Delivery Source®, or SDS®. Papers were presented on safe storage and delivery of ion implant dopant gases the following year in Catania, Sicily at the International Ion Implant Technology Conference[7].

The goal to find a safer method to offset the use of compressed gases was realized: (1) gas is stored at low pressure (ca. 650 Torr at 21°C) and (2) the potential for large and rapid gas loss is averted. Leaks, if they occur, whether by accidental valve opening or a containment breach, would be first inward into the cylinder. Once the pressure equalizes, gas loss to the environment would be governed mainly by diffusion as the gas molecules remain associated with the sorbent. The SDS package, while not a gas generator per se, effectively functions like one.

FIGURE 2. Cutaway view of SDS3 carbon pucks within a finished cylinder.

FIGURE 2. Cutaway view of SDS3 carbon pucks within a finished cylinder.

While subatmospheric pressure operation is an artifact of having to “pull the gas” away from the sorbent, it has become synonymous with safe gas delivery. The optimization work which followed focused on reducing pressure drop in the gas delivery system by improving conductance in valves, mass flow controllers and delivery lines. A restrictive flow orifice was no longer required. The new gas sources proved to work best when in close proximity to the tool.

The years after this technology introduction also saw considerable efforts to improve the sorbent; ultra-pure carbon replaced the zeolite-based material used in the first generation SDS (SDS1), roughly doubling the deliverable quantities of gas per cylinder. These granular carbon sorbents in the SDS2 were later replaced by solid, round monolithic carbon “pucks” in SDS3 (FIGURE 2), which necessitated the cylinder be built around the sorbent[8]. This improvement again roughly doubled gas cylinder capacity.

Recognized in international standards

In 2012, the United Nations (U.N.) recognized the uniqueness of adsorbed gases and amended the Model Regulation for the Transport of Dangerous Goods by creating a new “condition of transport” for gases adsorbed on a solid and assigning a total of 17 new identification numbers and shipping names to the Dangerous Good List. Adoption is expected to occur by 2015. A few of the additions are noted here.

Arsine   – UN 2188 – compressed
Arsine, adsorbed – UN 3522 – SDS
Phosphine – UN 2199 – compressed
Phosphine, adsorbed – UN 3525 – SDS

FIGURE 3. The evolution of a SAGS Type 1 gas package.

FIGURE 3. The evolution of a SAGS Type 1 gas package.

In recent years, fire codes have been updated through the definition and classification of subatmospheric Gas Systems, or SAGS, based on the internal [storage] pressure of the gas.9 Systems based on both sub-atmospheric pressure storage and delivery are designated as Type 1 SAGS. It is important to note that the UN definition for adsorbed gases, and the resulting new classifications mentioned above, only applies to Type 1 SAGS, defined as follows:

3.3.28.5.1 Subatmospheric Gas Storage and Delivery System (Type 1 SAGS). A gas source package that stores and delivers gas at sub-atmospheric pressure and includes a container (e.g., gas cylinder and outlet valve) that stores and delivers gas at a pressure of less than 14.7 psia at NTP.

It is also worth mentioning that sub-atmospheric pressure gas delivery can also be achieved using high pressure cylinders by embedding a pressure reduction and control system. The Type 2 SAGS typically employs a normally closed, internal regulator[s] that a vacuum condition to open. This is not a definition of sub-atmospheric storage and delivery, but of sub-atmospheric delivery only.

3.3.28.5.2 Subatmospheric Gas Delivery System (Type 2 SAGS). A gas source package that stores compressed gas and delivers gas subatmospherically and includes a container (e.g., gas cylinder and outlet valve) that stores gas at a pressure greater than 14.7 psia at NTP and delivers gas at a pressure of less than 14.7 psia at NTP.

In general, Environmental Safety and Health managers, risk underwriters and authorities having jurisdiction recognize the importance of SAGS and requires recommend their use whenever process conditions allow[10].

Expanding SAGS into new applications

Taking the lessons learned from SDS2/SDS3 in ion implant operations, along with key findings from
other applications like HDP-CVD (the SAGE package) and combined with sorbent purification and carbon nanopore size tuning, SAGS Type 1 packages are poised to offer their safety advantages in new and emerging areas, as well as add even more safety and efficiency benefits. Currently, a new package called Plasma Delivery SourceTM (PDSTM) is available for high flow rate applications, while maintaining all the safety attributes of the SAGS Type 1 package.

Also, in addition to the inherent safety, PDS employs a pneumatic operator (valve) to the cylinder which further minimizes the opportunity for human error. In an emergency, such as a toxic gas alarm, pressure excursion, loss of exhaust, etc., gas flow at the source can be quickly stopped and the cylinder isolated. Cycle/purge operations are made safer as human involvement is minimized. Human-initiated events, like over-torqueing the valve, failing to close the valve or even back-filling a cylinder with purge gas, are prevented.

SDS1 SDS2 SDS3
Arsine 200 559 835
Phosphine 85 198 385

Expanding the use of SAGS beyond the domain of ion implant involves successfully navigating key process factors such as operating pressure, flow rates, proximity to the tool and purity. One approach includes coupling the PDS cylinder and gas cabinet together to yield a plug and play “smart” delivery system. Unlike high pressure systems, which are more concerned with excess flow situations, knowing and controlling pressure allows a SAGS cabinet to operate at a reduced risk. This enables linking cabinet ventilation rates with the system operating pressure. During normal operating conditions, the exhaust rate could be reduced by up to 80 percent because the system is operating sub-atmospherically. Should the operating pressure exceed a preset threshold, the exhaust flow would automatically revert to a higher range or the cylinder valve would close.

The future, therefore, could see these PDS packages extended to another level by incorporating them into smart delivery systems, which will further reduce risk, maximize efficiency, improve cost of ownership and expand the footprint for SAGS into new applications like plasma doping, solar, epitaxy and etch.

Summary

During the last 20 years, the semiconductor industry undertook a large effort to develop safer gas delivery technologies to reduce risks associated with dopants used in ion implant. Many technologies were considered, including chemical and electrochemical gas generators, complexing gases with ionic liquids or mechanically controlling cylinder discharge pressure using embedded regulator devices.

In the end, storing gas on a sorbent provided an innovative, yet simple and lasting solution. Gas-sorbent interactions are well understood, reproducible and can be achieved with a minimum of moving parts. Gas release risks, driven by pressure, are all but removed from consideration. And any potential for human error continues to be a target for improvement wherever toxic gases are used.

References

1. Proc. Natl. Acad. Sci. USA 89 pp 821-826, 1992.
2. Appl. Phys. Lett., 60 1483
3. Electron Transfer Technology, US Patent 59225232
4. Olin Corporation, US Patent US4744221A
5. Advanced Technology Materials, US Patent US5518528 6. Many thanks to Dan McKee and Lee Van Horn for being the first of many early adopters.
7. Proceedings of the Tenth International Conference on Ion Implantation Technology, 1994, pp 523-526.
8. DOT-SP 13220.
9. NFPA 318, Standard for the Protection of Semiconductor Fabrication Facilities 2012 Edition. 10. SAGS in the FAB, SST reference

ATMI is a wholly owned subsidiary of Entegris, Inc. ATMI, Safe Delivery Source, SDS, Plasma Delivery Source and PDS are trademarks of Entegris, Inc. in the U.S., other countries, or both. All other names are trademarks of their respective companies.

A UC Riverside-led research project is among the 32 named today by U.S. Energy Secretary Ernest Moniz as an Energy Frontier Research Centers (EFRCs), designed to accelerate the scientific breakthroughs needed to build a new 21st-century energy economy in the United States. “Spins and Heat in Nanoscale Electronic Systems” (SHINES) will receive $12 million over four years from the Department of Energy. The lead researcher is UC Riverside Professor of Physics Jing Shi, who will work with researchers from seven universities.

SHINES is one of 10 new projects announced today, along with 22 other projects receiving new funding based on achievements to date. The Department of Energy announced a total of $100 million in funding to support fundamental advances in energy production, storage, and use.

“Today we are mobilizing some of our most talented scientists to join forces and pursue the discoveries and breakthroughs that will lay the foundation for our nation’s energy future,” Secretary Moniz said. “The funding we’re announcing today will help fuel innovation.”

He said the intent of the Energy Frontier Research Centers is to make fundamental advances in solar energy, electrical energy storage, carbon capture and sequestration, materials and chemistry by design, biosciences, and extreme environments.

“I am happy to hear the news,” said Shi, the UCR physics professor who has put together an interdisciplinary team of  researchers from UC Riverside, UCLA, Johns Hopkins, Arizona State University, University of Texas, Austin and Colorado  State University, Fort Collins.

“I’m looking forward to seeing the scientific advances that they come up with,” said Michael Pazzani, UC Riverside’s Vice Chancellor for Research and Economic Development. “This is exactly the kind of scientific leadership that UC Riverside has been encouraging and supporting This project will lay the groundwork for energy technology for the nation.”

SHINES will investigate several aspects of basic research: new ultrathin films, nanostructured composites, high resolution imaging, the transport of electrical signals, heat and light. “All of it will be studied, modeled and simulated in order to help the nation’s ability to advance in the way we use energy,” said Shi, the lead researcher.