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Trapping light with an optical version of a whispering gallery, researchers at the National Institute of Standards and Technology (NIST) have developed a nanoscale coating for solar cells that enables them to absorb about 20 percent more sunlight than uncoated devices. The coating, applied with a technique that could be incorporated into manufacturing, opens a new path for developing low-cost, high-efficiency solar cells with abundant, renewable and environmentally friendly materials.

This is illustration shows the nanoresonator coating, consisting of thousands of tiny glass beads, deposited on solar cells. The coating enhances both the absorption of sunlight and the amount of current produced by the solar cells. Credit: K. Dill, D. Ha, G. Holland/NIST

This is illustration shows the nanoresonator coating, consisting of thousands of tiny glass beads, deposited on solar cells. The coating enhances both the absorption of sunlight and the amount of current produced by the solar cells. Credit: K. Dill, D. Ha, G. Holland/NIST

The coating consists of thousands of tiny glass beads, only about one-hundredth the width of a human hair. When sunlight hits the coating, the light waves are steered around the nanoscale bead, similar to the way sound waves travel around a curved wall such as the dome in St. Paul’s Cathedral in London. At such curved structures, known as acoustic whispering galleries, a person standing near one part of the wall easily hears a faint sound originating at any other part of the wall.

Whispering galleries for light were developed about a decade ago, but researchers have only recently explored their use in solar-cell coatings. In the experimental set up devised by a team including Dongheon Ha of NIST and the University of Maryland’s NanoCenter, the light captured by the nanoresonator coating eventually leaks out and is absorbed by an underlying solar cell made of gallium arsenide.

Using a laser as a light source to excite individual nanoresonators in the coating, the team found that the coated solar cells absorbed, on average, 20 percent more visible light than bare cells. The measurements also revealed that the coated cells produced about 20 percent more current.

The study is the first to demonstrate the efficiency of the coatings using precision nanoscale measurements, said Ha. “Although calculations had suggested the coatings would enhance the solar cells, we could not prove this was the case until we had developed the nanoscale measurement technologies that were needed,” he noted.

This work was described in a recent issue of Nanotechnology by Ha, collaborator Yohan Yoon of NIST and Maryland’s NanoCenter, and NIST physicist Nikolai Zhitenev.

The team also devised a rapid, less-costly method of applying the nanoresonator coating. Researchers had previously coated semiconductor material by dipping it in a tub of the nanoresonator solution. The dipping method takes time and coats both sides of the semiconductor even though only one side requires the treatment.

In the team’s method, droplets of the nanoresonator solution are placed on just one side of the solar cell. A wire-wound metal rod is then pulled across the cell, spreading out the solution and forming a coating made of closely packed nanoresonators. This is the first time that researchers have applied the rod method, used for more than a century to coat material in a factory setting, to a gallium arsenide solar cell.

“This is an inexpensive process and is compatible with mass production,” said Ha.

 

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has released two new MOSFETs “TPHR7904PB” and “TPH1R104PB” housed in the small low-resistance SOP Advance (WF) package, as new additions to the automotive 40V N-channel power MOSFET series. Mass production starts today.

Fabricated using the latest ninth generation trench U-MOS IX-H process and housed in a small low-resistance package, the new MOSFETs provide low on-resistance and thus help reduce conduction loss. The U-MOS IX-H design also lowers switching noise compared with Toshiba’s previous design (U-MOS IV), helping to reduce EMI (Electromagnetic Interference).

The SOP Advance (WF) package adopts a wettable flank terminal structure, which enables AOI (Automated Optical Inspection) after soldering.

Applications

  • Electric power steering (EPS)
  • Load switches
  • Electric pumps

Features

  • Provides a maximum on-resistance, RDS(ON)max, of 0.79 mΩ from the use of the U-MOS IX-H process and the SOP Advance(WF) package.
  • Low-noise characteristics reduce electromagnetic interference (EMI).
  • Available in a small low-resistance package with a wettable flank terminal structure.

Main Specifications

(Unless otherwise specified, @Ta=25°C)

Part Number

Drain-Source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)

Drain-Source
on-resistance

RDS(ON) max.(mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series

@VGS=6V

@VGS=10V
TPH1R104PB 40 120 1.96 1.14 No U-MOS IX
TPHR7904PB 150 1.3 0.79 No U-MOS IX

ON Semiconductor (Nasdaq: ON) has introduced the industry’s first 1/1.7-inch 2.1 megapixel CMOS image sensor featuring ON Semiconductor’s newly developed 4.2μm Back Side Illuminated (BSI) pixels – the AR0221 delivers class-leading low light sensitivity for industrial applications.

The AR0221 offers exceptional 3-exposure line-interleaved High Dynamic Range (HDR) with a sensor resolution of 1936H x 1096V, supporting frame rates of 1080p at 30 fps and an outstanding Signal-Noise Ratio (SNR) across visible and near-infrared wavelengths. Its 16:9 ratio with vivid colors and high contrast make it ideal for demanding industrial applications.

Gianluca Colli, Vice President and General Manager, Consumer Solution Division of Image Sensor Group at ON Semiconductor, said: “The AR0221 represents the industry’s best CMOS image sensor in this class, thanks to its outstanding low light sensitivity and SNR performance. By including features like windowing, auto black level correction and an onboard temperature sensor, ON Semiconductor has produced an image sensor that will enable a new generation of security and surveillance cameras.”

The sensor offers dual data interfaces in the form of 4-lane MIPI CSI-2 and HiSPi SLVS. Designed to meet industrial-grade specifications, the AR0221 can operate in harsh outdoor environments where operating temperatures can range between -30°C and +85°C. Packaged in a durable, reliable and robust iBGA package with anti-reflection coating on its cover glass, the AR0221 is programmable through a simple two-wire serial interface.

When power generators like windmills and solar panels transfer electricity to homes, businesses and the power grid, they lose almost 10 percent of the generated power. To address this problem, scientists are researching new diamond semiconductor circuits to make power conversion systems more efficient.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

A team of researchers from Japan successfully fabricated a key circuit in power conversion systems using hydrogenated diamond (H-diamond.) Furthermore, they demonstrated that it functions at temperatures as high as 300 degrees Celsius. These circuits can be used in diamond-based electronic devices that are smaller, lighter and more efficient than silicon-based devices. The researchers report their findings this week in Applied Physics Letters, from AIP Publishing.

Silicon’s material properties make it a poor choice for circuits in high-power, high-temperature and high-frequency electronic devices. “For the high-power generators, diamond is more suitable for fabricating power conversion systems with a small size and low power loss,” said Jiangwei Liu, a researcher at Japan’s National Institute for Materials Science and a co-author on the paper.

In the current study, researchers tested an H-diamond NOR logic circuit’s stability at high temperatures. This type of circuit, used in computers, gives an output only when both inputs are zero. The circuit consisted of two metal-oxide-semiconductor field-effect transistors (MOSFETs), which are used in many electronic devices, and in digital integrated circuits, like microprocessors. In 2013, Liu and his colleagues were the first to report fabricating an E-mode H-diamond MOSFET.

When the researchers heated the circuit to 300 degrees Celsius, it functioned correctly, but failed at 400 degrees. They suspect that the higher temperature caused the MOSFETs to breakdown. Higher temperatures may be achievable however, as another group reported successful operation of a similar H-diamond MOSFET at 400 degrees Celsius. For comparison, the maximum operation temperature for silicon-based electronic devices is about 150 degrees.

In the future, the researchers plan to improve the circuit’s stability at high temperatures by altering the oxide insulators and modifying the fabrication process. They hope to construct H-diamond MOSFET logic circuits that can operate above 500 degrees Celsius and at 2.0 kilovolts.

“Diamond is one of the candidate semiconductor materials for next-generation electronics, specifically for improving energy savings,” said Yasuo Koide, a director at the National Institute for Materials Science and co-author on the paper. “Of course, in order to achieve industrialization, it is essential to develop inch-sized single-crystal diamond wafers and other diamond-based integrated circuits.”

The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

Plastics are excellent insulators, meaning they can efficiently trap heat – a quality that can be an advantage in something like a coffee cup sleeve. But this insulating property is less desirable in products such as plastic casings for laptops and mobile phones, which can overheat, in part because the coverings trap the heat that the devices produce.

Now a team of engineers at MIT has developed a polymer thermal conductor — a plastic material that, however counterintuitively, works as a heat conductor, dissipating heat rather than insulating it. The new polymers, which are lightweight and flexible, can conduct 10 times as much heat as most commercially used polymers.

Researchers at MIT have designed a new way to engineer a polymer structure at the molecular level, via chemical vapor deposition. This allows for rigid, ordered chains, versus the messy, 'spaghetti-like strands' that normally make up a polymer. This chain-like structure enables heat transport both along and across chains. Credit: MIT News Office / Chelsea Turner

Researchers at MIT have designed a new way to engineer a polymer structure at the molecular level, via chemical vapor deposition. This allows for rigid, ordered chains, versus the messy, ‘spaghetti-like strands’ that normally make up a polymer. This chain-like structure enables heat transport both along and across chains. Credit: MIT News Office / Chelsea Turner

“Traditional polymers are both electrically and thermally insulating. The discovery and development of electrically conductive polymers has led to novel electronic applications such as flexible displays and wearable biosensors,” says Yanfei Xu, a postdoc in MIT’s Department of Mechanical Engineering. “Our polymer can thermally conduct and remove heat much more efficiently. We believe polymers could be made into next-generation heat conductors for advanced thermal management applications, such as a self-cooling alternative to existing electronics casings.”

Xu and a team of postdocs, graduate students, and faculty, have published their results today in Science Advances. The team includes Xiaoxue Wang, who contributed equally to the research with Xu, along with Jiawei Zhou, Bai Song, Elizabeth Lee, and Samuel Huberman; Zhang Jiang, physicist at Argonne National Laboratory; Karen Gleason, associate provost of MIT and the Alexander I. Michael Kasser Professor of Chemical Engineering; and Gang Chen, head of MIT’s Department of Mechanical Engineering and the Carl Richard Soderberg Professor of Power Engineering.

Stretching spaghetti

If you were to zoom in on the microstructure of an average polymer, it wouldn’t be difficult to see why the material traps heat so easily. At the microscopic level, polymers are made from long chains of monomers, or molecular units, linked end to end. These chains are often tangled in a spaghetti-like ball. Heat carriers have a hard time moving through this disorderly mess and tend to get trapped within the polymeric snarls and knots.

And yet, researchers have attempted to turn these natural thermal insulators into conductors. For electronics, polymers would offer a unique combination of properties, as they are lightweight, flexible, and chemically inert. Polymers are also electrically insulating, meaning they do not conduct electricity, and can therefore be used to prevent devices such as laptops and mobile phones from short-circuiting in their users’ hands.

Several groups have engineered polymer conductors in recent years, including Chen’s group, which in 2010 invented a method to create “ultradrawn nanofibers” from a standard sample of polyethylene. The technique stretched the messy, disordered polymers into ultrathin, ordered chains — much like untangling a string of holiday lights. Chen found that the resulting chains enabled heat to skip easily along and through the material, and that the polymer conducted 300 times as much heat compared with ordinary plastics.

But the insulator-turned-conductor could only dissipate heat in one direction, along the length of each polymer chain. Heat couldn’t travel between polymer chains, due to weak Van der Waals forces — a phenomenon that essentially attracts two or more molecules close to each other. Xu wondered whether a polymer material could be made to scatter heat away, in all directions.

Xu conceived of the current study as an attempt to engineer polymers with high thermal conductivity, by simultaneously engineering intramolecular and intermolecular forces — a method that she hoped would enable efficient heat transport along and between polymer chains.

The team ultimately produced a heat-conducting polymer known as polythiophene, a type of conjugated polymer that is commonly used in many electronic devices.

Hints of heat in all directions

Xu, Chen, and members of Chen’s lab teamed up with Gleason and her lab members to develop a new way to engineer a polymer conductor using oxidative chemical vapor deposition (oCVD), whereby two vapors are directed into a chamber and onto a substrate, where they interact and form a film. “Our reaction was able to create rigid chains of polymers, rather than the twisted, spaghetti-like strands in normal polymers.” Xu says.

In this case, Wang flowed the oxidant into a chamber, along with a vapor of monomers – individual molecular units that, when oxidized, form into the chains known as polymers.

“We grew the polymers on silicon/glass substrates, onto which the oxidant and monomers are adsorbed and reacted, leveraging the unique self-templated growth mechanism of CVD technology,” Wang says.

Wang produced relatively large-scale samples, each measuring 2 square centimeters – about the size of a thumbprint.

“Because this sample is used so ubiquitously, as in solar cells, organic field-effect transistors, and organic light-emitting diodes, if this material can be made to be thermally conductive, it can dissipate heat in all organic electronics,” Xu says.

The team measured each sample’s thermal conductivity using time-domain thermal reflectance — a technique in which they shoot a laser onto the material to heat up its surface and then monitor the drop in its surface temperature by measuring the material’s reflectance as the heat spreads into the material.

“The temporal profile of the decay of surface temperature is related to the speed of heat spreading, from which we were able to compute the thermal conductivity,” Zhou says.

On average, the polymer samples were able to conduct heat at about 2 watts per meter per kelvin – about 10 times faster than what conventional polymers can achieve. At Argonne National Laboratory, Jiang and Xu found that polymer samples appeared nearly isotropic, or uniform. This suggests that the material’s properties, such as its thermal conductivity, should also be nearly uniform. Following this reasoning, the team predicted that the material should conduct heat equally well in all directions, increasing its heat-dissipating potential.

Going forward, the team will continue exploring the fundamental physics behind polymer conductivity, as well as ways to enable the material to be used in electronics and other products, such as casings for batteries, and films for printed circuit boards.

“We can directly and conformally coat this material onto silicon wafers and different electronic devices” Xu says. “If we can understand how thermal transport [works] in these disordered structures, maybe we can also push for higher thermal conductivity. Then we can help to resolve this widespread overheating problem, and provide better thermal management.”

BY GUIDO GROESENEKEN, imec fellow

To be able to guarantee the reliability of transistors, we have been conducting research for some years now at imec to see what happens when transistors operate properly and when they fail. We’ve been doing this in terms of circuits, devices and materials – and sometimes right down to the level of atoms. The insights that we gather from this work help us to provide the right feedback to the process technol- ogists, who in turn are able to make the transistors more reliable. It is particularly interesting to note that in recent years the knowledge we have gained about these failure mechanisms can also be applied to other areas. These insights no longer only serve to solve problems, but are the basis for innovative and surprising solutions in very diverse domains.
Last year, imec spent a lot of time working on self- learning chips, data security codes, FinFET biosensors and computer systems that can correct themselves. These are innovations that draw on the knowledge present in imec’s reliability group.

Self-learning chips

For example, take the self-learning or neuromorphic chip that gave imec such extensive coverage in the media in 2017. The development of this chip is based, among other things, on our knowledge of “resistive RAM” or RRAM memories, which use the breakdown of an oxide to switch a memory bit on or off (0 or 1). This oxide breakdown – which was previously (and still is) a reliability problem – occurs because a conductive path is created through the oxide, known as a filament. However, the work conducted by imec’s reliability group has demonstrated that not only can you create a filament or make it disappear, but that there are intermediate levels as well, which means that the strength of the filament can be controlled. And that is precisely what happens in our brains: the connec- tions between neurons can become stronger or weaker according to the occurrence they are processing or the learning process they use, etc. This means that these RRAM filaments can be used in chips that work like our brains. It was this insight that provided us with the foundation for the development of imec’s neuromorphic chip, which – as has been demonstrated – can even compose music.

Data security

Since recently we are also working closely with COSIC, an imec research group at KU Leuven that specializes in computer security and cryptography. Also here we can draw on our knowledge of transistor breakdown mechanisms. These can be used to create and read out a fingerprint that is unique for each chip and that cannot be predicted, hence the name ‘physically unclonable functions’ (or PUFs). This unique fingerprint makes it possible to ascertain the identity of chips in data exchanges and thus to prevent hacking by means of rogue chips.

The phenomenon of ‘Random Telegraph Noise’, which has long been known in the area of transistor reliability, could also be used as a security fingerprint. Random telegraph noise is a name for sudden jumps in voltage or current levels as the result of the random trapping of charges in traps within the gate insulation of a transistor. This phenomenon is unpredictable and random, and hence it could also be perfectly usable as PUF. What was once a problem for us – the breakdown of oxides or the existence of random telegraph noise – is now at the base of major new solutions for computer security.

Biosensors

A third example of discipline-overlapping innovation brings us to the world of life sciences. FinFET transistors are essential for the current and future generations of computer chips. As a result of the research carried out in our group, we have now found out a great deal about the way the work, including their failure mechanisms, etc. So much so that we can now explore the possibility to use them as biosensors. What happens is that biomolecules have a certain charge and when that charge comes into the vicinity of a FinFET, the current in the FinFET will be influ- enced. As a result, there is the potential that the presence of a single biomolecule can be detected by such a FinFET.

Self-healing chips

And, finally, we are also working with system architects to produce reliable chips, even with transistors that are no longer reliable. Extremely small transistors with dimen- sions smaller than 5 nanometers can be very variable and the way they behave is unpredictable. For that reason we are working with system architects on solutions such as self- healing chips, based among other things on the existing models of the failure mechanisms that we provide them with. These self-healing chips will contain monitors that detect local errors. A smart controller then interprets this information and decides how to solve the problem, after which actuators are directed by the controller to carry out the task required.

What about scaling?

Numerous methods are currently being investigated to ensure that transistors can still be miniaturized and improved for as long as possible, as propounded in Moore’s Law. To do so, the classic transistor architecture has already been replaced by a FinFET architecture and in the future this will evolve even to nanosheets or nanowires. Materials other than silicon, with greater mobility, are also being looked at, such as III-V materials (germanium for pMOS and InGaAs for nMOS).

In the choice made for these future architecture, it is extremely important to also look right from the start to the failure mechanisms and reliability of the new solutions.

As an example, last year, our reliability team focused extensively on III-V transistors. Although these transistors score well in terms of mobility, their stability is still one of the main challenges remaining before we are able to take the next step and start manufacturing. The insulation layers in III-V transistors contain a lot of traps that cause this insta- bility in transistor characteristics. Understanding this phenomenon is essential if we are to find a solution for it. So, a breakthrough in this area is needed urgently and our results, which were published in a recent IEDM paper, are certainly a step in the right direction. In the invited paper by Jacopo Franco these instabilities are first analyzed in detail. Then, based on this analysis, practical guidelines are given for the development of III-V gate stacks that offer sufficient reliability.

It’s very difficult to look ahead even further into the future, because as the end of Moore’s Law approaches, increasing numbers of different technologies and concepts are already on the radar (quantum computers, 2D materials, neuro- morphic computers, spinwave logic, etc.). However, none of these concepts has yet made a real breakthrough. But in my view 2017 was the year in which the industry began to take a strong interest in quantum computers, with major investments from important players such as Google and Intel. Imec also plans to play a major role in this field, with the launch of a new program on quantum computing, gathering the extensive expertise available. In the past, quantum computing has been considered more as a purely academic field of research – something of value for physi- cists at universities, but not for engineers and companies. So perhaps the breakthrough of industrial quantum computing will be the next milestone in the history of electronics. Or perhaps this milestone will come from a totally unexpected angle – by combining knowledge and people from entirely different disciplines, creating totally new ideas and concepts. Only the future will tell us!

People are growing increasingly dependent on their mobile phones, tablets and other portable devices that help them navigate daily life. But these gadgets are prone to failure, often caused by small defects in their complex electronics, which can result from regular use. Now, a paper in today’s Nature Electronics details an innovation from researchers at the Advanced Science Research Center (ASRC) at The Graduate Center of The City University of New York that provides robust protection against circuitry damage that affects signal transmission.

The breakthrough was made in the lab of Andrea Alù, director of the ASRC’s Photonics Initiative. Alù and his colleagues from The City College of New York, University of Texas at Austin and Tel Aviv University were inspired by the seminal work of three British researchers who won the 2016 Noble Prize in Physics for their work, which teased out that particular properties of matter (such as electrical conductivity) can be preserved in certain materials despite continuous changes in the matter’s form or shape. This concept is associated with topology–a branch of mathematics that studies the properties of space that are preserved under continuous deformations.

“In the past few years there has been a strong interest in translating this concept of matter topology from material science to light propagation,” said Alù. “We achieved two goals with this project: First, we showed that we can use the science of topology to facilitate robust electromagnetic-wave propagation in electronics and circuit components. Second, we showed that the inherent robustness associated with these topological phenomena can be self-induced by the signal traveling in the circuit, and that we can achieve this robustness using suitably tailored nonlinearities in circuit arrays.”

To achieve their goals, the team used nonlinear resonators to mold a band-diagram of the circuit array. The array was designed so that a change in signal intensity could induce a change in the band diagram’s topology. For low signal intensities, the electronic circuit was designed to support a trivial topology, and therefore provide no protection from defects. In this case, as defects were introduced into the array, the signal transmission and the functionality of the circuit were negatively affected.

As the voltage was increased beyond a specific threshold, however, the band-diagram’s topology was automatically modified, and the signal transmission was not impeded by arbitrary defects introduced across the circuit array. This provided direct evidence of a topological transition in the circuitry that translated into a self-induced robustness against defects and disorder.

“As soon as we applied the higher-voltage signal, the system reconfigured itself, inducing a topology that propagated across the entire chain of resonators allowing the signal to transmit without any problem,” said A. Khanikaev, professor at The City College of New York and co-author in the study. “Because the system is nonlinear, it’s able to undergo an unusual transition that makes signal transmission robust even when there are defects or damage to the circuitry.”

“These ideas open up exciting opportunities for inherently robust electronics and show how complex concepts in mathematics, like the one of topology, can have real-life impact on common electronic devices,” said Yakir Hadad, lead author and former postdoc in Alù’s group, currently a professor at Tel-Aviv University, Israel. “Similar ideas can be applied to nonlinear optical circuits and extended to two and three-dimensional nonlinear metamaterials.”

Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with Samsung Foundry to develop DesignWare Foundation IP for Samsung’s 8 nanometer (nm) Low Power Plus (8LPP) FinFET process technology. Providing DesignWare Logic Library and Embedded Memory IP on Samsung’s latest process technology enables designers to take advantage of a reduction in power and area compared to Samsung’s 10LPP process. The DesignWare Foundation IP will be developed to meet strict automotive-grade requirements, enabling designers to accelerate ISO 26262 and AEC-Q100 qualifications of their advanced driver assistance system (ADAS) and infotainment system-on-chips (SoCs). The DesignWare Logic Library and Embedded Memory IP will be available from Synopsys through the Foundry-Sponsored IP Program for the Samsung 8LPP process, enabling qualified customers to license the IP at no cost. The collaboration extends Synopsys’ and Samsung’s long history of working together to provide silicon-proven IP that helps designers meet their performance, power, and area requirements for a wide range of applications including mobile, automotive, and cloud computing.

“Samsung’s collaboration with Synopsys over the last decade has enabled first-pass silicon success for billions of ICs in mobile and consumer applications,” said Jongwook Kye, vice president of Design Enablement at Samsung Electronics. “As designs get more complex and migrate to smaller FinFET processes, Samsung’s advanced 8LPP process with Synopsys’ high-quality Foundation IP solutions will enable designers to differentiate their products for mobile, cryptocurrency and network/server applications, accelerate project schedules, and quickly ramp into volume production.”

“Samsung and Synopsys share a long and successful history of providing designers with silicon-proven DesignWare IP on Samsung’s processes ranging from 180 to 10 nanometer,” said John Koeter, vice president of marketing for IP at Synopsys. “As the leading provider of physical IP with more than 100 test chip tapeouts on FinFET processes, Synopsys continues to make significant investments in developing IP to help designers take advantage of Samsung’s latest process technologies, reduce risk and speed development of their SoCs.”

Solar cells have great potential as a source of clean electrical energy, but so far they have not been cheap, light, and flexible enough for widespread use. Now a team of researchers led by Tandon Associate Professor André D. Taylor of the Chemical and Biomolecular Engineering Department has found an innovative and promising way to improve solar cells and make their use in many applications more likely.

Most organic solar cells use fullerenes, spherical molecules of carbon. The problem, explains Taylor, is that fullerenes are expensive and don’t absorb enough light. Over the last 10 years he has made significant progress in improving organic solar cells, and he has recently focused on using non-fullerenes, which until now have been inefficient. However, he says, “the non-fullerenes are improving enough to give fullerenes a run for their money.”

Think of a solar cell as a sandwich, Taylor says. The “meat” or active layer – made of electron donors and acceptors – is in the middle, absorbing sunlight and transforming it into electricity (electrons and holes), while the “bread,” or outside layers, consist of electrodes that transport that electricity. His team’s goal was to have the cell absorb light across as large a spectrum as possible using a variety of materials, yet at the same time allow these materials to work together well. “My group works on key parts of the ‘sandwich,’ such as the electron and hole transporting layers of the ‘bread,’ while other groups may work only on the ‘meat’ or interlayer materials. The question is: How do you get them to play together? The right blend of these disparate materials is extremely difficult to achieve.”

Using a squaraine molecule in a new way – as a crystallizing agent – did the trick. “We added a small molecule that functions as an electron donor by itself and enhances the absorption of the active layer,” Taylor explains. “By adding this small molecule, it facilitates the orientation of the donor-acceptor polymer (called PBDB-T) with the non-fullerene acceptor, ITIC, in a favorable arrangement.”

This solar architecture also uses another design mechanism that the Taylor group pioneered known as a FRET-based solar cell. FRET, or Förster resonance energy transfer, is an energy transfer mechanism first observed in photosynthesis, by which plants use sunlight. Using a new polymer and non-fullerene blend with squaraine, the team converted more than 10 percent of solar energy into power. Just a few years ago this was considered too lofty a goal for single-junction polymer solar cells. “There are now newer polymer non-fullerene systems that can perform above 13 percent, so we view our contribution as a viable strategy for improving these systems,” Taylor says.

The organic solar cells developed by his team are flexible and could one day be used in applications supporting electric vehicles, wearable electronics, or backpacks to charge cell phones. Eventually, they could contribute significantly to the supply of electric power. “We expect that this crystallizing-agent method will attract attention from chemists and materials scientists affiliated with organic electronics,” says Yifan Zheng, Taylor’s former research student and lead author of the article about the work in the journal Materials Today.

Next for the research team? They are working on a type of solar cell called a perovskite as well as continuing to improve non-fullerene organic solar cells.