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Industry enters the age of WOW

December 13, 2017

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI, Milpitas, California

The semiconductor industry has been there before, with large increases in investments followed by dramatic downturns. While the most dramatic downturns, 2001 and 2009, were due to, in a large part, acro-economic factors, the industry has typically observed one to two years of increased investment spending followed by a down period. This time around, the industry will achieve a “WOW” with three consecutive years of fab investment growth, a pattern not observed since the mid-1990s.

Why are things different this time? A diverse array of technology drivers promise more robust long-term growth, such as Mobile applications, Internet of Things (IoT), Automotive & Robotics, Industrial, Augmented Reality & Virtual Reality (AR&VR), Artificial Intelligence (AI), and 5G networking. Each of these new technologies inspires a big “WOW” as the industry embarks on the beginning of a promising journey of growth.

Driven by these technologies, on average the semiconductor revenue CAGR from 2016 to 2021 is forecasted to be 6 percent (in comparison to the previous 2011-2016 CAGR of 2.3 percent). For the first time in the industry’s history, semiconductor revenues will exceed the US$400 billion revenue milestone in 2017. Demand for chips is high, pricing is strong for memory, and the competition is fierce. All of this is spurring increased fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See Figure 1.

Figure 1

The World Fab Forecast report, published on December 4, 2017, by SEMI, is modeling that fab equipment spending in 2017 will total US$57 billion or 41 percent year-over-year (YoY) growth. In 2018, spending is expected to shoot up another 11 percent at US$63 billion. The two spending jumps in 2017 and 2018 are contributing to the “WOW” factor and to two consecutive years of record fab investments. Following historic large investments, some slowdown is expected for 2019.

Many companies, such as Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES, have increased fab investments in 2017 and 2018; however, the strong increases we see in both years are not caused by these companies but by one company and primarily one region. See Figure 2.

Figure 2

The first jump – a Big WOW – in 2017 is the surge of investments in Korea, due mainly to Samsung. Samsung is expected to increase its fab equipment spending by 128 percent in 2017 from US$8 billion to US$18 billion. No single company has invested so much in a single year in its fabs and much of its spending is in Korea. SK Hynix also increased fab equipment spending, by about 70 percent, to US$5.5 billion, its largest spending level in its history. While the bulk of Samsung’s and SK Hynix’s spending remains in Korea, some will also go to China, and in the case of Samsung to the United States. Both Samsung and SK Hynix are expected to maintain high levels of investments for 2018.

The second jump – another WOW – is investment growth for 2018 in China. China is expected to begin equipping the many fabs that were constructed in 2017. In the past, non-Chinese companies made the majority of the fab investments in China but for the first time in 2018, Chinese-owned companies will approach parity, spending nearly as much on fab equipment as non-Chinese device manufacturers.

Between 2013 and 2017, fab equipment spending in China by Chinese-owned companies typically ranged between US$1.5 billion to US$2.5 Billion per year, while non-Chinese companies invested between US$2.5 billion to US$5 billion per year. In 2018, Chinese-owned companies are expected to invest about US$5.8 billion, while non-Chinese will invest US$6.7 billion. Many new companies such as Yangtze Memory Technology, Fujian Jin Hua, Hua Li, and Hefei Chang Xin Memory are investing heavily in the region.

New fabs being built

Historic highs in equipment spending in 2017 and 2018 reflect growing demand. This spending follows unprecedented growth in construction spending for new fabs also detailed in SEMI’s World Fab Forecast report. Construction spending will reach all-time highs with China construction spending taking the lead: US$6 billion in 2017 and US$6.6 billion in 2018, shattering another record – no region has ever spent more than US$6 billion in a single year for construction. More new fabs mean another wave of spending on equipping fabs in the next few years. See Figure 3.

Figure 3

Considering all of these “WOW” factors, there is good reason to feel positive about the semiconductor industry. Even with a slowdown, the industry has and will continue to enjoy a positive outlook for long-term growth. In the meantime, hold on tight and enjoy the “WOW.”

More details are available in SEMI’s just-published World Fab Forecast, December 4, 2017, edition which covers quarterly data (spending, capacity, technology nodes, wafer sizes, and product types) per fab until end of 2018.

4Q DRAM sales put exclamation point on an amazing year of growth

December 13, 2017

Throughout 2017, DRAM manufacturers faced pressure to boost output of their devices—particularly high-performance DRAM used in data center servers, and low-power high-density DRAM used in smartphones and other mobile products. Strong, ongoing demand put significant upward pressure on DRAM average selling prices. This trend continued into 4Q17 and is expected to drive quarterly DRAM sales to an all time high mark of $21.1 billion (Figure 1), capping an incredible year of growth in which DRAM sales set a new all time high sales mark each quarter. The forecast $21.1 billion sales level in 4Q17 would be an increase of 65% compared to the $12.8 billion DRAM market of 4Q16.

Figure 1

Annual DRAM market growth of 74% is forecast for 2017, which would be the highest growth rate since the 78% increase in 1994—23 years ago—and 61 points more than the 13% average DRAM market growth rate from 1993-2017 (Figure 2). The expected 74% DRAM market growth in 2017 will mark the fourth time since 1993 that the DRAM market has increased by more than 50%. This near-historic high market spike in 2017 was brought on by several factors, including constrained supply attributed to a lack of major fab expansion plans, yield difficulties with leading-edge (≤20nm) processes, demand for high performance (graphics) DRAM from gaming systems and data center-based server applications, and increased average content for mobile DRAM used in smartphones.

Figure 2

There is an increasing need for high-speed but inexpensive data storage in smartphone handsets for multi-tasking, which is boosting the average DRAM content in a smartphone. The Apple iPhone 8 features 2GB of DRAM and the iPhone X has 3GB of DRAM. The Samsung Galaxy S8 is sold with 4GB of DRAM (6GB in China). Huawei’s P10 Plus, and HTC’s U11 come with 6GB of DRAM. The One Plus 5 model and the first smartphone from Razer, a Singapore-based company that is primarily known for its video game equipment, have 8GB of DRAM.

With virtual and augmented reality and artificial intelligence becoming prominent features on new smartphones and apps, DRAM content in high-end smartphones shows no signs of slowing. Meanwhile, DRAM growth for smartphones is also stemming from less developed countries, where much of the population is moving from feature phones to their first smartphone—literally transitioning from zero to 1GB of mobile DRAM.

Based on historical trends, the DRAM industry will likely experience a decline (possibly a big market decline) in its growth rate in the not-too-distant future as prices begin to tumble with significant capacity additions and an increase in DRAM output expected over the next year or two. Announcements by Samsung and SK Hynix in the second half of 2017 confirmed that new DRAM capacity is set to come online in 2018, which likely will ease the upward trend of DRAM ASPs next year. Samsung has stated its semiconductor capital expenditure budget for 2017 will be an enormous $26.0 billion, and SK Hynix has announced plans to build a new manufacturing line at its massive facility in Wuxi, China. Micron has gone on record as saying it doubts that it will ever need to build another new DRAM fab, but it is hard to imagine that Micron will sit still as its two fiercest rivals capture additional marketshare. (For the record, Micron and Intel are developing Crosspoint memory as a potential replacement for DRAM).

3D acoustic images expand their usefulness

December 7, 2017

BY TOM ADAMS, Sonoscan, Inc., Elk Grove Village, IL

Three-dimensional acoustic images, like three-dimensional light images, differ from their two-dimensional counterparts by displaying the z dimension in addition to x and y dimensions. The first 3D acoustic images were made around by 20 years ago at Sonoscan, who invented the technique. The technology can display the surface topography of a sample, or its internal profile at a desired depth.

The C-SAM® acoustic micro imaging tools that make the 3D images have a transducer that pulses ultrasound at a given frequency at or into the sample thousands of times a second as the transducer scans back and forth above the surface of the sample. A pulse of ultrasound leaving the transducer travels first through a water couplant, supplied constantly by a water jet attached to the transducer. Every time ultrasound exits one material/fluid and enters another, some of the ultra- sound is reflected to the transducer; as a result, a portion of the pulse is reflected by the water-to-sample surface interface. The rest of the pulse crosses the surface interface and travels deeper into the sample.

In most acoustic imaging, the concern is with the amplitude of the returned echoes from the interior of the sample. A well bonded interface between silicon and epoxy will reflect a small amount of the pulse. The amount of ultrasound reflected causes a specific amplitude in the return echo. The echo amplitude is measured and then displayed in the acoustic image by an assigned color value for that amplitude. The highest amplitude echoes essentially indicate 100% reflection and are produced only by the interface between a solid and a gas. All gap-type defects meet this definition.

By measuring the amplitude of the reflected signal and identifying those having near-total reflection, an acoustic micro imaging (AMI) tool can detect voids, cracks, non-bonds and other gap-type anomalies that threaten the longevity of a part.

3D imaging, however, cares about the position in time of a reflection from a given plane such as the surface of the sample. By measuring the distance, in time, from the end of the transducer to the front surface, AMI can assign a color value to each location in time that the front surface occurs. In this way a color represen- tation of the topography is made. Plastic BGA packages, for example, are notorious for having internal defects that disturb the flatness of the package’s surface. By assigning a color to each height variation, the locations of surface disturbances are easily detected. The same method can be used to image unpopulated printed circuit boards to ensure that they are flat enough to avoid placing stress on connections. Samples imaged in 3D are viewed at an angle from the vertical perspective in order to make local height differences visible.

Recently the method has been used in a different role – measuring the height, before substrate attachment, of the solder bumps on BGAs. A precise vertical range is set – in acoustic terms, a gate. If the tops of all the solder bumps fall within the small vertical range defined by the gate, successful bonding of all bumps to the substrate is more likely.

The basics of imaging rounded bumps are essentially the same as for imaging flat surfaces. The sides of the bump may send back little or no signal, but in this investigation, they are not the area of interest. The color of the top of the bump is what matters, because it indicates whether the top lies within the narrow vertical range for successful bonding. Interpretation of the image is simplified by software that stretches the image of each solder bump vertically. If the solder bumps were imaged in their actual height, the gate in which the top should lie would be tiny and hard to see. Stretching each bump vertically does not change the measurement, it simply makes the results easier to interpret.

FIGURE 1 shows an acoustic side view image of a solder bump in its unstretched form, and the stretched form of its acoustic image. (Acoustic side views of internal features can be made by Sonoscan’s Q-BAMTM imaging mode, designed for non-destructive cross sectioning.) Even after the image is stretched, it may represent a vertical extent of only several microns. If bumps were imaged without vertical exaggeration, distinguishing accept from reject might be very difficult or even impossible. The amount of stretching needed for the bumps on a particular part type of BGAs, and the vertical extent of the gate that will yield the best results can typically be determined from previous experience with a BGA. Overall, what matters is not the precise configuration of the gate but ensuring that all bumps are very close to each other in height.

FIGURE 2 is the stretched 3D image of the solder bumps on one BGA before placement onto a PCB. The desired condition is that the top surface of the bump lie within the thin horizontal slice colored green in the image. FIGURE 3 is a magnified view of a small section of Fig. 2.

All the bumps in this BGA have tops that lie within the vertical “green” gate. There are no bumps toppled by other colors, a condition that would reveal that the bump might not bond to the substrate as well. The black areas in the figure are locations where no bump is present. BGAs like this are loaded into JEDEC-style trays and imaged in large quantities. Identification and removal of BGAs having one or more unsuitable bumps can be automated. The failure criteria are completely customizable depending on the level of tolerance a particular sample is held to.

FIGURE 4 is a small portion of the 3D image of a BGA where results were not quite so uniform. The desired color for the top of each bump here is red. As shown red is the top color on many of the bumps, especially in the left half of the image. But elsewhere there are bumps with pink, orange and other top colors. This is a BGA that may not make good contact with the PCB. Further down the assembly line this sample would likely experience immediate or early electrical failures due to attachment issues.

Location information can become useful to large scale production companies that are trying to understand their process better. If there are trends that suggest a specific location on the BGA is having a bump height problem, then there maybe something related to the process, handling, or materials being used that could be causing the issue. The measurement can be taken simultaneously while scanning in standard reflection mode. There is no addition in scan time or reduction in UPH to make this measurement.

3D imaging can also be used to depict strictly internal features. The operator sets two vertical values – an internal gate – to define the top and bottom of the desired depth measurement. This mode is known as profile mode imaging. When imaging in profile mode, only the echoes that occur within the depth of the gate are used for imaging. Signals outside of the gate are ignored. Because this is 3D imaging inside the part, the variation is measured relative to the top surface of the part.

3D acoustic imaging is useful for measuring the heights of bumps on BGAs, flip chips, and other devices. But it can also be used to image and quantify depth/ height variation of features within a particular sample. Measuring the distance of each of the thousands of x-y locations across the entire top surface of a tilted die can reveal how much of a threat to longevity the tilt is. It may even be helpful to stretch the image vertically to make so that the tilt could be easily seen to the human eye. Depending on the gate and depth chosen for a given profile mode image, it is possible to discern defects that occur at different height locations. This can be useful by showing that two similar looking defects may not be occurring at the exact same depth within the part. For example, you may have a void within the molding compound just a few microns before the lead frame. In standard reflection mode imaging, it would be impossible to determine if the defect occurred just before the lead (inclusion within the mold compound) or if the defect was a result of poor bonding directly to the lead frame. The is because standard reflection mode imaging only measures the amplitude of a given echo and not its location in time. Using profile mode, the depth location information is displayed using a color bar to depict the height infor- mation. In this way, defects that occur at different heights will also be assigned a different color value. This is the value of 3D acoustic imaging: mapping Time-Distance relationships at the surface or inter- nally for a given sample in a manner that is useful and easy to interpret.

Solutions for controlling resin bleed out

December 5, 2017

The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

BY RONGWEI ZHANG, ABRAM CASTRO and YONG LIN, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Die attach pastes, which consist of resin, curing agent, catalyst, filler and additives, have been extensively used to attach die onto lead frames in various electronic packages such as small outline integrated circuit (SOIC), thin-shrink small outline package (TSSOP), quad flat package (QFP) and quad-flat no-lead (QFN). One of the issues commonly encountered during package assembly is resin bleed-out (RBO), or epoxy bleed out (EBO). RBO is the separation of some formulation ingredients in the paste from the bulk paste (see FIGURE 1). Depending on die attach paste formulations and lead frame surface chemistry and morphology, bleeding ingredients can be solvents, reactive diluents, low-molecular-weight resins, catalysts, and additives like adhesion promoter. Resin bleed out tends to occur on high energy surfaces such as metal lead frames without any organic coating. In particular, if plasma cleaning is utilized to remove the contaminants prior to assembly, the bleeding issue may become more pronounced due to the increase in surface energy. Bleed-out can occur once die attach pastes are dispensed on to lead frames or during thermal curing. As microelectronics continue to move towards smaller form factor, higher reliability and higher performance, control of RBO becomes increasingly critical for packages where there is a very little clearance between die and die pad edge, or between one die and another in multi-chip modules (MCMs).

How resin bleed-out occurs

When die attach paste is dispensed onto a solid surface like lead frame surface, the paste will typically wet the surface partially. The adhesive force between die attach paste and lead frame surface causes the paste to spread while the cohesive force within the bulk paste will hold the ingredients together and avoid contact with a lead frame surface. The adhesive and cohesive forces are the intermolecular forces such as hydrogen bonding and Van der Waals forces. So the degree of wetting will depend on the balance between adhesive force and cohesive force. Bleed-out occurs when the adhesive force of some formulation ingredients to the substrate is stronger than the cohesive force within the paste. The driving force for bleed out is to minimize the surface energy of the substrate by wetting.

Impact of resin bleed-out

Resin bleed-out can cause several issues if it is not well controlled.

• If the formulation ingredients bleed from the periphery of the die attach pastes and covers the wire bonding area, then issues like non-stick on pad (NSOP) and weak wire bond can occur. It can also be an issue if bleeding occurs from the die attach fillet along die edge to the die top, contaminating the bond pad on die top surface [1].

• Resin bleed-out may affect the adhesion of mold compound to die pad or mold compound to die top surface, both of which can lead to delamination. In particular, die top delamination is strictly not allowed in wire-bonded packages because it can cause the ball bond to be mechanically lifted, thereby leading to electrical failures during temperature cycling [2].

• As the formulation ingredients bleed out of the bulk paste, the composition of die attach paste under die may change accordingly. This can impact the adhesion of die attach to lead frame adversely, leading to an adhesive failure [3].

Influence of surface roughness

There are many factors that can cause resin bleed-out, such as low surface tension of die attach pastes, high surface energy of metal lead frames, surface contami- nation, surface porosity and surface roughness. Here we will focus on the impact of surface roughness, which is critical to achieve high package reliability. Two die attach pastes were dispensed onto three lead frames with different surface roughness. The surface roughness of these three lead frames was characterized by Atomic Force Microscopy (AFM) using the roughness average (Ra) and the roughness ratio (r) (FIGURE 2). The roughness average (Ra) represents the arithmetic average of the deviations from the center plane. The roughness ratio is the ratio between the actual 3-D surface area calculated by AFM and the flat surface. The 3D morphologies of lead frames are shown in FIGURE 3. It was found that (a) there is a good correlation between the roughness ratio and resin bleed-out. As the surface roughness ratio increases, the bleeding becomes increasingly worse; (b) LF1 and LF2 have almost same Ra, but the bleeding performance of DA3 and DA4 are different. This indicates that the roughness average is not a good index for RBO; (c) DA4 is more resistant to bleed out than DA3.

The relationship between surface roughness and the wettability has been described by Young equation (Equ. 1) and Wenzel equation (Equ. 2).

cos0y=(YS-YSL)/YL (1)0
cosöm=rcos0y (2)

Where Ys, YL, YSL are surface tensions of the solid, liquid and interfacial tension between die attach paste and lead frame, respectively; 0y is the Young contact angle, 0m is the measured contact angle, and r is the roughness ratio. As the surface roughness increases, the better the wetting, and the worse the bleed-out if the contact angle is < 90o [4]. This is the case for die attach paste on a metal surface without anti-EBO coating.

Approaches to control resin bleed out

There are several approaches to control or eliminate resin bleed-out. These approaches include modifying formulation by selecting appropriate anti-EBO, using die attach film (DAF)/B-stage epoxy, controlling surface roughness, creating mechanical barrier, and lowering the surface energy of lead frames by surface coating.

• Modifying formulations. Generally, anti-bleeding agents are added to die attach pastes to reduce or eliminate RBO. Different anti-bleeding agents may have different working mechanisms. Some anti- bleeding agents are added to enhance the cohesiveness of the pastes while others are added to form a thin layer with a surface energy lower than the pastes themselves on a lead frame surface [5]. Therefore, tailoring die attach adhesives with appropriate anti-bleeding agents is critical to prevent RBO on different types of lead frames, while maintaining high adhesion to metal lead frames to achieve high reliability.

• Die Attach Film/B-stage Epoxy. The simplest and most effective way to eliminate RBO is to use die attach films or B-stage materials. However, there are limitations associated with this approach. These can include high material cost and capital investment, difficulty to achieve high adhesion and thus high reliability, and limited thermal performance of these materials.

• Mechanical barriers. In some cases, grooves on lead frames are designed in between die attach area and wire bond area to reduce resin bleed-out, as shown in FIGURE 4. This is a simple and cost-effective process. However, this approach may not work well if the bleeding is severe. Similarly, some low surface energy insulating film around a chip can be printed to confine the un-cure pastes to the space defined by the printed pattern [5].

• Vacuum baking. Vacuum baking of ceramic substrates with gold or other metal surfaces has been reported to reduce bleed-out. Several mechanisms were proposed: (a) through removal of polar surface contaminant, which promotes bleed-out of lighter organic resin by dipole attraction or chemical reaction [6]; (b) through reducing the surface energy of the plating surface by the formation of Ni2O3 [7]; (c) through producing a coating of hydrocarbon by oil back streaming toreduce the surface energy [8]. The method is not recommended either due to lack of controllability or due to the detrimental effect on wire bonding quality [7]. A more controlled method to reduce or eliminate RBO is to treat the surface with known chemicals and controlled processes, as discussed below.

• Low surface energy coating. Roughened lead frames have been utilized to enhance package reliability, particularly to meet Automotive Grade 0 requirements or beyond, as they increase surface contact area and enhance mechanical interlocking. As shown in Fig. 2, a small increase in roughness can result in a severe bleed-out. Therefore, increasing surface roughness will promote bleed-out if there is no anti-EBO on the surface. According to Young’s equation, decreasing surface energy will increase the contact angle, i.e. decreasing the wetting of the surface. Therefore, in roughened lead frame manufacturing, a solution of low surface energy material is used to treat roughened lead frames to lower their surface energy to reduce or eliminate RBO. Alternatively, a thin layer of film can be deposited onto the assembly surface by gas plasma technology to modify the surface energy [9]. FIGURE 5 shows water contact angles of lead frames with or without anti-EBO treatment. The anti-EBO coating will increase the contact angle on standard lead frame as explained by Young’s equation. Compared with standard lead frames, roughened lead frames have an increasing roughness and the anti-EBO coating on roughened lead frames further increases contact angle significantly. This can be explained by Wenzel equation, which demonstrates that adding surface roughness will increase surface hydrophobicity if the surface is chemically hydrophobic. In addition, Fig. 5 shows the resin bleed-out performances of a die attach paste (DA2) on these three types of lead frames. Bleed out was observed on the standard lead frame without anti-EBO, but there was no bleeding on both standard and roughened lead frame with anti-EBO coating. The low surface energy anti-EBO coating eliminates resin bleed out.

Summary

This article provides an understanding of how bleeding occurs, the impact of bleeding, and methods to control bleeding. Bleeding is the result of the interaction between die attach pastes and metal lead frames. In particular, we studied the influence of surface roughness on RBO of different die attach materials, and found that there is a good correlation between the roughness ratio and bleed-out performance. Reducing the surface roughness will reduce or eliminate RBO. It is noteworthy that there is a line between reducing roughness to achieve no RBO and increasing roughness to ensure excellent delamination performance for lead frames without Anti-EBO. In terms of die attach pastes, the most effective way to control RBO seems to be the surface coating with anti-RBO without affecting other performances like delamination, or combining this method with others to provide an even better solution.

References

1. B. Neff, J. Huneke, M. Nguyen, P. Liu, T. Herrington, S. K. Gupta, “No bleed die attach adhesives”, IEEE International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005, pp. 1-3.
2. R. W. Zhang, Y. Lin, A. Castro, “Solving delamination in lead frame- based packages”, Chip scale review, 2015, pp. 44-48.
3. S. Kanagavel, D. Hart, “Optimization of die attach to surface-enhanced lead frames for MSL-1 performance of QFN packages”, Chip scale review, 2017, pp. 35-38.
4. J.-C. Hsiung, R.A. Pearson, T.B. Lloyd, “A surface energy approach for analyzing die attach adhesive resin bleed,” J. of Adhesion Science and Technology, 2003, 17, No. 1, pp. 1-13.
5. H. Schonhorn, L. H. Sharpe, “Liquids with reduced spreading tendency”, US Patent 4,483,898.
6. J. Ireland, “Epoxy bleedout in ceramic chip carriers”, Int. J Hybrid Microelectron., 1982, 5, pp. 1-4.
7. M. R. Marks, J. A. Thompson, R. Gopalakrishnan, “An experimental study of die attach polymer bleedout in ceramic packages”, Thin Solid Film, 1994, 252, pp. 54-60.
8. N. Tan, K. H. H. Lim, B. Chin, A. J. Bourdillon, “Engineering surface in ceramic pin grid array packaging to inhibit epoxy bleeding”, The Hewlett-Packard Journal, 1998, pp. 81-89.
9. M. Burmeister, “Elimination of epoxy resin bleed through thin film plasma deposition”, Proceeding of the 36th international IMAPS conference, Boston, MA, 2003, pp. 780-785.

Reveal previously invisible defects and contaminants in advanced packaging applications

December 5, 2017

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

Clearfind^TM technology

The results presented here were all acquired using a Firefly^TM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology¹. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars². TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer³. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

Semiconductor industry continues upward trend toward record year

November 30, 2017

The semiconductor industry continued its upward trend in the third quarter of 2017, notching 12 percent sequential growth with strength across all application markets, according to IHS Markit (Nasdaq: INFO). Global revenue totaled $113.9 billion, up from $101.7 billion in the second quarter of 2017.

As memory prices remain high and the wireless market continues to see strong demand through the fourth quarter, 2017 is shaping up to be a record-breaking year for the semiconductor industry. IHS Markit projects that semiconductor revenue will reach a record-high $428.9 billion in 2017, representing a year-over-year growth rate of 21 percent.

Key growth drivers

All application end markets posted sequential growth over the prior quarter, with wireless communications and data processing categories leading the pack.

Revenue from wireless applications grew faster sequentially in the third quarter of 2017 than any of the other high-level application markets. Semiconductor revenue from wireless applications was a record high $34.8 billion in the third quarter, representing nearly 31 percent of the total semiconductor market. IHS Markit anticipates an even bigger fourth quarter for wireless applications, projecting $37.5 billion in revenue — and more than $131 billion for the full-year 2017.

As the wireless market evolves, this growth can be attributed to a number of factors. ”More complex and comprehensive smartphone systems on a chip are supporting applications such as augmented reality and computational photography,” said Brad Shaffer, senior analyst for wireless semiconductors and applications at IHS Markit. “Premium smartphones have increasing amounts of memory and storage. The radio frequency content in these smartphones has also grown considerably over the past few product generations, with many high-end smartphones now supporting gigabit LTE mobile broadband speeds.”

The memory markets proved once again to be the driving force and highest-growing segment for semiconductors in the third quarter of 2017. “The DRAM industry had another record quarter with $19.8 billion in revenue, exceeding the prior record by more than $3 billion,” said Mike Howard, director for DRAM memory and storage research at IHS Markit. “Prices and shipments were up during the quarter as strong demand for mobile and server DRAM continued to propel the market.”

The NAND industry had another record quarter as well, growing 12.9 percent in the third quarter of 2017, with total revenue reaching $14.2 billion. “Pricing was flat in the quarter, as seasonally strong demand driven by the mobile and solid-state drive segments was able to offset moderate shipment growth,” said Walter Coon, director for NAND flash technology research at IHS Markit. “The market is expected to soften exiting 2017 and into early next year, as the industry transition to 3D NAND technology continues to progress and the market enters a traditionally slower demand period.”

Manufacturer moves

Samsung officially passed Intel to become the number-one semiconductor supplier in the world in the third quarter of 2017, growing 14.9 percent sequentially. Intel now comes in at number two, with SK Hynix securing the third rank in terms of semiconductor revenue for the third quarter.

Among the top 20 semiconductor suppliers, Apple and Advanced Micro Devices (AMD) achieved the highest revenue growth quarter over quarter by 46.6 percent and 34.3 percent, respectively.

There was a good deal of market share movement within the top 10 suppliers throughout the third quarter as well. In terms of semiconductor revenue, Qualcomm surpassed Broadcom Limited to secure the number-five spot, while nVidia made its way into the top 10 ranking for the first time ever. At this time last year, the top five semiconductor companies controlled 40 percent market share of the entire industry. The top five gained 4.2 percent more market share this year over last year, while comprising three memory companies instead of the previous two.

More information on this topic can be found in the latest release of the Semiconductor Competitive Landscaping Tool (CLT) from the IHS Markit Semiconductor Competitive Landscape CLT Intelligence Service.

Soitec announces substrate breakthrough for 3D image sensing devices

November 30, 2017

Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, today announced the latest generation of silicon-on-insulator (SOI) substrates in its Imager-SOI product line designed specifically for fabricating front-side imagers for near-infrared (NIR) applications including advanced 3D image sensors. The new SOI wafers from Soitec are now available in large volumes with high maturity to meet the needs of customers in the growing market for 3D cameras used in augmented reality (AR) and virtual reality (VR), facial-recognition security systems, advanced human/machine interfaces and other emerging applications.

“Our newest Imager-SOI substrates represent a major achievement for our company and a smart way to increase performance in NIR spectrum domain, accelerating new applications in the growing 3D imaging and sensing markets,” said Christophe Maleville, executive vice president of the Digital Electronics Business Unit at Soitec. “Innovative sensor design on SOI is achieved by leveraging our advanced know-how in ultrathin material layer transfer and our extensive manufacturing experience.”

The new SOI substrate makes it possible to simply extend the operating range of high resolution silicon based CMOS image sensors into the NIR spectrum. This optimized version of SOI substrate greatly improves the signal to noise ratio in the NIR spectrum.

The market for 3D imaging and sensing devices is forecast to grow at a CAGR of 37.7 percent over the next five years and reach US$9 billion in sales by 2022, according to Yole Développement. The market research and consulting firm predicts that 2018 will likely see a massive influx of products, with the first applications in mobile electronics and computing.*

Will Samsung’s 2017 semi capex deliver knockout blow to competition?

November 15, 2017

IC Insights has revised its outlook for semiconductor industry capital spending and will present its new findings in the November Update to The McClean Report 2017, which will be released at the end of this month. IC Insights’ latest forecast now shows semiconductor industry capital spending climbing 35% this year to $90.8 billion.

After spending $11.3 billion in semiconductor capex last year, Samsung announced that its 2017 outlays for the semiconductor group are expected to more than double to $26 billion. Bill McClean, president of IC Insights stated, “In my 37 years of tracking the semiconductor industry, I have never seen such an aggressive ramp of semiconductor capital expenditures. The sheer magnitude of Samsung’s spending this year is unprecedented in the history of the semiconductor industry!”

Figure 1 shows Samsung’s capital spending outlays for its semiconductor group since 2010, the first year the company spent more than $10 billion in capex for the semiconductor segment. After spending $11.3 billion in 2016, the jump in capex expected for this year is simply amazing.

To illustrate how forceful its spending plans are, IC Insights anticipates that Samsung’s semiconductor capex of $8.6 billion in 4Q17 will represent 33% of the $26.2 billion in total semiconductor industry capital spending for this quarter. Meanwhile, the company is expected to account for about 16% of worldwide semiconductor sales in 4Q17.

IC Insights estimates that Samsung’s $26 billion in semiconductor outlays this year will be segmented as follows:

3D NAND flash: $14 billion (including an enormous ramp in capacity at its Pyeongtaek fab)

DRAM: $7 billion (for process migration and additional capacity to make up for capacity loss due to migration)

Foundry/Other: $5 billion (for ramping up 10nm process capacity)

IC Insights believes that Samsung’s massive spending outlays this year will have repercussions far into the future. One of the effects likely to occur is a period of overcapacity in the 3D NAND flash market. This overcapacity situation will not only be due to Samsung’s huge spending for 3D NAND flash, but also to its competitors in this market segment (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) responding to the company’s spending surge. At some point, Samsung’s competitors will need to ramp up their capacity or loose market share.

Samsung’s current spending spree is also expected to just about kill any hopes that Chinese companies may have of becoming significant players in the 3D NAND flash or DRAM markets. As our clients have been aware of for some time, IC Insights has been extremely skeptical about the ability of new Chinese startups to compete with Samsung, SK Hynix, and Micron with regards to 3D NAND and DRAM technology. This year’s level of spending by Samsung just about guarantees that without some type of joint venture with a large existing memory suppler, new Chinese memory startups stand little chance of competing on the same level as today’s leading suppliers.

A*STAR IME’s new multi-chip FOWLP development line to drive innovation and growth in semiconductor industry

November 8, 2017

A*STAR’s Institute of Microelectronics (IME) has established a development line to accelerate the development of fan-out wafer level packaging (FOWLP) capabilities for next-generation Internet of Things (IoT) technologies. The FOWLP development line, which is built upon existing infrastructure at IME’s facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners (see Annex A for list of partners) to develop technologies that serve a wide range of markets such as that of consumer electronics, healthcare and automotive.

The IoT is set to become the next growth driver for the semiconductor industry, as demand for internet-connected devices continues to soar. FOWLP is an emerging breakthrough chip packaging technology platform aimed at meeting the technology requirements of next-generation electronic devices that require ultra- low power consumption rates, smaller package profiles, higher performance; and all made at a lower cost.

IME’s FOWLP development line is equipped with fully automated tools that can perform the “mold-first” and “Re-Distribution Layer (RDL)-first” method in multi- chip fabrication. The “RDL-first” method is expected to achieve a higher reliability rate compared to the conventional “mold-first” method traditionally used by the semiconductor industry. IME and its partners will jointly develop tools and processes for next-generation FOWLP technologies such as high speed Copper (Cu) pillar plating, Physical Vapor Deposition (PVD) process to control the wafer warpage, moldable underfilling for Chip-to-Wafer, as well as over molding on wafer with vertical Cu pillar/Cu wire interconnections using wafer level compression molding, plasma descum of small vias and warpage adjustment, etc.

To unlock the potential of FOWLP and accelerate the development and adoption of these innovative process technologies by the industry, IME has also formed a consortium comprising leading OSATs, Materials, Equipment, EDA, Fabless partners (see Annex A for list of consortium members).

The FOWLP development line consortium will allow members across the value chain to co-share resources on an open innovation platform, and draw upon IME’s rich portfolio of advanced packaging capabilities to address the complexities in system scaling and heterogeneous system integration. The FOWLP development line will be a test-bedding platform through which consortium members could gain new insights on requirements of FOWLP by testing and developing new processes, paving the way for high-volume manufacturing.

The FOWLP development line utilises tools already in use in major OSATs, and will allow processes, materials and integration flows developed at IME to be smoothly transferred. Through this development line, fabless companies could also make quicker decisions on package structure, integration flows, processes, materials and equipment for their new products; so materials and equipment suppliers could expedite the development of their products and increase their adoption.

“The launch of IME’s FOWLP development line and consortium will enable us to advance pre-competitive R&D that positions the semiconductor industry for growth opportunities in the thriving IoT market. Through an open and collaborative approach, the consortium will drive the development and the transfer of innovative technologies from pilot-scale to commercial production more easily and quickly,” said Dr. Tan Yong Tsong, Executive Director, IME.

“We are extremely proud to be a part of IME’s FOWLP consortium and play an active role in this great initiative. This broad industry cooperation will help solve one of the largest challenges faced by the semiconductor industry in the area of achieving higher density in advanced packaging. ERS is committed to developing new thermo-management solutions to enable next generation of FOWLP technologies,” said Mr. Klemens Reitinger, Chief Executive Officer, ERS Electronic GmbH.

“We are pleased to be collaborating with IME in this FOWLP development line consortium (DLC). We have benefitted from the experience in the previous consortium on High Density FOWLP, and are confident that with our combined experience and knowledge, the consortium will accelerate the development of FOWLP and establish an innovative cost-effective manufacturing process to further the mass adoption of FOWLP,” said Mr. Tong Liang Cheam, Vice President of Corporate Strategy, Kulicke & Soffa.

“It’s exciting to participate in this new FOWLP development line at IME to advance chip packaging. Nordson has a successful history of working on innovations in the semiconductor packaging industry, and this consortium is positioned well to produce excellent solutions,” said Mr. Joseph Stockunas, Vice President, Advanced Technology – Electronics Systems, Nordson Corporation.

“It is through collaborative efforts, such as that of the FOWLP development line and consortium that the semiconductor ecosystem can advance. Our engagement with the consortium will not only benefit our customers, but the industry as a whole in driving the adoption of this technology for emerging High Bandwidth Memory (HBM) and diverse IoT applications,” said Mr. Asim Salim, Vice President of Manufacturing Operations, Open-Silicon. “Through Open- Silicon’s extensive experience in 2.5D ASIC design, and the expertise of the consortium, issues like cost will be mitigated, thus enabling OEMs of all sizes to adopt FOWLP technology.”

“We are delighted to be a part of IME’s FOWLP development line consortium and continue to play an active role in this open innovation initiative. Industry-wide cooperation is key in overcoming the many challenges faced today by the electronics packaging industry. Orbotech is committed to developing new cost- efficient solutions to enable the next generation of advanced packaging technologies, which in turn will impact the industry’s next inflection point,” said Dr. Abraham Gross, Chief Technology Officer and Head of Innovation, Orbotech.

“As demand for high speed, high bandwidth data connectivity in consumer electronics continues to grow, the performance and cost challenges limiting the implementation of high frequency millimeter wave applications have the potential to be addressed with FOWLP solutions. We look forward to working with the FOWLP development line consortium to realise the benefits of FOWLP technology for mmWave antennae devices in emerging markets such as automotive and the Internet of Things (IoT),” said Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC.

The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

The intelligence that leads to artificial intelligence

November 8, 2017

By Ajit Manocha, president and CEO, SEMI

Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding. Early in SEMI’s history, SEMI’s always intelligent members worked together to introduce International Standards that enabled different pieces of equipment to collect and later pass data. At first, it was for basic interoperability and equipment state analysis. Later, SEMI data protocol Standards allowed process and metrology data to be used locally and across the fab to approach the goals of Smart Manufacturing and AI – for the equipment itself to make adjustments based on incoming wafer data.

As a part of this evolution, SEMI members developed the latest sensors and computational hardware that could ever better sense, analyze and act on the environment. Often first to use its own newly developed hardware, progress in this area was critical toward improving the likelihood of success for one of the world’s most complicated production processes – and coping with the breakneck speed of Moore’s Law – by accelerating capabilities that would later be regarded as the basis for machine learning and “thinking” systems.

Since then, process steps have increased from about 175 to as many as 1,000 for the leading technology nodes. By the time 300mm wafers were introduced, manufacturing intelligence and automation sharply increased productivity while reducing fab labor by more than 25 percent. Employing adaptive models, modern leading-edge factories are fully automated and operate at nearly 60 percent autonomous control.

Today, AI is akin to where IoT was yesterday in the hype cycle – popping up everywhere as a major consideration for the future. Neither IoT nor AI is hype, though – they’re the future. There is ever more at stake for SEMI members with AI. AI appears to be the next wave helping to maintain double-digit growth for the foreseeable future.

As part of its appeal for the global supply chain, AI can be a key silicon driver for three inflections that should benefit society. First, there is a massive increase in the amount of compute needed. Half of all the compute architectures shipping in 2021 will be supporting and processing AI.

Second, the Cloud will flourish and the Edge will bloom. By 2021, 50 percent of enterprise infrastructure will employ cognitive and artificial intelligence.

Third, new species of chips will emerge, such as the devices fueling IC content and electronics for the rapid growth of disruptive capabilities in vehicles and autonomous cars (as well as medical and agricultural applications, for example). There are also many more advantages created with and for AI as SEMI members enable new materials and advanced packaging.

What results can be measured from these changes for the global electronics manufacturing supply chain? More apps, more electronics, more silicon and more manufacturing.

On the other hand, the technologies alone create relatively little business value if the problems in our factories and markets are not well understood. There’s a great need to anticipate and guide AI. This requires a new kind of collaboration.

To address this need, SEMI’s vertical application platforms have been created for Smart Data (which is all about AI), and also for Smart MedTech, Smart Transportation, Smart Manufacturing and IoT. This higher degree of facilitated collaboration serves to cultivate multiple “smart communities” that accelerate progress for AI, better directing how connected networks and data mining can step up the pace for advancement of global prosperity. This process also provides members with access to untapped business opportunities and new players.

We at SEMI are learning right along with our members. If you attended SEMICON West in July, several lessons about AI were presented by the Executive Panel (“Meeting the Challenges of the 4^th Industrial Revolutions along the Microelectronics Supply Chain”) with Mary Puma (Axcelis), Shaheen Dayal (Intel), Lori Ciano (Brooks Automation) and Regenia Sanders (Ernst & Young). This very timely and excellent panel discussed how and where predictive analytics can have the biggest impact and the implications of sharing (and not sharing) data for problem solving and process optimization.

Ensuring that the SEMI staff gleans everything possible from the experts, we hosted an “encore” of the Executive Panel in October in our headquarters for an even more in-depth discussion about how to enhance collaboration across the supply chain in support of AI.

Going forward, these SEMI vertical platform communities will help to simplify and accelerate supply chain engagement for member value. Collaboration will play an ever greater role for using AI to master the making of advanced node semiconductor devices and enabling limitless cognitive computing. As a result, AI as we know it today, has a big head start over the previous pace of evolution for one of our great trendsetters, Moore’s Law.

Join the conversation. Find out how you can work with SEMI to advance the AI – and especially AI in semiconductor manufacturing. Frank Shemansky Jr., Ph.D., is heading up SEMI’s formation of SEMI’s Smart Data vertical application platform. Let Frank know ([email protected]) you’re interested and he’ll give you more information on what’s to come. As always, please let me know your thoughts.