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The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

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A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

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At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

The number of IC packages utilizing wafer-level packaging (WLP) will overtake flip chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for flip chip, according to the report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” recently published by The Information Network, a New Tripoli, PA-based market research company.

“Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT,” noted Dr. Robert Castellano, [resident of The Information Network. “Flip chip technology is slowly replacing wire bonding for many high-performance chips, and wafer level packaging (WLP) is replacing flip chip.”

wlp device shipment

To meet the needs of thinner mobile devices, fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor. The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.

IC Insights has raised its IC market growth rate forecast for 2017 to 22%, up six percentage points from the 16% increase shown in its Mid-Year Update.  The IC unit volume shipment growth rate forecast has also been increased from 11% depicted in the Mid-Year Update to 14% currently.  As shown below, a large portion of the market forecast revision is due to the surging DRAM and NAND flash markets.

In addition to increasing the IC market forecast for this year, IC Insights has also increased its forecast for the O-S-D (optoelectronics, sensor/actuator, and discretes) market.  In total, the semiconductor industry is now expected to register a 20% increase this year, up five percentage points from the 15% growth rate forecast in the Mid-Year Update.

For 2017, IC Insights expects a whopping 77% increase in the DRAM ASP, which is forecast to propel the DRAM market to 74% growth this year, the largest growth rate since the 78% DRAM market increase in 1994.  After including a 44% expected surge in the NAND flash market in 2017, including a 38% increase in NAND flash ASP this year, the total memory market is forecast to jump by 58% in 2017 with another 11% increase forecast for 2018.

At $72.0 billion, the DRAM market is forecast to be by far the largest single product category in the semiconductor industry in 2017, exceeding the expected NAND flash market ($49.8 billion) by $22.2 billion this year. As shown in Figure 1, the DRAM and NAND flash segments are forecast to have a strong positive impact of 13 percentage points on total IC market growth this year. Excluding these memory segments, the IC industry is forecast to grow by 9%, less than half of the current total IC market growth rate forecast of 22% when including these memory markets.

Figure 1

Figure 1

IC Insights is set to release its October Update to The McClean Report.  The 30-page Update includes a detailed analysis of IC Insights’ revised forecasts for the IC, O-S-D, and total semiconductor markets through 2021.

The annual revenue from the global IC testing and packaging industry for 2017 is estimated to grow by 2.2% to reach US$51.73 billion, according to the latest research from TrendForce. Furthermore, providers of outsourced semiconductor assembly and test (OSAT) are projected to represent a share of 52.5% in the year’s total revenue.

The IC testing and packaging industry is expected to register recovery and growth in 2017 in contrast to the 2016 revenue result that showed a slight annual decline. This year, the main revenue driver has been the increase in the amount of IC components demanded for mobile devices. The strong demand for IC components has also expanded the deployment of advanced packaging solutions that offer higher levels of integration and higher numbers of I/O connections. In sum, the rising quantity and quality of demand during this year has benefited the IC testing and packaging industry revenue-wise.

The projected revenue ranking of the top 10 OSAT providers for 2017 is overall similar to the 2016 ranking. This year’s top three in sequence are ASE, Amkor and JCET. Among the top 10, PTI has gained enormously from the memory boom caused by the combination of tight market supply, application growth for high-performance computing and strong demand for high-density storage products. PTI also has the advantage of having a strong relationship with the memory giant Micron. TrendForce estimates that PTI’s annual revenue growth for this year will reach an impressive 26.3%, putting the company in the fifth place of the ranking.

osats

China’s IC backend service providers are focusing on developing their technologies as their progress in overseas mergers and acquisitions slows

TrendForce’s survey of the testing and packaging industry in 2017 also finds that there are now much fewer M&A targets for Chinese companies because of the increasing level of competition and consolidation activities in the global semiconductor sector. Furthermore, the barriers against Chinese companies for making overseas acquisitions using domestic capital have also been raised. Thus, Chinese IC backend service providers are shifting their focus away from trying to get technologies and market shares via overseas M&As. Instead, they are investing their resources in developing technologies related to fan-out processing and system-in-package (SiP) integration. They eventually want to get their solutions verified by potential clients, proving that they have the in-house expertise to be competitive in the market.

Chinese testing and packaging companies continue to gain processing capacity for packaging technologies that are high-end (e.g. flip chip and bumping) and more advanced (e.g. fan-in, fan-out, 2.5D interposer and SiP). Because of the progress in both technology development and M&As, Chinese service providers such as JCET, TSHT and TFME are projected to rise above the industry’s average in their revenue performances this year with double-digit growth rates.

Additionally, China’s IC testing and packaging industry will be supported by the growing number of domestic fabs in the coming year. TrendForce forecasts that China’s monthly 12-inch wafer capacity will increase by about 162,000 pieces before the end of 2018. This 180% increase from the current capacity level will give a sizable injection of demand into the domestic testing and packaging market.

 

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

As shown in Figure 1, 300mm wafers represented 63.6% of worldwide IC fab capacity at the end of 2016 and are projected to reach 71.2% by the end of 2021, which translates into a compound annual growth rate (CAGR) of 8.1% in terms of silicon area for processing by plant equipment in the five-year period.

capacity install

Figure 1

The report’s count of 98 production-class 300mm fabs in use worldwide at the end of 2016 excludes numerous R&D front-end lines and a few high-volume 300mm plants that make non-IC semiconductors (such as power transistors).  Currently, there are eight 300mm wafer fabs that have opened or are scheduled to open in 2017, which is the highest number in one year since 2014 when seven were added, says the Global Wafer Capacity report.  Another nine are scheduled to open in 2018.   Virtually all these new fabs will be for DRAM, flash memory, or foundry capacity, according to the report.

Even though 300mm wafers are now the majority wafer size in use, both in terms of total surface area and in actual quantity of wafers, there is still much life remaining in 200mm fabs, the capacity report concludes.  IC production capacity on 200mm wafers is expected to increase every year through 2021, growing at a CAGR of 1.1% in terms of total available silicon area. However, the share of the IC industry’s monthly wafer capacity represented by 200mm wafers is forecast to drop from 28.4% in 2016 to 22.8% in 2021.

IC Insights believes there is still much life left in 200mm fabs because not all semiconductor devices are able to take advantage of the cost savings 300mm wafers can provide.  Fabs running 200mm wafers will continue to be profitable for many more years for the fabrication of numerous types of ICs, such as specialty memories, display drivers, microcontrollers, and RF and analog products.  In addition, 200mm fabs are also used for manufacturing MEMS-based “non-IC” products such as accelerometers, pressure sensors, and actuators, including acoustic-wave RF filtering devices and micro-mirror chips for digital projectors and displays, as well as power discrete semiconductors and some high-brightness LEDs.

Today, Intel announced the delivery of a 17-qubit superconducting test chip for quantum computing to QuTech, Intel’s quantum research partner in the Netherlands. The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

The delivery of this chip demonstrates the fast progress Intel and QuTech are making in researching and developing a working quantum computing system. It also underscores the importance of material science and semiconductor manufacturing in realizing the promise of quantum computing.

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Quantum computing, in essence, is the ultimate in parallel computing, with the potential to tackle problems conventional computers can’t handle. For example, quantum computers may simulate nature to advance research in chemistry, materials science and molecular modeling – like helping to create a new catalyst to sequester carbon dioxide, or create a room temperature superconductor or discover new drugs.

However, despite much experimental progress and speculation, there are inherent challenges to building viable, large-scale quantum systems that produce accurate outputs. Making qubits (the building blocks of quantum computing) uniform and stable is one such obstacle.

Qubits are tremendously fragile: Any noise or unintended observation of them can cause data loss. This fragility requires them to operate at about 20 millikelvin – 250 times colder than deep space. This extreme operating environment makes the packaging of qubits key to their performance and function. Intel’s Components Research Group (CR) in Oregon and Assembly Test and Technology Development (ATTD) teams in Arizona are pushing the limits of chip design and packaging technology to address quantum computing’s unique challenges.

About the size of a quarter (in a package about the size of a half-dollar coin), the new 17-qubit test chip’s improved design features include:

  • New architecture allowing improved reliability, thermal performance and reduced radio frequency (RF) interference between qubits.
  • A scalable interconnect scheme that allows for 10 to 100 times more signals into and out of the chip as compared to wirebonded chips.
  • Advanced processes, materials and designs that enable Intel’s packaging to scale for quantum integrated circuits, which are much larger than conventional silicon chips.

“Our quantum research has progressed to the point where our partner QuTech is simulating quantum algorithm workloads, and Intel is fabricating new qubit test chips on a regular basis in our leading-edge manufacturing facilities,” said Dr. Michael Mayberry, corporate vice president and managing director of Intel Labs. “Intel’s expertise in fabrication, control electronics and architecture sets us apart and will serve us well as we venture into new computing paradigms, from neuromorphic to quantum computing.”

Intel’s collaborative relationship with QuTech to accelerate advancements in quantum computing began in 2015. Since that time, the collaboration has achieved many milestones – from demonstrating key circuit blocks for an integrated cryogenic-CMOS control system to developing a spin qubit fabrication flow on Intel’s 300mm process technology and developing this unique packaging solution for superconducting qubits. Through this partnership, the time from design and fabrication to test has been greatly accelerated.

“With this test chip, we’ll focus on connecting, controlling and measuring multiple, entangled qubits towards an error correction scheme and a logical qubit,” said professor Leo DiCarlo of QuTech. “This work will allow us to uncover new insights in quantum computing that will shape the next stage of development.”

Advancing the quantum computing system

Intel and QuTech’s work in quantum computing goes beyond the development and testing of superconducting qubit devices. The collaboration spans the entire quantum system – or “stack” – from qubit devices to the hardware and software architecture required to control these devices as well as quantum applications. All of these elements are essential to advancing quantum computing from research to reality.

Also, unlike others, Intel is investigating multiple qubit types. These include the superconducting qubits incorporated into this newest test chip, and an alternative type called spin qubits in silicon. These spin qubits resemble a single electron transistor similar in many ways to conventional transistors and potentially able to be manufactured with comparable processes.

While quantum computers promise greater efficiency and performance to handle certain problems, they won’t replace the need for conventional computing or other emerging technologies like neuromorphic computing. We’ll need the technical advances that Moore’s law delivers in order to invent and scale these emerging technologies.

Intel is investing not only to invent new ways of computing, but also to advance the foundation of Moore’s Law, which makes this future possible.

The global CMOS image sensor market is expected to grow at a CAGR of more than 12% during the forecast period, according to Technavio’s latest market research.

In this market research report, Technavio covers the market outlook and growth prospects of the global CMOS image sensor market for 2017-2021. The market is further categorized into four application segments, including consumer devices, automotive, security, and industrial. The consumer devices segment accounted for close to 83% of the market share in 2016.

“The market is characterized by a technological shift from charged CCD sensors to CMOS because of the simple manufacturing process and low costs. Though CCD sensors offer better features, such as great light sensitivity and quality, their adoption is low because of their complicated design and high-power consumption. The consumer device segment will remain the key market driver during the forecast period owing to the increase in the demand for mobile-related applications,” says Chetan Mohan, a lead sensors research expert from Technavio.

CMOS image sensor market in Americas

The CMOS image sensor market in the Americas is expected to maintain its steady growth trajectory in the coming years. The early adoption of new technologies and gadgets drives the market growth. In addition, the region has a large consumer base for consumer electronics, such as tablets and smartphones.

The high rate of industrial automation in the US drives the demand for CMOS image sensors as they are widely used in automated manufacturing and process machinery. The US and Canada boast of a strong healthcare sector which will lead to demand for a large number of medical devices that are integrated with CMOS image sensors.

“The growing demand for camera-enabled phones in South America will drive the market in the region. The government in South America is also focusing on urbanization and improving healthcare sectors. The increasing use of these sensors in automobiles and medical equipment is expected to have a positive impact on the market in the region,” says Chetan.

CMOS image sensor market in APAC

The region is expected to grow at the highest CAGR, owing to the presence of many manufacturing units for consumer electronic devices. In addition, APAC has the largest customer base for consumer devices. Rising disposable incomes have led to increased consumer spending capacity, which has further fueled the demand for latest gadgets. China, Japan, Taiwan, South Korea, and India are the key revenue contributors to the market in the region. These countries have numerous consumer electronics manufacturing units.

The presence of numerous semiconductor manufacturers in Japan, Taiwan, Korea, and China, will fuel market growth. In addition, the availability of low-cost labor and setting up of production facilities by global vendors are factors that will have a positive impact on the market in the region.

CMOS image sensor market in EMEA

EMEA will exhibit the lowest growth compared with other regions because of the low concentration of image sensor manufacturers and small consumer base. Germany is among the leading nations in the region. The country has numerous leading car manufacturers that offer CMOS sensing technology in their vehicles. The technology ensures passenger safety and promotes the development of intelligent vehicle systems. The country plans to automate a majority of the industrial process by the end of the forecast period. Advanced R&D in the medical field will also drive the demand for image sensing technology. South Africa is expected to account for the highest contribution to the market share in this region.

The top vendors in the global CMOS image sensor market as highlighted in this market research analysis are:

  • Sony
  • Samsung
  • OmniVision Technologies
  • ON Semiconductor