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IC Insights has revised its outlook and analysis of the IC industry and presented its new findings in the Mid-Year Update to The McClean Report 2017, which originally was published in January 2017.  Entering the second half of the year, it is clear the IC industry is on course for a much stronger upturn than was initially forecast in January.  IC Insights now expects the IC market to increase 16% in 2017 due to exceptional growth in the DRAM and NAND flash memory markets. The DRAM market is now forecast to grow 55% and the NAND flash market is now expected to rise 35% this year—in both cases, almost entirely due to fast-rising prices rather than unit growth.  Excluding these two markets, the overall IC market growth is forecast to show just 6% year-over-year growth (Figure 1).  The expected 16% increase would be the first double-digit gain for the IC market since it expanded by 33% in 2010—the recession-recovery year—and the fifth double-digit increase for the IC market since 2000.

ic insights

As seen in the figure, the DRAM market has had a notable impact on total IC market growth in recent years. With market surges of 32% and 34% in 2013 and 2014, respectively, the DRAM market alone boosted the worldwide IC market growth rate by three percentage points in 2013 and four percentage points in 2014.

At $64.2 billion, the DRAM market is forecast to be by far the largest single product category in the IC industry in 2017, exceeding the expected second-ranked MPU market for standard PCs and servers ($47.1 billion) by $17.1 billion this year.

Overall, IC Insights’ global economic outlook remains on course with initial projections covered in The McClean Report. Electronic system production, capital spending as a percent of sales, and IC wafer capacity added were unchanged from the original outlook.  However, other factors and conditions that contribute to the forecast were upgraded slightly in the Mid-Year Update. For example, the worldwide GDP forecast was upgraded by 0.1 point to 2.7% for 2017, marginally ahead of what is considered to be the global recession threshold of 2.5% growth.  IC Insights believes that through the forecast period, annual IC market growth rates will closely track with the performance of worldwide GDP growth.

Following a fairly strong first half of growth, China’s 2017 GDP was raised to 6.8% for 2017 from the original forecast of 6.3%.  Also, IC Insights upgraded its U.S GDP forecast to 2.1% in the Mid-Year Updatefrom 2.0% in January. While the U.S. economy is far from perfect, it is currently one of the most significant positive driving forces in the worldwide economy.  A falling unemployment rate, PMI figures of 57.0 and 55.8 in the first and second quarters of this year, and relatively low oil prices should help the U.S. economy sustain its modest growth in the second half of this year. Growth rates for IC unit shipments, IC average selling price, and semiconductor capital spending were also revised slightly higher.

Additional details and commentary regarding the updated IC forecasts for the 2017-2021 timeperiod are covered in IC Insights’ Mid-Year Update to The McClean Report 2017.

As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunities for continued innovation.

BY HARMEET SINGH, Lam Research Corp., Fremont, CA

Since its introduction several years ago, 3D NAND has become a mainstream technology because of its ability to increase bit density in memory devices. Its adoption has been accelerated by advances in the underlying manufacturing processes that are enabling 3D architectures and lowering the cost per bit. With all its advantages, however, the overall complexity and capital intensity of 3D NAND manufacturing add significantly to the challenges fabs are facing in terms of process control, yield, and economics.

Market and technology drivers for 3D NAND

The main impetus for 3D NAND was the recognition that planar technology was approaching the end of its physical limits to deliver higher densities and a lower cost-per-bit. Past advances in conventional planar NAND technology have primarily been driven by physical scaling, where lithography capabilities determined just how many memory cells could fit within a given die size. Using multiple levels of charge within each cell by going from single- to multi-level cell designs has also enabled increased bit densities. However, these improvements typically have come at the expense of speed because of the need to differentiate between the multiple levels of charge. In addition, since the individual memory cells for these designs lie in a horizontal plane, scaling is still ultimately limited by lithography. Other challenges in scaling 2D NAND beyond the 15 nm node include cell-to-cell interference, unscalable dielectrics, and electron leakage [1].

To address these challenges, 3D NAND fundamentally changes the scaling paradigm. Instead of traditional X-Y scaling in a horizontal plane, 3D NAND scales in the Z-direction by stacking multiple layers of NAND gates vertically. This allows more cells to be packed into the same X-Y space (planar area) on the die without shrinking dimensions horizontally. By easing cell size requirements, triple- and even quadruple-level cell designs are possible. As such, 3D NAND offers a signif- icant increase in bit density over planar NAND.

Unlike planar NAND, where scaling is primarily driven by lithography, 3D NAND scaling is enabled by advances in deposition and etch processes. An incredible level of precision and repetition is required in defining complex 3D structures with extremely high aspect ratio (HAR) features. Achieving success with 3D NAND requires innovative deposition and etch solutions that minimize variability.

Overview of critical 3D NAND processes

The 3D NAND architecture requires advanced capabilities enabling HAR and complex structures (FIGURE 1). Critical processes involved include multilayer stack deposition, HAR channel etch, wordline metallization, staircase etch, HAR slit etch, and stair contacts formation. The following sections look at some of these areas in more depth and describe the most critical process parameters that must be controlled.

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Film deposition

Creating stacked memory cells starts with depositing alternating layers of thin films. Unlike planar NAND, where cell pitch is defined by lithography, pitch in 3D NAND is determined by the film thickness. As such, precise control of layer-to-layer deposition uniformity is extremely important. Currently, commercial 3D NAND products in high-volume manufacturing have layers ranging from 32 to 48 pairs, while next-generation products with more than 60 pairs are now beginning high-volume ramps.

Critical requirements for depositing stacked films are the stress and uniformity of the individual layers within the overall stack. These requirements become more stringent and increasingly more challenging to meet as the number of layers grows. Wafer bow and local film stress (FIGURE 2) directly impact the ability to achieve precise lithog- raphy overlay. Film thickness and repeatability affects the active area of cell and consistency of the litho/etch performance. As a result, both film stress control and excellent uniformity are critical to wafer yields. To address these concerns, careful management of stress by tuning deposition conditions and optimizing integration is needed not only for the film stack deposition, but also throughout 3D NAND manufacturing.

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High aspect ratio channel etching

HAR channel etch is the most critical and challenging step in 3D NAND because it is key to achieving uniform hole size through multiple layers to define the channel of memory cells. More than a trillion holes must be etched simultaneously and uniformly on every wafer, each with an aspect ratio of more than 40:1. For comparison, the highest aspect ratio structure that is etched in planar NAND is less than 15:1.

Deep etch on these multilayer stacks can push the limits of physics to achieve uniformity from top to bottom. As shown in FIGURE 3, the high aspect ratio of this etch leads to transport limitation challenges that can generate a range of problems. These include incomplete etch wherein some holes don’t reach the bottom, bowing, twisting, and CD variation between the top and bottom of the stack. Such defects can lead to shorts, interference between neighboring memory strings, and other perfor- mance issues. Solving these HAR-related transport issues requires precise control of high-energy ions during the etch process. Technologies that help deliver this capability include a symmetric chamber design for intrinsic uniformity, a proprietary high ion energy source with advanced plasma confinement and modulation, and orthogonal (independent) uniformity tuning knobs, such as multi-zone gas delivery and temperature control to achieve required uniformity across the wafer.

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As the 3D NAND roadmap adds more layers to achieve higher bit density, channel hole etching becomes increasingly challenging due to higher aspect ratios. Managing the fundamental trade-offs among profile, selectivity, and CD requires continuous equipment innovation, not only to deliver HAR etching capabilities for more than 100 pairs, but also to do this at the productivity needed for volume manufacturing.

Wordline tungsten metal fill

For replacement-gate 3D NAND schemes, wordline tungsten fill provides the critical conductive links between individual memory cells within layers. This process is particularly challenging because of the need to achieve void-free fill of complex, narrow, lateral structures with minimal stress on the memory stack.

Due to the structural complexity, atomic-scale engineering is required for wordline fill. Traditional CVD tungsten films have inherent characteristics that limit capability for 3D NAND wordline fill. High tensile stress in CVD tungsten can lead to wafer bow, and fluorine in the process has been known to diffuse into adjacent layers where it can create yield-limiting defects. In addition, resistivity limits scaling: making each layer thinner would allow for more layers (more storage bits), but would also make wordline resistance too high. One approach to address these concerns is the use of a low-fluorine tungsten (LFW) ALD process. This has the ability to provide a smoother morphology that conforms better with the surface in each fill layer, thereby minimizing stress induced by the deposition process. Stress reduction by more than an order of magnitude has been demonstrated with LFW ALD technology. This approach has also been shown to lower fluorine content by up to 100x (FIGURE 4) and reduce resistivity by over 30% compared to conventional CVD tungsten.

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Staircase etch

The staircase etch step creates the individual contact pads for each memory cell within the layers. A highly controlled etch process is used to define the size of each contact pad. To reduce the cost associated with lithography and improve productivity, repeated vertical etch and lateral trim etch processes are adopted to form the staircase instead of using numerous lithography steps. For each lithography pass, multiple staircase levels can be created by etching and trimming, as shown in FIGURE 5. The number of stairs that can be formed by this process is determined by the lateral-to-vertical (L/V) etch rate. Improving L/V etch selec- tivity can reduce the number of lithography steps needed.

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Extreme accuracy is required to maintain the stair CD, thus avoiding misaligned contacts. If the CD for a pad is off by a few percent, that error will propagate through subsequent pads defined within the same lithography pass. Current technology can deliver uniform and repeatable stair CD precision of 1% (3-sigma) after more than five L/V trim processes. This is a critical factor for achieving high productivity and being able to scale to higher stacks with more layers economically.

Summary

Traditional planar scaling to increase NAND density is approaching its limits due to lithography and performance challenges. As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunitiesforcontinuedinnovation. Stress management throughout wafer processing is crucial, and significant innovations in both deposition and etch processes are essential in forming the HAR features that dominate 3D NAND architectures. Finally, reducing variability in every critical step is a must to meet performance, yield, reliability, and cost requirements.

3D NAND completely changes the scaling paradigm by going vertical. No longer limited by lithography capabilities, 3D NAND can achieve greater levels of integrity, perfor- mance, and reliability – while building vertically for higher bit density and a lower cost-per- bit – through relying on advances in deposition and etch processes.

References

1. Y.W. Park, Flash Memory, IEDM short course, 2015

BY ELISABETH BRANDL, THOMAS UHRMANN and MARTIN EIBELHUBER, EV Group, St. Florian, Austria

Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance. For all aforementioned packages, temporary bonding will be needed, either to enable the thinning of wafers to address the need for smaller form factors, to achieve cost savings on mold materials or to serve as a processing platform for redistribution-layer (RDL) first processes.

Temporary bonding requires both a bonding and debonding process. Determining the right debonding technology can be difficult and confusing as every application from fan-out wafer-level packaging (FoWLP) to power devices has its own requirements in terms of process temperature, mechanical stress and thermal budget, to name just a few considerations. In this article, we will focus on laser debonding, where high- temperature compatible materials are available. We will point out for which applications the laser debond characteristics fit well.

To limit the thermal input associated with debonding, UV lasers are utilized for debonding where several materials from different temporary bonding material suppliers are available. To confine the maintenance effort to a minimum, a diode-pumped solid-state (DPSS) laser is the right choice in combination with beam-shaping optics for high process control and minimum heat input.

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Challenges of temporary bonding for FoWLP

FoWLP has gained significant industry interest in part due to carrier, the requirements of the temporary bonding material in terms of chemical and thermal compat- ibility are high. Certain kinds of polyimides comply with this harsh environment and are also suitable for laser debonding.

By just comparing these two processes, the require- ments differ significantly even though both are FoWLP processes. By looking at the wide variety of semiconductor processes for various applications, it becomes clear that no single debonding process solution is compatible with all semiconductor processes, but rather several solutions are necessary. This is the reason why a variety of debonding processes (temporary bonding is characterized by the debonding technology) have been developed and are still in use today.

Comparison of the mainstream debonding technologies

The most common debonding methods are thermal slide-off debonding, mechanical debonding and UV laser debonding. These three methods are all in high- volume manufacturing and differ strongly in their process compatibility.

Thermal slide-off is a method that employs a thermo-plastic material as an adhesive interlayer between the device and carrier wafer. The debonding method uses the reversible thermal behavior of the thermoplastic material, meaning that at elevated temperatures the material experiences a drop in viscosity, which enables debonding to be accomplished by simply sliding the wafers off of each other. The character- istics of thermal slide-off debonding is bonding and debonding at elevated temperatures, which depending on the thermoplastic material being used can range between 130 and 350°C. Temperature stability depends in large part on mechanical stress, which can be observed due to the thermoplastic’s low viscosity at high temperatures [1].

Mechanical debonding is a method that is highly dependent on the surface properties of the wafers involved as well as the adhesion and cohesion of the temporary bonding material. For most material systems, a mechanical release layer is applied to achieve a controlled debonding mechanism. Key characteristics of mechanical debonding include processing at room temperature and a strong dependence on mechanical stress. Since mechanical debonding needs a low adhesion between the temporary bonding material and the wafer for a successful debond process, it can be tricky to use it for FoWLP applications. This is because the high wafer stress associated with FoWLP processing can lead to spontaneous debonding, even during the thinning process, which in turn can result in a drastic drop in yield [2].

Laser debonding is a technology that has been implemented with several different variations. The debond mechanism depends on the type of laser as well as the temporary bonding adhesive or the specific release layer used for the process. Infrared lasers work on the principle of the photo thermal process, where light is absorbed and transferred into heat, which leads to high temperatures within the bond interface. UV laser debonding typically uses the photo chemical process, where light is absorbed and the energy is used for breaking chemical bonds. Breaking the chemical bonds of a polymer results in the production of fragments of the original polymer. These fragments comprise gases, which increase the pressure within the interface to support the debonding process. For FoWLP applications, this method is a good fit due to the high adhesion of the temporary bonding adhesive to the wafers before the debonding process.

Optimized solution for FoWLP applications

UV lasers are advantageous for FoWLP processing due to their limited thermal input through the debonding process. The carrier wafer must be transparent to the UV laser’s wavelength to ensure efficient use of the laser energy and also ensure a higher lifetime of the carrier wafer. Two main types of UV lasers are available (solid-state laser and excimer laser), with each having several different wavelength options. Choosing a laser with a wavelength larger than 300nm is optimal for several reasons. First, commercially available laser debond materials effectively absorb and therefore debond at wavelengths higher than 300nm. Second, it allows a standard glass wafer to be used as the carrier since glass enables high transmission in this wavelength regime.

Solid-state lasers have the advantage of lower maintenance costs because they do not need halogen gas, which must be replaced on a regular basis. For solid-state lasers, the consumables are very low, and depending on the amount of power used by the laser there are examples of lasers used for laser debonding on a 24/7 basis that have required no laser consumables in the first five years of operation. Additionally, a smaller footprint can also be achieved due to a compact optical setup. Solid-state lasers typically have Gaussian beam profiles, pictured in FIGURE 3.

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UV laser debonding is a threshold process, meaning that debonding occurs above a certain value of radiant exposure. In Figure 3, the area with the blue criss-cross lines indicates the radiant exposure, which is used for the debonding process. The energy that is below or above that value (areas in red in the picture) cannot be used for debonding and is typically trans- ferred into heat, which can lead to carbonization and particle creation. Because of the lack of sufficient energy at the edge of the Gaussian laser beam profile, a certain overlap of the pulses is necessary, which is an additional variable that must be optimized in order to achieve successful debonding without carbonization. Additionally, the excess energy in the beam center can cause carbonization. A Gaussian beam profile is not suitable to limit thermal effects during debonding.

Gaussian beam profiles can be transferred into quasi top hat beam profiles by using a proprietary optical setup for beam shaping. By employing this optical setup, a highly reproducible beam for debonding (whereby the beam shape does not change over time) is achieved with constrained thermal input similar to what is seen in the “top hat” beam profile in FIGURE 4. This gives tighter process control, which in combination with the high pulse repetition rate of this laser type and the ability to scan across the surface of a fixed wafer leads to a well-controlled, high-throughput debonding process. The scanning process is pictured in FIGURE 5 where — in contrast to an excimer laser — the wafer is fixed on a static stage and the laser spot is controlled by a galvo scanner over the wafer. leads to a well-controlled, high-throughput debonding process.

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Screen Shot 2017-07-27 at 9.10.34 AM Screen Shot 2017-07-27 at 9.10.42 AMAs shown in FIGURE 6, a test wafer is used to determine the optimum radiant exposure for debonding. Even with a top hat beam profile, it is important to use a radiant exposure value close to the debonding threshold to minimize heat effects [3]. Small overlaps are necessary nonetheless because the adhesion between the temporary bonding material and the wafers is very high.

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Temporary bonding for future FoWLP

Ultrathin and stacked fan-out packages, also called Package on package (PoP), are already on several industry roadmaps due to their ability to enable higher device densities. However, the need for reconstituted wafers to become even thinner for PoP versus current FoWLP will give rise to more challenges for temporary bonding. For example, the bow of the temporary bonded wafer stack consisting of a molded wafer and a carrier wafer must be minimized to ensure uniform thinning. The maximum total thickness variation (TTV) will also become tighter depending on the final thickness. As for every 3D application, questions regarding interconnects, such as choosing via first or via last, also arises for PoP, where several processes are also available and where no standard process exists that is employed by all fan-out packaging houses.

Summary

UV laser debonding is a suitable method for both chip- first and chip-last/RDL-first FoWLP processes because it offers debonding at room temperature, and because chemically stable materials are available. The UV laser debonding solutions presented in this article combine the advantages of the solid-state laser with low mainte- nance, low consumables costs and high pulse frequencies combined with high spatial control due to the special beam-shaping optics.

Further Readings

1. Critical process parameters and failure analysis for temporary bonded wafer stacks. Karine Abadie, Elisabeth Brandl, Frank Fournel, Pierre Montméa, Wimplinger, Jürgen Burggraf, Thomas Uhrmann, Julian Bravin. Fountain Hills, Arizona: iMaps, 2016. iMaps Device Packaging Conference.

2. Temporary Wafer Carrier Solutions for thin FOWLP and eWLB-based PoP. Jose Campos, André Cardoso, Mariana Pires, Eoin O’Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA International, 2015. iWLPC (International Wafer Level Packaging Conference).

3. Key Criteria for Successful Integration of Laser Debonding. Elisabeth Brandl, Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber, Harald Wiesbauer, Mariana Pires, Philipp Kolmhofer, Matthias Pichler, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA Inter- national, 2016. iWLPC.

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released later this week), IC Insights addresses the changing landscape for semiconductor industry mergers and acquisitions.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in the past two years slowed to a trickle in the first half of 2017, with the combined value of about a dozen transactions announced in 1H17 reaching just $1.4 billion.

In the first halves of 2016 and the record-high M&A year of 2015, the combined value of acquisition agreements in 1H16 and 1H15 totaled $4.6 billion and $72.6 billion, respectively (Figure 1).  Last year, M&A got off to a slow start—compared to the record-breaking pace in 1H15—but several large transactions announced in 3Q16 pushed the 2016 total value in semiconductor acquisitions to nearly $100 billion and within striking distance of the all-time high of $107.3 billion set in 2015.  A few major semiconductor acquisitions were pending or rumored to be in the works during July 2017, but it is unlikely that a 2H17 surge in purchase agreements will bring this year’s M&A total value anywhere close to those of 2016 and 2015.

The big difference between semiconductor M&A activity in 2017 and the prior two years has been the lack of megadeals.  Thus far, only one transaction in 2017 has topped a half billion dollars (MaxLinear’s $687 million cash acquisition of analog and mixed-signal IC supplier Exar announced in March 2017 and completed in May).  There were seven announced acquisitions with values of more than $1 billion in 2016 (three of which were over $10 billion) and 10 in 2015 (four of which were over $10 billion).  IC Insights’ M&A list only covers semiconductor suppliers and excludes acquisitions of software and systems businesses by IC companies (e.g., Intel’s planned $15.3 billion purchase of Mobileye, an Israeli-based provider of digital imaging technology for autonomous vehicles, announced in March 2017).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for the 2017-2021 timeperiod.

Figure 1

Figure 1

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights addresses the amazing growth of the 2017 DRAM and NAND flash memory markets.

Sales of both memory types—DRAM and NAND—are expected to set record highs this year.  In both cases, the strong annual upturn in sales is being driven almost entirely by fast-rising average selling prices.  In the case of DRAM, unit shipments are actually forecast to show a decline this year.  Moreover, NAND shipments are forecast to increase only 2%, providing a small, added boost to the market growth in that segment. Prices for DRAM and NAND first began increasing in the second half of 2016, and continued with quarterly increases through the first half of 2017. Figure 1 plots the robust quarterly ASP growth rates, which, from 3Q16 through 2Q17, averaged 16.8% for DRAM and 11.6% for NAND.

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Figure 1

With DRAM ASPs surging since the third quarter of 2016, DRAM manufacturers once again stepped up their spending for this segment.  However, the majority of this spending is going towards technology advancements and not toward capacity additions.

IC Insights believes that essentially all of the spending for flash memory in 2017 will be used for 3D NAND flash memory process technology as opposed to planar flash memory.  A big increase in NAND flash capital spending this year is expected from Samsung as it ramps 3D NAND production at its large, new fab in Pyeongtaek, South Korea.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. Samsung, SK Hynix, Micron, Intel, Toshiba/SanDisk, and XMC/Yangtze River Storage Technology each plan to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market).  The likelihood of overshooting 3D NAND flash capacity over the next few years is very high.

IC Insights shows the DRAM quarterly ASP growth rate peaked in 4Q16 but continued a strong upward trend through 2Q17. IC Insights forecasts the DRAM ASP to increase (though marginally) into 3Q17 before edging slightly negative in 4Q17, signaling the end of another cyclical upturn.

Even though DRAM ASP growth is forecast to slow in the second half of the year, the annual DRAM ASP growth rate is still forecast to be 63%, which would be the largest annual rise for DRAM ASPs dating back to 1993 when IC Insights first started tracking this data.  The previous record-high annual growth rate for DRAM ASP was 57% in 1997.  For NAND flash, the 2017 ASP is forecast to increase 33%, also a record high gain. (In the year 2000, the predominantly NOR-based flash ASP jumped 52%).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for DRAM and NAND flash memory for 2017-2021 and includes a refreshed outlook on its semiconductor capital expenditure forecast.

Leti today announced that the European FP7 project PLAT4M has now been completed with results that exceeded expectations.

Si photonics has long been expected to bring substantial breakthroughs in very high speed data communications, telecommunications and supercomputing. In addition, it is one of the most promising industrial-production candidates because of its potential for large-scale and low-cost production capability in existing CMOS foundries.

The European Commission launched the 15-member PLAT4M project in 2012 to build a Si photonics supply chain in Europe that would speed industrialization of the technology by enabling its seamless transition to commercial production.

The main objective of PLAT4M was to advance existing silicon photonics research foundries and seamlessly transition to pilot line operation and industrial manufacturing of products based on silicon photonics. The supply chain is based on three different but complementary technology platforms of Leti, STMicroelectronics and imec.

Leti Platform

Leti’s 8,500m2 cleanroom facility includes a 200mm pilot line that enables fabrication of passives, detectors, modulators and integrated lasers with a focus on high-bandwidth devices. The project team developed a new Si-photonic platform based on a 310nm silicon film on top of an 800nm buried oxide (BOX) on a high-resistivity silicon substrate. Since the targeted applications for the project were O-band transceivers and receivers, most of the developed devices are suitable for 1310nm operations.

CEA-LETI has developed 3 PDKs which are dedicated to Multi Project Wafers (MPW) runs on this silicon photonics technology which is now offered via the brokers CMP and Europractice. Moreover, III-V Lab has designed and co-fabricated a state-of-the-art integrated hybrid III-V/Si transmitter using a wafer bonding technique on this platform.

STMicroelectronics Platform 

STMicroelectronics, the first 300mm wafer silicon photonics device manufacturer, is a key solution provider for 100 Gbps transceiver products since 2016. In parallel to its industrial activity, during the PLAT4M project ST developed another silicon photonics technology aimed at generating and nurturing further application specific industrial nodes. This technology platform creates an advanced photonic nanoscale environment, and combines state-of-the-art CMOS foundry tools with the flexibility necessary to support R&D efforts. Strong collaboration with research partners such as CEA LETI and University Paris Sud have been devoted to advanced studies in power consumption management, optical excess loss reduction and higher data-rate transmissions using complex modulation formats, signal multiplexing and higher Baud-rate devices. With R&D exploration that goes as far as core-to-core optical interposers, ST has also evaluated notions of device and circuit footprints toward Large System Integration (LSI).

In the context of PLAT4M, the participants chose a 4×25G transceiver as a Wavelength Division Multiplexing (WDM) data-communication demonstrator to validate both LETI and ST R&D platforms. The device functionalities were evaluated for compatibility with the 100GBase-LR4 standard, implying a signal transmission over 4 channels, spaced by 800 GHz around 1310 nm window, one fiber out and one fiber in.

imec Platform

In the course of the PLAT4M project imec has consolidated and further developed its silicon photonics technology platform ISIPP25G using its 200mm pilot line facilities located in Leuven to support industrial prototyping for various applications and markets. The imec platform component portfolio has been expanded to specific devices for sensing and high power free space applications. Furthermore, imec’s technology is supporting state-of-the-art modulation and detection at 50Gb/s and beyond with a variety of modulator options (GeSi EAM, Si MZM, Si MRM) now offered under its ISIPP50G technology along with both edge and surface fiber coupling technology and a library of O-Band and C-Band high quality passive components.

The technology is accessible through imec’s PDK, which is supported by software tools from several vendors including project partner PhoeniX Software. In collaboration with Mentor, a Siemens business, imec has also explored LVS verifications to reduce design errors and performed litho-friendly design analysis to improve the patterning predictability. Using the imec technology with new processing steps, TNO has demonstrated a multi-channel ring resonator based sensor system. Polytec demonstrated the operation of Multichannel Laser Doppler Vibrometer. THALES has demonstrated an integrated FMCW LiDAR system with 8 switchable output channels, enabling to scanning directions as well as a coherent beam combiner with 16 beams with linear operation up to a maximum input power of 26dBm. The thermal phase-shifter elements achieved a power efficiency of 10mW for a p-phase shift.

Finally, imec has demonstrated new advances in its technology such as a very low loss silicon waveguide technology (~0.6dB/cm for a 220nmx450nm waveguide) applying leading edge CMOS patterning technology developed in its 300mm pilot line with immersion lithography. It has also demonstrated a further reduction of thermal phase-shifter elements down to 4mW for a p-phase shift.

In an Unified Design Environment

The PLAT4M project has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. Mentor and PhoeniX Software have worked closely together on an integrated electronics/photonics co-design workflow. This has been accomplished by building on existing tool-sets wherever possible and developing new technologies when required.

The supply chain includes EDA solutions such as Mentor’s Pyxis™ and Calibre®, which were extended to “understand” photonics. Interfaces were developed between these tools and Photonic IC design solution OptoDesigner from PhoeniX Software to create integrated design flows using the best practices from both photonics and electronics design. In addition, process design kit elements were developed for Mentor’s Calibre DRC, Calibre LVS, and Pyxis tools, incorporating new components, added models and fabrication information.

Producing a Packaging toolkit 

Packaging played a key role in the development of the project demonstrators. The skills and processes developed by Aifotec and Tyndall, advanced the development of the Silicon Photonic packaging toolkit. This toolkit establishes standardised packaging processes for optical fibres, active devices, electronic components and thermo-mechanical systems to ensure that PICs can be more easily packaged in a timely and cost-effective way. A design rule document was made available through EuroPractice by Tyndall and also implemented into PDKs for OptoDesigner.

Perspectives 

“The consortium developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit,” said Jean-Marc Fedeli, coordinator of the PLAT4M project. “The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.”

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights forecasts that the 2017 global electronic systems market will grow by only 2% to $1,493 billion while the worldwide semiconductor market is expected to surge by 15% this year to $419.1 billion. Moreover, IC Insights forecasts that the total semiconductor market will exceed $500.0 billion four years from now in 2021.  If the 2017 forecasts come to fruition, the average semiconductor content in an electronic system will reach 28.1%, an all-time record (Figure 1).

Figure 1

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (0%), automobiles (2%), and PCs (-2%) forecast to be weak in 2017, the disparity between the slow growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2017 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and below average electronic system sales growth this year. After dipping slightly to 28.6% in 2020, the semiconductor content figure is expected to climb to 28.9% in 2021, an average yearly gain over the 2016-2021 timeperiod of about 0.8 percentage points.

Of course, the trend of increasingly higher semiconductor value in electronic systems has a limit. Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4% per year).  In IC Insights’ opinion, the “ceiling” is at least 30% but will not be reached within the forecast period.

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast data for 2017-2021.

Worldwide industrial semiconductor revenues grew by 3.8 percent year-over-year in 2016, to $43.5 billion, according to the latest analysis from business information provider IHS Markit (Nasdaq: INFO).

Industrial electronics equipment demand was broad-based, with continued growth in commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and various medical electronics such as cardiac equipment, hearing aids and imaging systems, IHS Markit said.

The U.S. economy continued to boost industrial spending while improved economic conditions in Europe and large emerging countries like China, India and Brazil toward the end of 2016 that propelled growth. These economic conditions are expected to continue thorough 2017, according to the IHS Markit analysis.

Top 20 company ranks: Global industrial semiconductor market share

Texas Instruments (TI) maintained its position as the largest industrial semiconductor supplier in 2016 followed by Intel, STMicroelectronics, Infineon Technologies and Analog Devices. Intel surged to second place, swapping spots with Infineon, which dropped to fourth. The Intel IoT group’s double-digit revenue growth is attributed to strength in factory automation, video surveillance and medical segments.

“Toshiba, ON Semiconductor and Microchip Technology climbed into the top 10 industrial semiconductor supplier ranks in 2016,” said Robbie Galoso, principal analyst, industrial semiconductors for IHS Markit. Toshiba’s industrial market share rank jumped to number six, according to survey feedback. Toshiba’s industrial electronics revenue grew from $1.1 billion in 2015 to $1.4 billion in 2016—a 30.5 percent bounce driven by discretes, microcomponent integrated circuits (ICs), memory and logic IC solutions in manufacturing and process automation, power and energy as well as security and video surveillance.

Mergers and acquisitions make an impact

The semiconductor industry had another cycle of merger and acquisition in 2016 that affected the competitive landscape. The combined ON Semiconductor – Fairchild organization generated $1.3 billion in 2016 industrial revenues, catapulting the consolidated company into seventh place. The acquisition of Fairchild allowed On Semiconductor to leapfrog to the top ranks of the power discrete market, forecast to be one of the higher growth markets over the next five years, IHS Markit said

On Semiconductor has been a relatively small player in the power discrete segment; with the Fairchild acquisition, it now has the scale and product portfolio to compete effectively with the combined Infineon International Rectifier. On Semiconductor’s 2016 revenue grew nearly 60 percent, largely driven by analog and discretes in the manufacturing and process automation and the power and energy sectors, both of which were sizeable segments for Fairchild.

The Microchip Technology – Atmel merger generated $1.2 billion in revenues in 2016, propelling the combined company into 10th place. The acquisition of leading microcontroller supplier, Atmel, positioned Microchip as the third-ranked supplier of microcomponent ICs in the industrial market, after Intel and TI. The combination of Microchip and Atmel created an MCU powerhouse, allowing it to compete effectively against the combined NXP Freescale. Microchip Technology’s 2016 revenue growth of 53 percent was driven by microcomponent ICs in manufacturing and process automation, Atmel’s bread and butter. Toshiba, Micron and ON Semiconductor displaced Nichia, Renesas and Xilinx in the top 10 rankings.

China’s massive investments in light-emitting diode (LED) manufacturing capacity propelled Chinese firm MLS into the 2016 top 20 industrial semiconductor supplier ranks, displacing Maxim. “MLS posted revenue growth of 27 percent, to $640 million, building its share against competition including top-20 firms Nichia, Osram and Cree,” added Galoso.

Strategic acquisitions will continue to play a major role in shaping the overall semiconductor market rankings in key industrial semiconductor segments. IHS Markit expects Analog Devices to increase its lead in 2017 market shares among the top semiconductor suppliers, due to an acquisition of Linear Technology. A joint Analog Devices – Linear Technology would battle for the number four spot and impressive gains in test and measurement, manufacturing and process automation as well as medical electronics.  Among the top 10 semiconductor suppliers, eight companies achieved growth in 2016, with two companies posting double-digit growth due to mergers.

industrial semi growth

Industrial semiconductor key growth drivers

Optical semiconductors delivered solid performance, driven by continued strength in the LED lighting market. IHS Markit expects the LED segment to grow from $9.4 billion in 2016 to $14.3 billion in 2021. With many countries phasing out incandescent bulbs, mass adoption of energy-efficient LED lighting solutions will continue to gain traction as prices for LED lamps fall to affordable levels for average-income households. Discrete power transistors, thyristors, rectifiers and power diodes are expected grow from $5.7 billion in 2015 to $8 billion in 2021 due to policy shifts toward energy efficiency in the factory automation market. IHS Markit projects that the microcontrollers (MCUs) segment  will grow robustly in the long term, expanding from $4.4 billion in 2016 to $7 billion in 2021, attributing this growth to both shipments and average selling price driven by system level cost savings provided by MCUs through advances in power efficiency and integration integrated features supporting connectivity, security, sensors and HMI.

CMOS image sensor sales are on pace to reach a seventh straight record high this year and nothing ahead should stop this semiconductor product category from breaking more annual records through 2021 (Figure 1), according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After rising 9% in 2017 to about $11.5 billion, worldwide CMOS image sensors sales are expected to increase by a compound annual growth rate (CAGR) of 8.7% to $15.9 billion in 2021 from the current record high of $10.5 billion set in 2016, based on the five-year forecast in the 360-page O-S-D Report, which covers more than 40 different product categories across optoelectronics, sensors and actuators, and discrete semiconductors.

Figure 1

Figure 1

After strong growth from the first wave of digital cameras and camera-equipped cellphones, image sensor sales leveled off in the second half of the last decade.  However, another round of strong growth has begun in CMOS image sensors for new embedded cameras and digital imaging applications in automotive, medical, machine vision, security, wearable systems, virtual and augmented reality applications, and user-recognition interfaces.

Competition among CMOS image sensor suppliers is heating up for new three-dimensional sensing capability using time-of-flight (ToF) technology and other techniques for 3D imaging and distance measurements.  ToF determines and senses the distance of faces, hand gestures, and other things by measuring the time it takes for light to bounce back to sensors from emitted light (often an infrared laser or LED).  CMOS technology has progressed to the point of supporting integration of ToF functions into small chip modules and potentially down to a single die.  Sony, Samsung, OmniVision, ON Semiconductor, STMicroelectronics, and others have rolled out and developed 3D image sensors. Infineon has also jumped into the image sensor arena with a 3D offering that is built in ToF-optimized CMOS technology.

Automotive systems are forecast to be the fastest growing application for CMOS image sensors, rising by a CAGR of 48% to $2.3 billion in 2021 or 14% of the market’s total sales that year, says the 2017 O-S-D Report.  CMOS image sensor sales for cameras in cellphones are forecast to grow by a CAGR of just 2% to $7.6 billion in 2021, or about 47% of the market total versus 67% in 2016 ($7.0 billion).  Smartphone applications are getting a lift from dual-camera systems that enable a new depth-of-field effect (known as “bokeh”), which focuses on close-in subjects while blurring backgrounds—similar to the capabilities of high-quality single-lens reflex cameras.

BY PETE SINGER, Editor-in-Chief

What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years? A Rolls Royce would cost only $40, go around the world eight times on a gallon of gas, and have a top speed of 2.4 million miles per hour.

That point was made by Subi Kengeri speaking at The ConFab in May. Kengeri is vice president, CMOS Business Unit, at GlobalFoundries. He also noted that if one of today’s high performance graphics chips were produced using 1960 vs state-of-the-art “it would be the size of a football field.”

Clearly, no other industry can match the pace of innovation of the semiconductor industry. “The transistor count per square inch in 1965 was roughly 100. In 52 years, if you follow Moore’s Law of 2 years per innovation cycle, that gives 26 innovation cycles. That’s 100 millionX improvement (2X26),” Kengeri noted.

Of course, there has been plenty of innovation in the automotive industry. Interestingly, most of the exciting new innovations such as backup cameras, collision avoidance, navigation/ infotainment, self-parking, and anti-lock brakes are only possible because of semiconductor technology.

Kengeri said that Moore’s Law scaling will continue – “there’s no question about it,” he said – but there’s a growing need for new innovation to address the increasingly diverse array of semicon- ductor applications. These are driven by growth in mobile computing, development in IoT computing, the emergence of intelligent computing and augmented/virtual reality.

“Leading edge innovation will continue and all the leading manufacturers continue to invest, whether it is litho scaling in terms of EUV, or device archicture,” Kengeri said. “What is really important is how do we continue to innovate, how do we continue to get the value at competitive costs? Trying to get the scaling at any cost is not what is needed in the majority of the markets. It’s still okay at the very high end, for CPUs and servers, but in all markets, managing cost is really critical.”

“On top of all of that, we have to continue to deliver on time. Because of the complexity, things aren’t getting slower. We’re doing everything we can do continue to keep the same pace as we used to,” he added.

Kengeri said continued advances mean changing the way we think about innovation. It will require continued technical Innovation (materials and processes, device architecture and design-technology co-optimization), but – perhaps more importantly – business model innovation. This includes new thinking about long-term R&D focus/ investment, shared investments/learning/reuse, and consolidation and collaboration.