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Qualcomm to acquire NXP


October 27, 2016

Qualcomm Incorporated (NASDAQ:  QCOM) and NXP Semiconductors N.V. (NASDAQ:  NXPI) today announced a definitive agreement, unanimously approved by the boards of directors of both companies, under which Qualcomm will acquire NXP.  According to Qualcomm’s official press release, a subsidiary of Qualcomm will commence a tender offer to acquire all of the issued and outstanding common shares of NXP for $110.00 per share in cash, representing a total enterprise value of approximately $47 billion.

NXP is a developer of high-performance, mixed-signal semiconductor electronics, with products and solutions and leadership positions in automotive, broad-based microcontrollers, secure identification, network processing and RF power.  As a semiconductor solutions supplier to the automotive industry, NXP also has leading positions in automotive infotainment, networking and safety systems, with solutions designed into 14 of the top 15 infotainment customers in 2016.  NXP has a broad customer base, serving more than 25,000 customers through its direct sales channel and global network of distribution channel partners.

“With innovation and invention at our core, Qualcomm has played a critical role in driving the evolution of the mobile industry.  The NXP acquisition accelerates our strategy to extend our leading mobile technology into robust new opportunities, where we will be well positioned to lead by delivering integrated semiconductor solutions at scale,” said Steve Mollenkopf, CEO of Qualcomm Incorporated.  “By joining Qualcomm’s leading SoC capabilities and technology roadmap with NXP’s leading industry sales channels and positions in automotive, security and IoT, we will be even better positioned to empower customers and consumers to realize all the benefits of the intelligently connected world.”

The combined company is expected to have annual revenues of more than $30 billion, serviceable addressable markets of $138 billionin 2020 and leadership positions across mobile, automotive, IoT, security, RF and networking.  The transaction has substantial strategic and financial benefits:

  • Complementary technology leadership in strategically important areas: The transaction combines leadership in general purpose and automotive grade processing, security, automotive safety sensors and RF; enabling more complete system solutions.
    • Mobile: A leader in mobile SoCs, 3G/4G modems and security.
    • Automotive: A leader in global automotive semiconductors, including ADAS, infotainment, safety systems, body and networking, powertrain and chassis, secure access, telematics and connectivity.
    • IoT and Security: A leader in broad-based microcontrollers, secure identification, mobile transactions, payment cards and transit; strength in application processors and connectivity systems.
    • Networking: A leader in network processors for wired and wireless communications and RF sub-segments, Wave-2 11ac/11ad, RF power and BTS systems.
  • Enhanced go-to-market capabilities to serve our customers:  The combination of Qualcomm’s and NXP’s deep customer and ecosystem relationships and distribution channels enables the ability to deliver leading products and platforms at scale in mobile, automotive, IoT, industrial, security and networking.
  • Shared track record of innovation and commitment to operational discipline: Both companies have demonstrated a strong commitment to technology leadership and best-in-class product portfolios with focused investments in R&D.  Qualcomm and NXP have both taken action to position themselves for profitable growth, while maintaining financial and operational discipline.  
  • Substantial financial benefits: Qualcomm expects the transaction to be significantly accretive to non-GAAP EPS immediately upon close.  Qualcomm expects to generate $500 million of annualized run-rate cost synergies within two years after the transaction closes.  The transaction utilizes Qualcomm’s strong balance sheet and will be efficiently financed with offshore cash and new debt. The transaction structure allows tax efficient use of offshore cash flow and enables Qualcomm to reduce leverage rapidly.

Mollenkopf continued, “We have taken significant action to build a foundation for profitable growth and the acquisition of NXP is strongly aligned with our strategy.  Our companies both have substantial expertise in delivering industry-leading solutions to our global customers, built upon a shared commitment to technology innovation, focused R&D investments and strong financial and operational discipline.”

“The combination of Qualcomm and NXP will bring together all technologies required to realize our vision of secure connections for the smarter world, combining advanced computing and ubiquitous connectivity with security and high performance mixed-signal solutions including microcontrollers. Jointly we will be able to provide more complete solutions which will allow us to further enhance our leadership positions, and expand the already strong partnerships with our broad customer base, especially in automotive, consumer and industrial IoT and device level security,” said Rick Clemmer, NXP Chief Executive Officer. “United in a common strategy, the complementary nature of our technologies and the scale of our portfolios will give us the ability to drive an accelerated level of innovation and value for the whole ecosystem. Such a strong fit will bring opportunities for our employees and customers, as well as provide immediate attractive value for our shareholders, in creating the semiconductor industry powerhouse.”

Sir Peter Bonfield, Chairman of NXP’s Board of Directors, said, “This is a major step in my ten years’ Chairmanship of NXP, and I am very pleased to see that the board of NXP has unanimously approved the proposed transaction and fully supports and recommends the offer for acceptance to NXP shareholders.”

IC Insights will release its October Update to the 2016 McClean Report later this week.  This Updateincludes a review of IC Insights’ latest 2016 IC market forecast, an update on the rebounding DRAM market, and an extensive analysis of the optoelectronics, sensor/actuator, and discrete (O-S-D) markets. An excerpt from the October Update, describing the upgraded 2016 IC market forecast, is shown below.

IC Insights has raised its IC market forecast for 2016 by three percentage points from a 2% decline to a 1% increase and its 2016 IC unit volume shipment growth rate forecast from 4% to 6%.  A large portion of this revision is due to a strengthening DRAM market.

Although the average third quarter sequential increase in the worldwide IC market since 2002 has been 8%, last year’s 3Q growth rate was barely positive with a meager 1% increase.  However, 3Q16 results were slightly above the past 15-year average and posted a strong 9% jump.  Moreover, with an anticipated increase of 1% next quarter, the total 4Q16 IC market is forecast to climb to $76.9 billion, a new quarterly record high, surpassing the previous high of $76.7 billion posted in 4Q14.

It should be noted that the average second half versus first half of the year growth rate in the IC market since 1990, including the forecast for 2016, is 8.9% (Figure 1).  However, IC Insights is forecasting that the 2H16 IC market will be up 12.3% as compared to 1H16, a strong turnaround from the extremely poor second half result of -1.2% posted last year and the highest second half growth rate since 2009.

With expectations for slightly better worldwide GDP growth in 2017 as compared to 2016 and continued firming of both DRAM and NAND memory prices, IC Insights believes that the worldwide IC market will grow by 4% next year (IC Insights’ detailed 2016-2020 IC market forecast by product type will be presented in the November Update).

history of ic growth

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2016–2018. The SEMI forecast shows polished and epitaxial silicon shipments totaling 10,444 million square inches in 2016; 10,642 million square inches in 2017; and 10,897 million square inches in 2018 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2015 and are forecast to continue shipping at record levels in 2017 and 2018.

“Silicon shipment volumes have been gaining strength in recent months, after a soft start at the beginning of the year,” said Denny McGuirk, president and CEO of SEMI. “This positive momentum is expected to continue and result in modest annual growth for the segment this year, 2017 and into 2018.”

2016 Silicon Shipment Forecast

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished Wafers

(Millions of Square Inches, MSI)

Actual

Forecast

2014

2015

2016

2017

2018

MSI

9,826

10,269

10,444

10,642

10,897

Annual Growth

11%

5%

2%

2%

2%

Source: SEMI, October 2016

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

This year again, both market segments, high end and low end, are the main targets of the TSV technologies providers. In its latest advanced packaging technology and market analysis entitled 3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update reportYole Développement (Yole) announces, high volume production started: 3D TSV is a reality, especially in the memory industry. Amongst a dynamic advanced packaging market showing an overall advanced packaging revenue CAGR estimated at 8%, rising to US$ 30 billion in 2020, the development of TSV platforms is still pushed by the need to the increase of performance, functionalities and integration; in addition, form factor and cost reduction are also part of the playground.

The More than Moore market research and strategy consulting company proposes today an overview of the 3D/2.5D IC packaging technologies per application. In addition to wafer forecast for 2015-2021 for different TSV applications, Yole’s analysts review the status of the current and future 3D IC products. They also describe and analyze the dedicated technology roadmap per device and highlight the organization of this market including supply chain activities, list of key players and OSAT and foundry strategies.

3D TSV technology is becoming a key solution platform for heterogeneous interconnection, high end memory and performance applications.

The higher end market segment is led by 3D stacked memories, 2.5D integration and emerging application such as photonics. From its side, the low end application includes CIS , MEMS devices and other sensors and new applications such as LEDs.

TSVs have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CIS, MEMS , sensors, and RF filters. In the near future they will also enable photonics and LED function integration.

“The market for 3D TSV and 2.5D interconnect is expected to reach around 2.1 million wafers in 2021, expanding at an 18% CAGR,” said Santosh Kumar, Senior Technology& Market Analyst at Yole. The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs.

CIS still commanded more than 80% share of TSV market wafer volume in 2015, although this will decrease to around 56% by 2021. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors. However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 38% of CIS production by 2021. The TSV markets for RF filters and fingerprint sensors are expected to reach around US$2.6 billion and US$0.7 billion by 2021 respectively.

Under this new report, Yole’s analysts also highlight the diversity of business models within the 3D & 2.5D TSV supply chain. They identify:
•  IDMs with Samsung, Micron, Freescale, Sony, Toshiba, STMicroelectronics…
•  OSATs including SPIL, Amkor Technology, ASE, Powertech…
•  CMOS foundries with TSMC, SMIC and more.
Si interposers suppliers, 3D packaging foundries and R&D services are also part of the business models identified by Yole’s analysts.
So will 3D TSV open the doors for new strategies? Indeed each player has its own approach:
•  Both OSATs, Amkor Technology and SPIL are strongly involved in the memory and the MEMS & Sensor market.
•  In parallel Samsung, an IDM, is well positioned in the CIS, Si interposer and LED market segments only.
•  In addition no foundries for memory products have been identified by Yole’s advanced packaging team.
Amongst the numerous 3D & 2.5D TSV players, Micron, SKHynix, Samsung, AMS and Avago Technologies are investing in capex…
A detailed analysis per player is available in Yole’s report, especially the OSATs and foundries strategies, that are willing to increase their market shares for TSV applications.

According to Yole’s analysts, 3DIC & 2.5D TSV continue its attractive growth. Under a dynamic ecosystem, a lot of valuable companies are involved in this field and propose innovative solutions. Because of the increasing consumer market, as well as the need for higher performance products such as 4K gaming, networking, 2.5D/3D TSV packaging platform becomes a key solution platform.

During the Electronics Packaging Technology Conference (EPTC) taking place from November 30 to December 3 in Singapore, Yole’s expert, Santosh Kumar will present his vision of the 3DIC & 2.5D TSV industry. His presentation is entitled: “What’s happening in TSV based 3D/2.5D IC packaging: Latest market & technology trends”. Discover the program and register on EPTC 2016.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $28.0 billion for the month of August 2016, an increase of 3.5 percent compared to the previous month’s total of $27.1 billion and an uptick of 0.5 percent over the August 2015 total of $27.9 billion. August marked the market’s largest month-to-month growth since May 2013 and its first year-to-year growth since June 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Following months of sluggish global semiconductor sales, the global market recently has shown signs of a rebound, punctuated by solid growth in August,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas market was particularly encouraging, topping 6 percent month-to-month growth for the first time in nearly three years to lead all regional markets. China also stood out, posting by far the strongest year-to-year growth of all regions in August. All told, global sales are still behind last year’s pace, but appear to be on the right track as 2017 draws closer.”

Month-to-month sales increased across all regions: the Americas (6.3 percent), Japan (4.8 percent), China (3.1 percent), Asia Pacific/All Other (2.7 percent), and Europe (0.7 percent). Year-to-year sales increased in China (7.1 percent) and Japan (2.2 percent), but fell in Asia Pacific/All Other (-2.7 percent), the Americas (-3.1 percent), and Europe (-3.3 percent).

 

August 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.10

5.43

6.3%

Europe

2.70

2.71

0.7%

Japan

2.60

2.73

4.8%

China

8.56

8.82

3.1%

Asia Pacific/All Other

8.12

8.34

2.7%

Total

27.08

28.03

3.5%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.60

5.43

-3.1%

Europe

2.81

2.71

-3.3%

Japan

2.67

2.73

2.2%

China

8.23

8.82

7.1%

Asia Pacific/All Other

8.57

8.34

-2.7%

Total

27.88

28.03

0.5%

Three-Month-Moving Average Sales

Market

Mar/Apr/May

Jun/Jul/Aug

% Change

Americas

4.79

5.43

13.2%

Europe

2.63

2.71

3.3%

Japan

2.55

2.73

6.9%

China

8.09

8.82

9.0%

Asia Pacific/All Other

8.00

8.34

4.2%

Total

26.07

28.03

7.5%

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business. An excerpt from the September Update, describing foundry sales by feature size, is shown below.

Figure 1

Figure 1

TSMC has long been the technology leader among the major pure-play foundries. As shown in Figure 1, 54% of TSMC’s 2016 revenue is expected to come from <40nm processing. GlobalFoundries, which has dedicated a large portion of its capacity to making advanced processors over the past few years, also generates a large portion of its sales based on leading-edge process technology and feature sizes. In 2016, 52% of GlobalFoundries’ sales are forecast to come from <40nm production.

Although GlobalFoundries and TSMC are forecast to have a similar share of their sales dedicated to <40nm technology this year, TSMC is expected to have almost 6x the sales volume at <40nm as compared to GlobalFoundries in 2016 ($15.6 billion for TSMC and $2.6 billion for GlobalFoundries). In contrast, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.

Because TSMC has a very large percentage of its sales targeting <40nm production, its revenue per wafer is forecast to increase at a CAGR of 3% from 2011 through 2016 as compared to a -1% CAGR expected for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC over this same timeperiod. Only 2% of SMIC’s 2016 sales are expected to come from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

It is interesting to note that the increase in pure-play foundry sales this year is forecast to be almost entirely due to <40nm feature size device sales (Figure 2). Although it is expected to represent 60% of total pure-play foundry sales in 2016, the ≥40nm pure-play IC foundry market is forecast to be flat this year. In contrast, the leading-edge <40nm pure-play foundry market in 2016 is expected to surge by 23%, increasing by a hefty $3.6 billion.

Figure 2

Figure 2

By David W. Price and Douglas G. Sutherland

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. 

Introduction

In a previous Process Watch article [1], we showed that big excursions are usually easy to detect but finding small excursions requires a combination of high capture rate and low noise. We also made the point that, in our experience, it’s usually the smaller excursions which end up costing the fab more in lost product. Catastrophic excursions have a large initial impact but are almost always detected quickly. By contrast, smaller “micro-excursions” sometimes last for weeks, exposing hundreds or thousands of lots to suppressed yield.

Figure 1 shows an example of a micro-excursion. For reference, the top chart depicts what is actually happening in the fab with an excursion occurring at lot number 300. The middle chart shows the same excursion through the eyes of an effective inspection strategy; while there is some noise due to sampling and imperfect capture rate, it is generally possible to identify the excursion within a few lots. The bottom chart shows how this excursion would look if the fab employed a compromised inspection strategy—low capture rate, high capture rate variability, or a large number of defects that are not of interest; in this case, dozens of lots are exposed before the fab engineer can identify the excursion with enough confidence to take corrective action.

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Unfortunately, the scenario depicted in the bottom of Figure 1 is all too common. Seemingly innocuous cost-saving tactics such as reduced sampling or using a less sensitive inspector can quickly render a control strategy to be ineffective [2]. Moreover, the fab may gain a false sense of security that the layer is being effectively monitored by virtue of its ability to find the larger excursions. 

Micro-Excursions 

Table 1 illustrates the difference between catastrophic and micro-excursions. As the name implies, micro-excursions are subtle shifts away from the baseline. Of course, excursions may also take the form of anything in between these two.

Table 1: Catastrophic vs. Micro-Excursions

Table 1: Catastrophic vs. Micro-Excursions

Such baseline shifts happen to most, if not all, process tools—after all, that’s why fabs employ rigorous preventative maintenance (PM) schedules. But PM’s are expensive (parts, labor, lost production time), therefore fabs tend to put them off as long as possible.

Because the individual micro-excursions are so small, they are difficult observe from end-of-line (EOL) yield data. They are frequently only seen in EOL yield data through the cumulative impact of dozens of micro-excursions occurring simultaneously; even then it more often appears to be baseline yield loss. As a result, fab engineers sometimes use the terms “salami slicing” or “penny shaving” since these phrases describe how a series of many small actions can, as an accumulated whole, produce a large result [3].

Micro-excursions are typically brought to an end because: (a) a fab detects them and puts the tool responsible for the excursion down; or, (b) the fab gets lucky and a regular PM resolves the problem and restores the tool to its baseline. In the latter case, the fab may never know there was a problem.

The Superposition of Multiple Simultaneous Micro-Excursions

To understand the combined impact of these multiple micro-excursions, it is important to recognize:

  1. Micro-excursions on different layers (different process tools) will come and go at different times
  2. Micro-excursions have different magnitudes in defectivity or baseline shift
  3. Micro-excursions have different durations

In other words, each micro-excursion has a characteristic phase, amplitude and wavelength. Indeed, it is helpful to imagine individual micro-excursions as wave forms which combine to create a cumulative wave form. Mathematically, we can apply the Principle of Superposition [4] to model the resulting impact on yield from the contributing micro-excursions.

Figure 2 illustrates the cumulative effect of one, five, and 10 micro-excursions happening simultaneously in a 1,000 step semiconductor process. In this case, we are assuming a baseline yield of 90 percent, that each micro-excursion has a magnitude of 2 percent baseline yield loss, and that they are detected on the 10th lot after it starts. As expected, the impact of a single micro-excursion is negligible but the combined impact is large.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

It is interesting to note that the bottom curve in Figure 2 would seem to suggest that the fab is suffering from a baseline yield problem. However, what appears to be 80 percent baseline yield is actually 90 percent baseline yield with multiple simultaneous micro-excursions, which brings the average yield down to 80 percent. This distinction is important since it points to different approaches in how the fab might go about improving the average yield. A true baseline yield problem would suggest that the fab devote resources to run experiments to evaluate potential process improvements (design of experiments (DOEs), split lot experiments, failure analysis, etc.). These activities would ultimately prove frustrating as the engineers would be trying to pinpoint a dozen constantly-changing sources of yield loss.

The fab engineer who correctly surmises that this yield loss is, in fact, driven by micro-excursions would instead focus on implementing tighter process tool monitoring strategies. Specifically, they would examine the sensitivity and frequency of process tool monitor inspections; depending on the process tool, these monitors could be bare wafer inspectors on blanket wafers and/or laser scanning inspectors on product wafers. The goal is to ensure these inspections provide timely detection of small micro-excursions, not just the big excursions.

The impact of an improved process tool monitoring strategy can be seen in Figure 3. By improving the capture rate (sensitivity), reducing the number of non-critical defects (by doing pre/post inspections or using an effective binning routine), and reducing other sources of noise, the fab can bring the exposed product down from 40 lots to 2.5 lots. This, in turn, significantly reduces the yield loss and yield variation.

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Summary

Most fabs do a good job of finding the catastrophic defect excursions. Micro-excursions are much more common and much harder to detect. There are usually very small excursions happening simultaneously at many different layers that go completely undetected. The superposition of these micro-excursions leads to unexplained yield loss and unexplained yield variation.

As a yield engineer, you must be wary of this. An inspection strategy that guards only against catastrophic excursions can create the false sense of security that the layer is being effectively monitored—when in reality you are missing many of these smaller events that chip away or “salami slice” your yield.

References:

About the Author: 

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry industry and a look at the current state of the merger and acquisition surge in the semiconductor industry. An excerpt from the M&A portion of this Update is shown below.

After an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions has eased (until recently), but 2016 is already the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion. As of the middle of September, announced semiconductor acquisition agreements this year have a combined value of $55.3 billion compared to the all-time high of $103.8 billion reached in all of 2015 (Figure 1). Through the first three quarters of 2015, semiconductor acquisition pacts had a combined value of about $79.1 billion, which is 43% higher than the total of the purchasing agreements reached in the same period of 2016, based on M&A data compiled by IC Insights.

In many ways, 2016 has become a sequel to the M&A mania that erupted in 2015, when semiconductor acquisitions accelerated because a growing number of suppliers turned to purchase agreements to offset slower growth in major existing end-use equipment applications (such as smartphones, PCs, and tablets) and to broaden their businesses to serve huge new market potentials, including the Internet of Things (IoT), wearable electronics, and strong segments in embedded electronics, like highly-automated automotive systems. China’s goal of boosting its domestic IC industry is also driving M&A. In the first half of 2016, it appeared the enormous wave of semiconductor acquisitions in 2015 had subsided substantially, with the value of transactions announced between January and June being just $4.3 billion compared to $72.6 billion in the same six-month period in 1H15. However, three large acquisition agreements announced in 3Q16, including SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil) have insured that 2016 will be second only to 2015 in terms of the total value of announced semiconductor M&A transactions.

Figure 1

Figure 1

A major difference between the huge wave of semiconductor acquisitions in 2015 and the nearly 20 deals being struck in 2016 is that a significant number of transactions this year are for parts of businesses, divisions, product lines, technologies, or certain assets of companies.  This year has seen a surge in the agreements in which semiconductor companies are divesting or filling out product lines and technologies for newly honed strategies in the second half of this decade.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

By Ted Shafer, Business Manager, Mature Product Sales, ASML

Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group. Your next opportunity to catch up on latest trends on ≤200mm manufacturing trends and its impact on the secondary equipment and applications market is SEMICON Europa 2016 and the Secondary Equipment Tech Arena session

Wednesday July 13th at SEMICON West a seminar and panel discussion were held to discuss the longevity and growth of the 200mm equipment market, and responses from IDMs, OEMs and 3rd parties to the challenges this growth presents.

Tim Tobin of Entrepix was the first speaker.  Entrepix is a premier 3rd party refurbisher of CMP and other process equipment.  Tim was the first to remark on a phenomenon that the other speakers and panelists also noted: a huge portion of the die in the devices we use daily do not require state of the art 300mm manufacturing.  For example, 60% – 80% of the chips in your smartphone or tablet are manufactured on 200mm – or smaller – wafers.  These wafers are created using mature equipment, which is frequently purchased from the secondary market, often from refurbishers such as Entrepix.

SEMI’s Christian Dieseldorff next provided a great overview of 200mm market trends, titled “200mm Fab: Trends, Status, and Forecast”.  Driven by the growth of IoT (Internet of Things), new 200mm fabs are being built and additional capacity is being added at existing fabs.  Key take-away is that after peaking in 2006, then declining for several years, 200mm wafer starts per month are now forecasted to exceed 2006’s level of 5.4M by 2019.  The question on everyone’s mind is, once that level is exceeded, where will the tools come from to manufacture those wafers?

200mm-image1

Pierric Gueguen of Yole spoke of the increased adoption of exotic substrates like GaN, Sapphire and Silicon Carbide.  These substrates provide many performance advantages, such as lower power consumption, faster switching speed, and high temperature resistance.  Yet the substrates cannot scale to 12”, and sometimes not to 8”.  So the increased adoption of these substrates is driving additional demand for 150mm/200mm tools.

As a counter-point to the 200mm discussions, Karen Erz of Texas Instruments gave a very well-received presentation on TI’s pivot to 300mm for analog, which has traditionally been manufactured on 200mm wafers.  A key to TI’s success is to embrace without fear buying opportunities for used equipment when they present themselves.  TI does not compete at the leading edge – their minimum feature size is 130nm – and thus mature, pre-owned, cost-effective equipment is always their first choice.  In fact, surplus 300mm is often more available, and less expensive, than comparable 200mm tools.  TI capitalized on the bankruptcies of the 300mm fabs of Qimonda Dresden, Qimonda Richmond, and PROMOS, also surplus tools at Powerchip, to scoop up large batches of inexpensive 300mm tools.  They continue to buy surplus 300mm tools when they come on the market, even in advance of actually requiring the tools.  As a result, 92% of RFAB’s analog production is done with pre-owned 300mm equipment.

Emerald Greig of Surplus Global, in addition to organizing the seminar, also provided a well-researched presentation on surplus equipment trends, titled “The Indispensable Secondary Market”.  Surplus Global is one of the largest surplus equipment traders, and they track the used equipment market very closely.  Emerald discussed how the supply of tools per year is trending dramatically downwards.  In 2009 they saw 6,000 tools come on the market, and that run-rate has steadily decreased to the point where by last year it was under 1,000/year.  This year we are at just 600.

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AMAT’s John Cummings provided the first OEM perspective on the 200mm market.  John showed how over 70% of the chips in the segments of automotive, wearables and mobile are produced on <=200mm wafers.  These segments are growing – for example a BMW i3 contains an astonishing 545 total die, and 484 of them are manufactured on <=200mm wafers.   AMAT reports that there are not enough used 200mm tools on the market to support the demand, and thus AMAT supplies their customers with new 200mm tools to augment the upgrades and refurbs they perform on pre-owned tools.  AMAT also provides new functionality for their mature 200mm products, increasing their usefulness and extending their lifetime.

Finally there was the OEM panel discussion, consisting of Kevin Chasey of TEL, David Sachse of LAM, Hans Peters from Ebara, and Ted Shafer of ASML.  Emerald Greig of Surplus Global provided some initial questions and solicited additional ones from the audience.   The OEMs echoed one common theme of the presentations, that 200mm demand is robust, and core tools are increasingly hard to find.  TEL additionally noted that China is a growing player in this market, and that OEMs must now support their 200mm product lines much longer than initially planned.  LAM said that 200mm core supply is so tight that the prices are rising above even comparable 300mm cores.  In response, LAM augments the supply of used tools by creating new 200mm tools.  Ebara added that the core tools coming on the market are often undesirable first-generation tools or tools in very bad condition.  On the other hand, this creates a role for the OEM, who has the expertise to make these tools production-worthy.  ASML noted that many of their larger 200mm customers are considering a migration from the PAS 5500 platform to ASML’s TWINSCAN platform for 200mm production.  Although developed for 300mm, and in general larger and more expensive than the 200mm 5500 series, ASML has spent the last 15 years making TWINSCANs increasingly productive and reliable, to the point where they often offer superior cost of ownership at 200mm than ASML’s 5500 platform.  Furthermore, customers buying TWINSCAN for 200mm production have an easy upgrade to 300mm when/if their plans call for it.

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In summary, the seminar showcased a robust exchange of ideas, where the presenters and panelists examined the resurgent 200mm market, and described many solutions to the common challenge of limited and expensive 200mm cores.

Attend SEMICON Europa and the Secondary Equipment & Applications session on October 26 to find out the latest trends and discuss in what areas OEMs, IDMs and secondary  market operators can cooperate more closely to improve sustainable access to legacy manufacturing equipment.

Find out more about SEMI’s Secondary Equipment and Applications Special Interest Group and the Secondary Equipment Legacy Management Program that is currently under development. For more information and to get involved, contact [email protected] (Ms. Rania Georgoutsakou, Director Public Policy for Europe, SEMI).