Tag Archives: letter-ap-top

By Yoichiro Ando, SEMI Japan

The 2016 global semiconductor market is forecast to decrease by 2.4 percent from the previous year according to the World Semiconductor Trade Statistics (WSTS). SEMI forecasts that the global semiconductor manufacturing equipment market will be effectively flat this year. However, SEMI also forecasts double-digit growth in 2017 with significant new fab construction starts in 2016 and 2017 that will drive later equipment. The forecast foresees the Japan market will shrink through 2017. This article provides insight behind those forecast numbers.

Overview

Large-scale investments in 300mm wafer lines in Japan are primarily made by three companies: Toshiba (NAND Flash), Sony (image sensors) and Micron Memory Japan (DRAM). The logic players’ investments are largely for upgrading and expanding existing capacity; the companies producing power, surface acoustic wave (SAW), and automotive semiconductor devices are actively adding capacity by constructing new fabs and expanding existing fabs. These activities are planned on 200mm or smaller wafers, so the investments are smaller in terms of dollar values. However, they are important to Japan’s semiconductor industry in the coming Internet of Things (IoT) age.

Toshiba plans a new mega fab

Toshiba continues to expanding its 300 mm NAND fabs in Yokkaichi in 2015 and 2016 ─ including the second phase construction of Fab 5, new Fab 2 for 3D NAND flash memory production, and plan for a new fab (Fab 6).

Toshiba New Fab 2

Toshiba’s new Fab 2 cleanroom (Source: Toshiba)

The new Fab 6 will be dedicated to 3D NAND flash memory production, and is planned to be built in an adjacent area of the current Yokkaichi factory site. Detailed plans of the construction (such as construction period, production capacity, and investment to manufacturing instrument used) will be decided in FY 2016 based on market trends. Fab 6 is expected to be built in FY 2017. Production capacity of the fab is projected to be more than 200,000 wafers per month (300mm wafers) at full capacity.

Toshiba and Western Digital announced a plan in July 2016 to invest a total of 1.5 trillion JPY for the next three years in Yokkaichi operations. This investment will be for the construction of the new fab as well as for updating equipment for existing fabs such as new Fab 2 and Fab 5.

Sony expands 300mm capacity

Sony is also actively expanding its 300mm wafer fabs for increased production of complementary metal-oxide-semiconductor (CMOS) image sensors. Sony plans to expand production capacity not only with its existing lines but also to acquire fabs from other companies. Specifically, Sony acquired Tsuruoka factory in Yamagata prefecture in 2014 from Renesas Electronics Corporation, and it is now operated as Yamagata Technology Center (TEC) of Sony Semiconductor Manufacturing Corporation, which is a semiconductor production subsidiary of Sony Corporation. In 2015, Sony acquired the 300mm line of the Toshiba Oita factory, for production of CMOS image sensors.

Sony plans to invest 70 billion JPY in FY 2016, and expand image sensor production capacity ─ now 70,000 wafers per month as of first quarter of 2016. The restoration of Kumamoto TEC damaged by the Kumamoto earthquake would make investment in other TECs decrease.

Micron and TowerJazz

Micron Technology operates a 300mm fab in Hiroshima (Micron Memory Japan Fab 15). The fab manufactures DRAM with 12nm process technology. Micron invested US$750 million in 2015 and $500 million in 2016 for the technology upgrades. The capacity has been flat in these two years.

Panasonic TowerJazz Semiconductor, a Panasonic and TowerJazz joint venture, operates a 300mm foundry fab in Uozu. The company invested $10 million in 2015 and plans to invest the same amount in 2016 to improve the productivity.

Investments in 200mm and smaller wafer lines

Other major semiconductor manufacturers primarily invest in existing fabs and lines for maintenances and productivity improvements. Therefore, investment amount is modest. However, these fabs will be the major source for semiconductor devices of the Internet of Things applications.

  • Renesas Electronics Corporation plans upkeep of production capacity of Kumamoto fab (200mm wafer fab) and Naka fab (300mm wafer fab).
  • Fujitsu enhances Fab B2 of Mie Fujitsu Semiconductor Limited, which provides foundry services with 300mm wafer lines. Taiwan’s major foundry UMC participated in capital of Mie Fujitsu Semiconductor Limited, and assists with 40nm process technology.
  • Rohm Co., Ltd. plans to invest more than 10 billion JPY in enhancement of 200mm lines of fab and others in the headquarters.
  • Fuji Electric Co., Ltd. continues enhancement of its 200mm wafer lines for IGBT of Yamanashi plant in FY 2016. Fuji Electric further expands its SiC power device production capacity by enhancing 200mm wafer lines at Matsumoto fab.
  • Mitsubishi Electric Corporation manufactures power devices at 200mm wafer line of Kumamoto fab. Mitsubishi Electric continues enhancement of power device production capacity.
  • Shindengen Electric Manufacturing Co., Ltd. is enhancing its power semiconductor module production by adding a new line each for Akita Shindengen Co., Ltd. and Higashine Shindengen Co., Ltd. from FY 2015.

Electronic Parts and Optoelectronic Devices

The electronic parts companies are emerging as new fab owners in Japan. Their recent activities are summarized below:

  • New Japan Radio Co., Ltd. continues enhancement of production capacity of SAW devices and GaAs ICs at its Kawagoe fab in 2016.
  • Hamamatsu Photonics K.K. continues enhancement of MEMS fabrication facility (Fab 13) which started operation in March 2014.
  • Upkeep of new clean room of Toyota Motor Corporation, which started operation in 2014, is now underway. Currently, this line is used for research and development, and trial production of SiC devices.
  • Murata Manufacturing Company, Ltd. is building a new fab for SAW filter production at its headquarter factory in Toyama. The new fab construction will be completed in September 2016. Total investment to the facility is planned to be 12 billion JPY. Then it will be equipped with 200 mm (mostly secondary) equipment.
  • Taiyo Yuden Co., Ltd. continues its enhancement plan of Oume fab in FY 2016, which was acquired from Hitachi in 2013 for SAW device production.
  • TDK agreed to acquire 125mm wafer lines in Tsuruoka Factory from Renesas Electronics Corporation in November 2015. TDK plans to enhance its production capacity of super miniature electronic components at this plant. Production will start in FY 2016 after replacement of manufacturing equipment to conform to products to be manufactured. Investment will continue in FY 2016 as well for startup of the mass production and maintenance at this plant.

SEMI World Fab Forecast

To obtain line-by-line investment and capacity trends in Japan and other regions in the world, SEMI Fab Forecast is a powerful and affordable tool. The report is in easy to use, with Excel spreadsheet format that covers six quarters of actual data and six quarters of forecast on over 1,000 fab/lines. For further information, please see www.semi.org/en/MarketInfo/FabDatabase.

Connect with Japan Semiconductor Industry at SEMICON Japan
SEMICON Japan (December 14-16, Tokyo) offers excellent opportunities to interact and connect with the Japan semiconductor industry. To join the exhibition, please see www.semiconjapan.org/en/exhibit.

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Worldwide silicon wafer area shipments increased during the second quarter 2016 when compared to first quarter 2016 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,706 million square inches during the most recent quarter, a 6.6 percent increase from the 2,538 million square inches shipped during the previous quarter. New quarterly total area shipments are 0.1 percent higher than second quarter 2015 shipments and are at their highest recorded quarterly level.

“Silicon shipment growth continues to gain momentum resulting in a quarterly volume shipment high,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “Although year-to-date shipments are effectively flat relative to the same period as last year.”

Silicon* Area Shipment Trends

Millions of Square Inches

2Q2015

1Q2016

2Q2016

1H2015

1H2016
Total

2,702

2,538

2,706

5,339

5,243

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

By Pete Singer, Editor-in-Chief

Last year, Rudolph Technologies, Inc. announced the widespread adoption and success of its newest macro defect inspection tool, the NSX® 330 Series. The NSX 330 Series provides high-speed macro defect inspection with 2D\3D metrology for advanced packaging applications, which are being developed primarily to support mobility. The company said it had been “quickly and enthusiastically adopted,” garnering repeat orders from top foundries, integrated device manufacturers (IDMs) and outsourced assembly and test (OSAT) manufacturers.

The NSX 330 Series offers an array of metrology capabilities for both 2D and 3D metrology applications, including 100 percent bump height and coplanarity measurements. The NSX 330 series has now been further improved by incorporating a high speed bump laser triangulation sensor and the highly accurate VT-SS distance and thickness sensor. “We specifically offer these capabilities on a single platform because they improve total measurement accuracy on complex materials which have troubled the industry for some time,” said Scott Balak, director, inspection product management, Rudolph Technologies Inc. (Bloomington, MN).

Figure 1 illustrates the problem. The goal is to measure the actual bump height and overall coplanarity from bump top to polyimide (PI) surface. If one or more bumps are too high or too low, the other bumps won’t connect. A high-speed laser triangulation sensor attempts to see through the polyimide (PI) layer, which is typically 3-6 microns thick. “The problem is that polyimide isn’t completely transparent, so when the triangulation sensor attempts to detect the bottom of this PI layer, it is actually finding it somewhere in the middle. The current industry’s work around is to assume a PI thickness and apply a PI layer offset; however, PI thickness variation limits the accuracy of this approach,” Balak explained.

Figure 1

Figure 1

Inaccurate measurements create unnecessary review work. Because bumps may have acceptable coplanarity, but they are incorrectly flagged for further evaluation. “Customers use the review mode to determine if the bump is actually too big, or too small” Balak said.

Enter Rudolph’s Visible Thickness and Shape Sensor (VT-SS) sensor, which can concurrently measure the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This is achieved through the integration of reflectometry and visible light interferometry principles. The direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature.

“Rudolph samples multiple bumps with both the laser triangulation and VT-SS sensors to accurately obtain a measurement average of wafer PI thickness while simultaneously calibrating the triangulation sensor with an accurate PI offset for the specific wafer being measured.,” Balak said. “The properly calibrated triangulation sensor then quickly and accurately measures millions of bumps per wafer correctly flagging bad bumps and eliminating the need to review good product. Wafer results are then sent to our Discover Analysis solution where customers can analyze correlations between defectivity and process metrology to improve the overall process. Whether it is understanding wafer and lot level trends or specific individual bumps; Discover provides the drill down capability required for root cause analysis.”

By Pete Singer, Editor-in-Chief

Fan-out wafer level packaging (FOWLP) is gaining traction, leading to higher I/Os and larger formats, and new mobile displays are pushing the limits of pixel per inch (PPI) while also moving to larger formats. Both trends are driving new requirements for lithography equipment, including steppers, track systems and photoresists. Both packages and displays are employing new types of materials and thinner substrates as well. “There’s a lot of commonality between the advanced display technologies and packaging technologies,” said Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “The step-and-repeat system approach is ideally suited to address those challenges.”

Key lithographic challenges of advanced packaging and displays are shown in Figure 1.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Rogoff said another big challenge is the ability to manage what he calls dimensionally unstable material. “These are materials that change with time, with temperature, with humidity and with process steps, every time they come back through a lithography step they can change form. Steppers have to be able to deal with that,” he said.

Rogoff also said he’s seeing changes in imaging chemistries which are creating another challenges. “We’re doing things now from broadband resist to i-line resist, from thin-films to thick films, to dry films to organic chemistries. It’s all over the field here with respect to what types of chemistries are being used to image, and the challenge is of course when going from a thick material to a thin material and varied compositions, you get a much different kind of imaging characteristic. Really you need to be able to manage all of those without having to change your lithography system,” he said.

In packaging applications, large topography is yet another challenge. In a fan-out type of situation, there can be significant differences in heights between the substrate and the die, for example. “You’re having to image through, in some cases, >20 microns of photoresist for a two or three micron line, and that becomes a very big challenge,” Rogoff said. “The package size and the display sizes are also getting bigger, and so you need to try to get as much as you can into one imaging field. The lenses need to have a very large field of view.”

FOWLP, where individual die are connected on redistribution layer, is expected to lead to a major change in process equipment. Today, die are “reconstituted” on a wafer. In the future, as volume increases, a move to high density panels is expected. “As the demand goes up, certainly panels make the most sense,” Rogoff said.

Earlier this year, Rudolph announced that a leading outsourced assembly and test facility (OSAT) has placed an order for the JetStep Lithography System for the semiconductor advanced packaging industry’s first panel manufacturing line. “That’s the first true panel fan-out application that’s moving forward, especially in the OSAT world,” Rogoff said.

While the stepper part of the litho equation is ready for “panelization,” the rest of the industry infrastructure is working from two directions. One, from printed-circuit board type solutions where thick resist are dry films. The other, from the display side, uses thin chemical resists. “Somehow we have to bridge the gap between a thin film and a thick film,” Rogoff said. “These are some of the infrastructure things that are still being worked out, but I think those are relatively easy to solve.”

Elvino da Silveira, Rudolph’s vice president of marketing, said he’s seen some recent changes. “Last year, when we were talking to the various customer and partners that we interact with in terms of the panel level fan out, everybody was really focused on doing reconstituted panels, the face-down type chips. Basically taking the EWLB process and scaling it up to the panel level. As time has gone on, and with TSMC bringing out InFO and so forth, there have been several players that are more open to doing this on a carrier. It adds some costs, but at least based on the general feedback we’ve gotten from some of the industry , scaling up to the larger substrate offsets the additional cost of the carrier,” he said.

Figure 2 (presented at SEMI’s Industry Strategy Symposium in January by Babak Sabi, corporate vice president, director, assembly and test technology department, Intel Corp.) shows the expected progression of packaging technology as IO density increases. Flip chip, ball grid array on the left (the orange box) has 15-60 micron feature sizes depending on the layer and the type of feature being exposed.

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

The next generation, (the yellow box) indicates fan out packaging. “We’re still more towards that boundary between the orange and the yellow, because really no one’s producing sub-five microns in HVM today. Most of it is between 5 and 10,” da Silveira said.

The next level (the green box) indicates embedded technology, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB). Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. Here, the IOs are getting much higher, and the feature sizes are getting pushed toward two microns. As technology moves from the yellow box to the green box, expect a switch from wafers to panels.

By Jean-Eric Michallet, Leti Vice President for Sales and Marketing

The pervasiveness of the Internet of Things (IoT) and its connections ranging from $1 objects to connected cars requires security to be reliable, simple, safe and affordable. Because the Internet of Things is made up of objects (hardware) connected to a network (software), security has to be factored in from the application or use’s conception. In short, assuring IoT security will require strategies to manage the entire value and supply chains.

Attendees at the recent Leti Innovation Day 2016 in Lyon, France, heard several variations of that message from industry experts and Leti scientists, against a backdrop of a proliferation of security and data threats.

Didier Lamouche, CEO of Oberthur Technologies, a provider of embedded security software products and services, noted industry forecasts of 10 billion connected devices shipped annually by 2020. This amounts to an exponential increase in security risks, as well. “This is the wave we have to catch,” he said.

Security is a brand problem

Recalling the 2013 data breach at Target in the U.S., in which 40 million credit and debit card numbers and 70 million items of customer personal information were compromised, Lamouche said that cybersecurity is not only a problem for security officers and CIOs. It has become a problem for CEOs and board of directors, as the 2014 resignation of Target CEO Gregg Steinhafel showed. In fact, he said, cybersecurity is becoming a brand problem, because of the severe damage fraud and data breaches can cause for a company.

Retail is not the only at-risk industry. Lamouche noted that more than 76 million Sony PlayStation user accounts were breached and 3.6 million connected vehicles in the U.S. and Europe have been hacked.

In recent years, “card not present” (CNP) transactions, primarily online purchases, accounted for approximately 65 percent of fraud in Europe, Australia and Canada, and 49 percent in the U.S., which still amounted to $6 billion in 2014.

Credits cards with continuously updated security codes

To address the growth of CNP fraud, Oberthur has developed MOTION CODE for credit card issuers. It secures online transactions by automatically and randomly updating a cryptogram security code on the back of the card. If the card is lost or stolen, it can be rendered useless quickly.

Keynoting the session on “Strengthening Security with Advanced Technologies,” Jean-Marie Saint-Paul, Europe application director for Mentor Graphics, outlined numerous security challenges involving hardware. 

Who can you trust?

Thieves looking for ways to steal money, companies looking for competitors’ vulnerabilities and even users “playing” with the system can create risks. The supply chain presents numerous risks, as well. Specific hardware challenges include:

  • A “vast space” of possible intrusions during IC, printed circuit board and embedded design and in the supply chain
  • Unknown bugs and frequent field updates that open back doors for attackers
  • The “fading of a trusted foundry” and proposed solutions that may not be viable
  • Counterfeit ICs that cause economic loss similar to yield loss discovered much later
  • For mission-critical apps, fake ICs that compromise devices risking security and safety

“Whatever structure we put in place, we have to put it in place with something we trust,” he said.

Digital disruption across the board

Borrowing information from IBM, Saint-Paul closed his presentation with a slide that highlights some of the most disruptive changes in business, industry and society at large that digital technology has enabled.

  • World’s largest taxi company owns no taxis (Uber)
  • Largest accommodation provider owns no real estate (Airbnb)
  • Largest phone company owns no telco infrastructure (Skype)
  • World’s most valuable retailer owns no inventory (Alibaba)
  • Most popular media owner creates no content (Facebook)
  • Fastest-growing banks have no actual money (SocietyOne)
  • World’s largest movie house owns no cinemas (Netflix)
  • Largest software vendors don’t write apps (Apple, Google)

The slide also asked when disruption will happen in semiconductors and electronics, when the world’s largest trusted foundry will own no fab or equipment, the top trusted contract manufacturer will own no assembly line and the leading secure electronics supplier will not purchase boards or chips. Will it be true? Maybe not, Saint-Paul said, but the industry needs some new models to reinvent itself.

Sameer Sharma, general manager of Intel’s IoT Group, said the IoT will provide pervasive, real-time intelligence from the physical world to data centers and the cloud: mobile devices via networks, and industrial and home applications via gateways. He cited a projection of 50 billion devices sharing 44 zetabytes of data.

Intel and Leti recently signed a multi-year collaboration agreement involving a variety of subjects such as making the IoT more secure, enabling 5G networks and device innovation, and driving the future of high-performance computing. 

85 percent of systems not connected

Combining revealing statistics from the past with projections about the direction the industry is headed, Sharma noted that the rapidly evolving digital era is spurring transformation across many fields, supported by a shift to open standards. Fixed-function ASICs are giving way to programmable architectures, dedicated appliances are now parts of virtualized systems, and purpose-built hardware is transforming into general-purpose hardware and software-defined functions.

Dramatically declining costs are a key driver for this transformation. In the past 10 years, the costs for sensors have fallen 2x, the cost of bandwidth has dropped 40x and the cost of processing 60x.

One of the most arresting facts Sharma shared relates to the huge potential, and need, for more hardware and software systems to keep up with the exponential growth of connected devices. Eighty-five percent of deployed systems are not connected and do not share data with each other or the cloud.

IoT threat landscape

Even so, Sharma said, attacks on IoT devices will increase rapidly due to hyper-growth in the number of connected objects, “poor security hygiene” and high value of data on those devices. A recent study of IoT devices showed that an average of “25 holes or risks of compromising the home network” were found on every device evaluated.

Sharma outlined a path to IoT security paved by infrastructure, end-to-end security, and 5G network and connectivity and standards. He said the Intel IoT Platform offers secure, scalable and interoperable building blocks for data acquisition, analytics and actions to improve business and peoples’ lives. Like other speakers, Sharma emphasized that security must be part of system concept and design.

“Security cannot be an add-on. Those days are gone,” he said.

Devices to protect biological, radiological and chemical data

Leti’s Alain Merle noted that privacy and security far outweigh other user concerns about connected devices. Integration in advanced technology, a focus of Leti R&D, is required, including use of security primitives, or low-level cryptographic algorithms. Secure IoT nodes face a complex array of potential weaknesses beyond physical attacks, such as attacks through communication interfaces, fault injection (glitches, light, laser, electromagnetism) and software, in which a single error can open the door to a hacker.

Beyond its cybersecurity programs, Leti is working with its partners to develop dedicated security devices to protect biological, radiological, chemical and weapons data. CESTI is Leti’s evaluation laboratory to determine whether security components and devices are designed and manufactured to prevent breaches and whether they are capable of withstanding attacks from terrorists, criminals or others.

The CESTI lab has evaluated products from leading companies such as SAFRAN, Samsung, ATMEL, STMicroelectronics, Gemalto, Oberthur and Inside Secure. The lab is part of Leti’s Strategic Security and Defense Programs, which promotes the development of innovative security solutions for information and communication (ICT) technologies for transfer to defense and commercial markets.

‘System approach with partners’

In her closing remarks, Leti CEO Marie Semeria noted that reliability, security and privacy are “must haves” to support the many key uses of digital technology. “Leti relies on a combination of hardware and software, so we pursue system approaches with our partners,” she said.

Focusing on micro- and nanotechnologies, architectures, tools and design methodologies, Semeria underlined that Leti is a worldwide recognized important center of competencies in developing innovations to propose efficient and reliable elements & architectures for emergent computing systems. She highlighted several recent Leti innovations for the Internet of Things and advanced computing for health, automotive and other sectors.

Leti has unique know-how and access to shielding, sensors, architectures and embedded software technologies for designing ASICs and SOCs for security applications. Moreover, its unique concentration of experts in materials, technologies integration, design and systems, even in biology and clinical domains, allows Leti to make the best trade offs possible between security, such as resistance to attacks, and application constraints, such as power, cost and performance.

Leti will celebrate its 50th anniversary next year as part of Leti Innovation Day in Grenoble.

asmlThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Martin van den Brink, president and chief technology officer at ASML Holding and renowned pioneer in semiconductor manufacturing technology, has been named the 2016 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Van den Brink will accept the award at the annual SIA Award Dinner on Thursday, Nov. 10 in San Jose, an event that will commemorate the 25thanniversary of the Noyce Award.

Many past award recipients will be in attendance to celebrate the anniversary, including the following semiconductor industry leaders and founders: Dr. Craig Barrett, Dr. Morris Chang, John Daane, Dr. John E. Kelly III, Stanley Mazor, Jim Morgan, Jerry Sanders, George Scalise, Mike Splinter, Ray Stata, Rich Templeton, and Pat Weber.

“Throughout his distinguished career, Martin van den Brink has been a true semiconductor industry innovator, champion, and visionary, pioneering optical lithography methods that have given rise to the smaller, faster, more efficient chips that underpin modern technology,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Martin’s myriad accomplishments over the last 30 years have strengthened our industry and fundamentally transformed semiconductor manufacturing. On behalf of the SIA board of directors, it is a pleasure to announce Martin’s selection as the 2016 Robert N. Noyce Award recipient in recognition of his outstanding achievements.”

During Van den Brink’s three decades at ASML, he has led transformative advances in optical lithography procedures used to manufacture semiconductors. Optical lithography, a microfabrication process in which light-sensitive chemicals are used to transfer circuit patterns onto chip wafers, is the primary technology used for the production of semiconductors and has allowed for the continued miniaturization of chips. Thanks in large part to Van den Brink’s technological leadership, ASML is now the world’s largest supplier of optical lithography equipment for the global semiconductor industry.

Van den Brink was one of ASML’s first employees, joining when the company was founded in 1984. He has held various engineering positions since that time, including Vice President, Technology and Executive Vice President, Marketing & Technology. He has served on ASML’s Board of Management since 1999 and was appointed President and CTO on July 1, 2013. Van den Brink earned a degree in Electrical Engineering from HTS Arnhem, and a degree in Physics from the University of Twente, the Netherlands.

“I’m extremely gratified to accept this honor and enter the company of previous Noyce Award recipients, many of whom I’m proud to call friends, colleagues, and mentors,” said Van den Brink. “Throughout my career, I have been privileged to work with some of the finest scientists, engineers, and researchers in the world, individuals who have helped strengthen the semiconductor industry, the tech sector, and the global economy. It is with them in mind that I thankfully accept this award and look forward to continuing to work alongside them to advance semiconductor innovation.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

“I’m also pleased that we will be joined at this event by so many of the past winners of the Noyce Award who have built this industry and driven its success over the years,” Neuffer said. “This event will be a unique opportunity to celebrate the industry and the promise for the future.”

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at: http://cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

In the early stages of development, having more process control can help reduce both the number and duration of cycles-of-learning (the iterations required to solve a particular problem). In high volume manufacturing a well-thought-out process control strategy can increase baseline yield and, at the same time, limit yield loss due to excursions. At all stages, an effective process control strategy is required to ensure that the fab is operating at its lowest possible cost. In addition to minimizing production costs, adding process control steps can, counterintuitively, also minimize cycle time.

Figure 1 shows a conceptual plot of how cycle time would vary as a function of the number of process control steps. On the left hand side of the chart where there are no metrology and inspection (M&I) steps in place, the cycle time is effectively infinite. If a lot reaches the end of the line and has zero yield there is no way to isolate the problem. Theoretically one could isolate the problem by trial and error, but with only 100 process steps and only two parameters each, there would be 2100 (1.3 x 1030) possible combinations. Even testing one parameter per second, it would take much longer than the age of the universe to exhaust all possible combinations of the parameter space.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

As process control steps are added the cycle time comes down from an effectively infinite value to some manageable number. At some point the cycle time will reach a minimum value. Beyond this point, adding in further process control steps will actually cause the cycle time to increase linearly with the number of added steps. The optimal amount of process control will always be a trade-off between minimizing cycle time, minimizing excursion cost, and maximizing baseline yield. The latter two usually have a much greater financial impact.

Adding process control steps can reduce a fab’s cycle time, but how does that work? A full treatment of cycle time (Queuing Theory) is far beyond the scope of this article, however at a high level, it can be broken down into a few manageable components. The total cycle time (CT) is the sum of the queue time (the time a lot spends waiting for a process tool to become available) and the processing time itself. Since the processing time is fixed, the only way to reduce CT is to concentrate on the queue time (Q). From Queueing Theory it can be shown that Q can be expressed by the product of three separate functions4,

Q = f(u) f(a) f(v)                                                                                           eqn 1

where f(u), f(a) and f(v) are, respectively, functions of utilization, availability and variability. The first two functions will always be finite, therefore it becomes clear that Q = 0 only when f(v) = 0. Put another way, reducing variability in the fab reduces the queue time, and if we remove all variability from the system the queue time will drop identically to zero and the CT will be equal to just the processing time.

Figure 2 shows a plot of CT as a function of utilization for three different levels of variability: zero, medium and high. The Y-axis measures cycle time in units of total processing time called the X-factor. When the variability is zero all the lots move through the fab in lock-step; there is no increase in CT with increasing utilization and all tools could be run, theoretically, at 100 percent utilization. In this case the queue time is zero and the CT is equal to the total processing time for all the steps (CT=1). As soon as some variability is introduced, the CT starts to increase exponentially with utilization and the more variability there is, the more dramatic the increase becomes.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Variability in the fab comes from many sources: in the lot arrival rate, in the frequency of maintenance requirements, and in the time required for that maintenance to be performed are just a few of the sources. An excursion—a lot that is out of control—affects all of the above.

Having more process control points will not immediately change the number of excursions in a fab but it will immediately improve the efficiency with which the fab reacts to them.

In fact, over time, having more process control points can also reduce the number of excursions because it increases a fab’s rate of learning.

Consider a lot that has been flagged for having a defect count that was beyond the control limit for process step N. If, as shown in figure 3a, there was another inspection point between process steps N and N-1, then the problem can be immediately isolated. Only the tool at step N (the process tool the offending lot went through) needs to be put down and only the lots that went through that tool since the last good inspection need to be put on hold for disposition.

By contrast, consider what would happen in figure 3b where the last inspection point was five steps ago at process step N-5. Practices differ from fab to fab, however in the worst case scenario, all ten tools that the lot went through would be put down and all lots that went through any of those tools would have to be put on hold. Instead of a minor disruption involving a single process tool and a few lots, entire modules and dozens of lots can be directly affected. Indirectly, it affects the entire fab.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3 shows that implementing fewer inspection steps has a threefold impact on cycle time:

  1. More process tools are involved and must be taken offline
  2. Each process tool is down for a much longer period of time because it takes longer to isolate the problem
  3. More wafers are in the impacted section of the production line. These wafers must be dispositioned

The variability introduced by these three impacts will also propagate through the fab; they constrict the flow of work in progress (WIP) through the fab, creating a WIP bubble that affects the lot arrival rate (increased variability) at every station downstream. All of these factors contribute to fab-wide variability and because of the re-entrant nature of the process flow, they add to the cycle time of every single lot in the fab.

When an excursion occurs, the resulting disruption impacts the cycle time of every lot in the fab and it quickly becomes a vicious cycle. The more excursions that happen during a given lot’s cycle time, the longer that cycle time will be. And the longer the cycle time is, the more likely it is that that lot will be in the fab when the next excursion occurs.

Adding inspection steps will add a small, known amount of cycle time to those lots that get inspected, but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved.

This counter-intuitive concept has been borne out by several fabs that have both added inspection steps and reduced cycle time simultaneously. Adding process control steps contributes to fab efficiency on several levels: accelerating R&D and ramp phases, increasing baseline yield, limiting the duration of excursions, and reducing cycle time. In short, a better-controlled process is a more efficient process.

The next article in this series will discuss the impact of process control to cycle time on so-called “hot lots” typically run during early ramp.

References:

  • “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  • “Process Watch: Time is The Enemy of Profitability,” Solid State Technology, May 2015.
  • “Economic Impact of Measurement in the Semiconductor Industry,” Planning Report 07-2, National Institute of Standards and Technology, U.S. Department of Commerce, December 2007.
  • Hopp, W. J., and Spearman, M. L. Factory Physics (2nd). (New York: Irwin, McGraw-Hill, 2001), 325.

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 700 companies exhibit at SEMICON West and 26,000+ professionals attend, from the electronics manufacturing supply chain. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

The Best of West 2016 Finalists will be displaying their products on the show floor at Moscone Center from July 12-14:

  • Coventor: SEMulator3D – A 3D semiconductor process modeling platform that can predicatively model any fabrication process applied to any semiconductor design. Starting from a “virtual” silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer. (Facilities and Software category; Booth #2622)
  • CyberOptics: WaferSense® and ReticleSense® Auto Multi Sensors (AMS) – Wireless sensor devices capable of multiple measurements (leveling, vibration and relative humidity) to save time and expense while improving yields. WaferSense AMS travels through virtually any tool with its thin and light form factor, while ReticleSense AMSR has the same measurement capabilities in a reticle shaped form factor. (Metrology and Test category; Booth #2323)
  • Graphenea: Graphene Integration on CMOS-Fab – Allows large-scale manufacture of 200mm CMOS-compatible graphene wafers (SEMI Standards), with low metal contamination levels. The industrial production method will produce uniform, large-scale/high-performance graphene in high yields and a reliable manner. (Advanced Materials and Materials Management category; Booth #632)
  • Kulicke & Soffa Industries: IConn MEM PLUS High Performance Wire Bonder for Memory Devices – A new high-performance memory device bonder for gold and silver alloy wire bonding. With its advanced process, looping, overhang control and ease of use capabilities, it delivers high quality and productivity benefits in complex multi die stack package applications. (Assembly/Packaging Solutions category, Booth #6060)
  • Rorze Automation: Rorze N2 Purged LP – Maintains low humidity during critical steps. A typical bottom purged LP can only offer control of an average of 30 percent RH. However, N2 purge LP from Rorze (patent pending) can offer a humidity control that is better than 5 percent. (Components and Subsystems category; Booth #1613)
  • SPTS Technologies (an Orbotech company): Rapier-300S – A production silicon DRIE module, designed specifically for dicing of 300mm  wafers mounted on 400mm frames. It builds on SPTS experience in plasma singulation of framed 150mm and 200mm wafers, and employs patent-protected end-pointing and process control techniques, critical to delivering stronger die than traditional dicing methods. (Assembly/Packaging Solutions category; Booth #1417)

The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 13, 2016.