Tag Archives: letter-ap-top

STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package.

As the industry was beginning to learn about eWLB in 2008, STATS ChipPAC immediately recognized the significant potential, value and scalability of eWLB and designated it as a key technology for the company.  Within a year, STATS ChipPAC had ramped eWLB to high volume production and was driving a number of technology and manufacturing initiatives in this new packaging approach. STATS ChipPAC has led the industry in eWLB manufacturing capabilities, capacity and technology innovations, particularly in 2.5D and 3D package designs.  STATS ChipPAC became the first company in the semiconductor industry to implement significantly larger than 300mm eWLB wafer manufacturing capabilities and has a strong portfolio of innovative eWLB packages, including small die, large die, multi-die, multi-layer, Package-on-Package (PoP) and System-in-Package (SiP) architectures.

“We differentiated STATS ChipPAC by our unwavering commitment to eWLB technology over the years, beginning with our vision of how this scalable packaging platform can be leveraged to drive performance and size advantages for our customers’ applications.   Over the years we have made significant capital investments and process enhancements to fulfill our vision and raise the bar on manufacturing efficiency and productivity in the industry, adding further value for our customers,” said Dr. Han Byung Joon, President and Chief Executive Officer, STATS ChipPAC. “Although we have achieved multiple milestones with eWLB through the years, shipping over one billion eWLB packages is a testament to the ever expanding customer adoption in the industry and success which we knew was possible with this game changing technology.”

The exceptional success of eWLB in the mobile market, particularly in baseband processors, connectivity devices, Codec devices, RF transceivers and power management integrated circuits (PMICs), is a reflection of the ongoing pressure semiconductor companies face in cost effectively achieving higher input/output (I/O), higher bandwidths and lower power consumption in the smallest possible form factor. STATS ChipPAC has driven a number of eWLB technology achievements such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line width and spacing down to 2um/2um and ultra thin package profiles below 0.3mm (including solderball) for single packages and below 0.6mm for a stacked PoP with proven warpage control.

With the ability to partition silicon and embed passive devices and vertical interconnects (known as eBar) into a design, eWLB is a powerful integration technology for 2.5D and 3D PoP or SiP solutions for a wide range of new and emerging applications. The compelling performance, size and cost advantages of eWLB are accelerating the adoption of this advanced technology into new markets such as the Internet of Things (IoT) and wearable electronics, Micro-Electro-Mechanical Systems (MEMS) and automotive applications. Examples of new eWLB applications are Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $26.1 billion for the month of March 2016, a slight increase of 0.3 percent compared to the previous month’s total of $26.0 billion. Sales from the first quarter of 2016 were $78.3 billion, down 5.5 percent compared to the previous quarter and 5.8 lower than the first quarter of 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased in March for the first time in five months, but soft demand, market cyclicality, and macroeconomic conditions continue to impede more robust growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Q1 sales lagged behind last quarter across nearly all regional markets, with the Americas showing the sharpest decline.”

Regionally, month-to-month sales increased in Japan (4.8 percent), Asia Pacific/All Other (2.3 percent), and Europe (0.1 percent), but fell in China (-1.1 percent) and the Americas (-2.8 percent). Compared to the same month last year, sales in March increased in Japan (1.8 percent) and China (1.3 percent), but decreased in Asia Pacific/All Other (-6.4 percent), Europe (-9.8 percent), and the Americas (-15.8 percent).

“Eighty-three percent of U.S. semiconductor industry sales are into markets outside the U.S., so access to overseas markets is imperative to the long-term strength of our industry,” Neuffer said. “The Trans-Pacific Partnership (TPP) is a landmark trade agreement that would tear down myriad barriers to trade with countries in the Asia-Pacific. The TPP is good for the semiconductor industry, the tech sector, the American economy, and the global economy. Congress should approve it.”

March 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.03

4.89

-2.8%

Europe

2.66

2.67

0.1%

Japan

2.47

2.59

4.8%

China

8.02

7.93

-1.1%

Asia Pacific/All Other

7.83

8.01

2.3%

Total

26.02

26.09

0.3%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.81

4.89

-15.8%

Europe

2.96

2.67

-9.8%

Japan

2.55

2.59

1.8%

China

7.83

7.93

1.3%

Asia Pacific/All Other

8.57

8.01

-6.4%

Total

27.70

26.09

-5.8%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

5.75

4.89

-15.0%

Europe

2.77

2.67

-3.6%

Japan

2.57

2.59

0.8%

China

8.45

7.93

-6.1%

Asia Pacific/All Other

8.08

8.01

-0.8%

Total

27.62

26.09

-5.5%
Year-to-year percent change in world semiconductor revenues over the past 20 years.

Year-to-year percent change in world semiconductor revenues over the past 20 years.

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, today announced the launch of the International Roadmap for Devices and Systems (IRDS), a new IEEE Standards Association (IEEE-SA) Industry Connections (IC) program to be sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative in consultation with the IEEE Computer Society. Together, this group will ensure alignment and consensus across a range of stakeholders to identify trends and develop the roadmap for all of the related technologies in the computer industry.

The IRDS represents the next phase of work that began with the partnership between the IEEE RC Initiative and the International Technology Roadmap for Semiconductors 2.0 (ITRS 2.0). With the launch of the IRDS program, IEEE is taking the lead in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. The Methods of governance, reports, and strategic roadmaps developed by the ITRS and ITRS 2.0 will inform the IRDS within the IEEE-SA IC program.

“The computer industry has benefitted from roadmaps since it was first published in 1965,” said IEEE Fellow Thomas M. Conte, 2015 president, IEEE Computer Society; co-chair, IEEE Rebooting Computing Initiative; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “Bringing the IRDS under the IEEE umbrella will create a new ‘Moore’s law’ of computer performance, and accelerate bringing to market new, novel computing technologies.”

“The broad scope of IRDS spanning from base technology through systems and architecture will create an environment where known end-requirements will drive technological solutions and decrease the time to market for implementation, ultimately creating a new Moore’s law,” added IEEE Fellow and Senior Director, IEEE Future Directions, William R. Tonti. “The integration of the work of the IRDS into IEEE and governance of the semiconductor to system roadmap through the IEEE Rebooting Computing Initiative opens the door to innovative end-to-end computing solutions.”

“Over the past decade, the structure and requirements of the electronics industry have evolved well beyond the semiconductor’s industry requirements. In line with the changes in the new electronics ecosystem, the IRDS will build upon the past groundwork and move up a level to identify challenges and include recommendations on possible solutions,” said Paolo A. Gargini, IEEE Fellow and chairman, of IRDS. “The IRDS will deliver a 15-year vision that encompasses systems and devices, setting a new direction for the future of the semiconductor, communications, IoE and computer industries.”

Participants in the IRDS will convene 12-13 May 2016 in Leuven, Belgium. Over the course of the two-day workshop, the group will review the roadmap activities of the Focus Teams (FT) and of the International Technology Working Groups (ITWG) and lay out plans for additional activities in 2016. Some of the fields of discussion include System Integration, Heterogeneous Integration, Connectivity, Future IC Devices and Factory Integration.

The IEEE Rebooting Computing Initiative is a program of the IEEE Future Directions Committee, designed to develop and share educational tools, events and content for emerging technologies.

IEEE-SA’s Industry Connections Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

IC Insights’ March Update to the 2016 McClean Report refreshed the forecasts for 33 major IC product categories through 2020.  The complete list of all 33 major IC product categories ranked by the updated forecast growth rates for 2016 is shown in Figure 1.  Fourteen product categories—topped by Cellphone Application Processors and Signal Conversion (analog) devices—are expected to exceed the 2% growth rate forecast for the total IC market this year. Another five product categories are expected to grow at the same 2% rate as the total IC market.  The total number of IC categories forecast to register sales growth in 2016 increases to 20 products from only nine in 2015.

Growth of Cellphone Application MPUs (10%) is forecast to remain near the top on the growth list for a fifth consecutive year. Though the rate of growth for cellphone application MPUs has cooled in recent years, IC Insights still forecasts a solid 10% growth year for this market as smartphone shipments remain an attractive end-use application for IC markets.  Signal Conversion (DAC analog, etc.) devices are also expected to show a 10% increase in 2016 thanks to their implementation across a wide variety of consumer, communication, and computing devices, and in other systems to monitor and control the interface between analog and digital signals.   The market for 32-bit MCUs is forecast to increase 8% with “intelligent” cars the catalyst for much of this growth.  Driver information systems and many of the increasing number of semi-autonomous driving features such as self-parking, advanced cruise control, and collision-avoidance rely on 32-bit MCUs. Complex 32-bit MCUs are expected to account for over 25% of the processing power in vehicles in the next few years.

Other notable categories include the previously high-flying Tablet MPU market, which is forecast to sputter to just 2% growth in 2016 as enthusiasm fades for these systems. DRAM is expected to show a steep market decline this year and drop to become the second-largest IC product category (trailing only the standard PC, server MPU market) in 2016.  After registering big gains in 2013 and 2014, the DRAM market fell 3% in 2015 and is forecast to tumble another 8% in 2016 as oversupply and waning desktop and notebook computer demand force suppliers to slash average selling prices to move product.  Worldwide DRAM ASP growth was down 4% in 2015 and is on track to fall 11% in 2016.

2016 forecast of ic market

Figure 1

By Jan Vardaman (TechSearch International) and Dan Tracy (SEMI)

While much of the recent attention has been focused on the growth of wafer level packages (WLPs), specifically fan-out WLPs, this is not the only segment forecast to undergo strong unit growth. In total, IC leadframe shipment growth will trend in the low single-digit range; the growth is entirely attributed to the chip-scale package (CSP) leadframe form factor. Combined, the more traditional IC leadframe segments are expected to experience flat shipments trends, while leadframe CSP shipments continue to growth.

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook

Leadframe CSP packages find broad adoption in analog, power, mixed signal, general purpose logic, sensors, and other device applications. A number of leadframe CSPs are in the form of quad flat no-lead (QFN) packages. These packages have pads instead of leads and do not use solder balls.  QFNs are found in mobile phones including smartphones, toys, games, tablets, medical systems, industrial, computers, networking, and automotive products.  Devices packaged in QFNs include many different MEMS and sensors such as accelerometers, gyroscopes, magnetometers, and pressure sensors, and power management devices, controllers, and ASICs.  Stacked die versions are increasingly common.  Gyroscopes and accelerometers are stacked with wire bonds in the QFNs found in many wearable products.  QFNs are also increasingly common as packages for automotive electronics.

This form factor will grow as it delivers a thin, small, and low-cost solution required in many applications. Emerging in the market are coreless structures based on a modified leadframe technology called a Molded Interconnect Solution/System (MIS) that deliver higher I/O and SiP solutions. Advancements are needed to further the high-volume ramp of MIS and other routable-leadframe CSP technologies.

Small package form factors deliver solutions needed in mobile applications and will provide the package technology for many sensor and wearable applications emerging in the market place.

The information in this article is from the Global Semiconductor Packaging Materials Outlook—2015-2019 report produced by SEMI and TechSearch International.

The flip chip technology market market is expected to grow from $19.01 billion in 2015 to $31.27 billion by 2022, at a CAGR of 7.1% between 2016 and 2022, according to the new market research report “Flip Chip Technology Market by Wafer Bumping Process (CU Pillar, Lead-Free), Packaging Technology (2D IC, 2.5D IC, 3D IC), Packaging Type (BGA, PGA, LGA, SIP, CSP), Product (Memory, LED, CPU, GPU, SOC), Application and Geography – Global Forecast to 2022,” published by MarketsandMarkets.

The flip chip technology market is driven by factors such as increasing demand for miniaturization and high performance in electronic devices, and strong penetration in consumer electronics sector.

3D IC packaging technology to register the highest growth rate

On the basis of packaging technology, the Flip Chip Technology Market is segmented into 2D IC, 2.5D IC, and 3D IC packaging technology. With the semiconductor technology moving towards integration of diverse chips, 2.5D IC packaging technology and 3D IC packaging technology are becoming the mainstream trend in obtaining the integration objectives. Owing to the growing demand for increasing density, higher bandwidth, and lower power, design teams are expected to adopt 3D ICs with TSVs, which promise ‘more than Moore’ integration by packaging a great deal of functionality into small form factors, while improving performance and reducing costs.

Applications in consumer electronics held the largest market size and would also grow at the highest rate

Smartphones & tablets are observed to have the highest adoption among all the consumer electronic devices, owing to their small form factor and better performance requirements to operate at a higher bandwidth, at a relatively lower cost. The automotive market is expected to grow at a second-highest CAGR rate, catapulting the flip chip technology market further.

The market in Asia-Pacific to grow at the highest rate

The APAC held a large share of the overall flip chip technology market in 2015; moreover, the market in APAC is expected to grow at the highest CAGR between 2016 and 2022. Countries in Asia-Pacific are major manufacturing hubs and are expected to provide ample opportunities for the growth of the flip chip technology. The growing demand for high performance in smartphones and automotive MCUs is driving the market in this region.

Major players in this market are Intel (U.S.), TSMC (Taiwan), Samsung (South Korea), and GlobalFoundries (U.S.), ASE group (Taiwan), Amkor Technology (U.S.), UMC (Taiwan), STATS ChipPAC (Singapore), Powertech Technology (Taiwan), and STMicroelectronics (Switzerland) among others.

On the basis of wafer bumping process, the flip chip technology market is segmented into copper pillar, lead free, tin/lead eutectic solder, and gold stud+ plated solder. The product segment consists of CPU, SoC, GPU, memory, LED, CMOS image sensor, and RF, mixed signal, analog, and power IC. On the basis of application, the market is segmented into consumer electronics, telecommunications, automotive, industrial sector, medical devices, smart technologies, and military and aerospace. The packaging type segment includes FC BGA, FC PGA, FC LGA, FC QFN, FC SiP, and FC CSP. The packaging technology in flip chip has been segmented into 2D IC, 2.5D IC, and 3D IC. This global report gives a detailed view of the market across the four regions, namely, Americas, Europe, Asia-Pacific, and the Rest of the World which includes the Middle East and Africa. The report profiles the 10 most promising players in the flip chip technology market.

Samsung Electronics Co., Ltd. announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class, 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.

Samsung 10nm-class DRAM-Group_002

Samsung opened the door to 10nm-class DRAM for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.

Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm) 4Gb DDR3 DRAM in 2014.

“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”

Samsung’s leading-edge 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30 percent.

The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.

The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.

Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.

Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM (1y).

In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.

Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.

While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.

Optimized settings for DI water pressure at CMP and careful analysis of interconnect layout are used to improve quality on a complex analog design.

BY STEPHEN SWAN, JOSEPH WILLIAMS, ANN CONCANNON, JIM O’HANNES and ERIC EVANGELOU, Texas Instruments, Dallas, TX

Triboelectricity is defined as a charge of (static) electricity generated by friction. The concept was first applied in the 1940s for electrostatic painting and is now widely used in photocopy machines. This phenomenon becomes a concern in wafer manufacturing processes since water is a polar molecule and deionized water (~18MOhm) is a good insulator [1, 2].

Our investigation into circuit damage was initiated by a finding of high leakage from a single transistor within a complex analog design. Electrical and physical analysis of a failing site revealed a halo image on a TEM micrograph, suggesting that the area of highest electric field under the poly gate had been damaged (FIGURE 1).

Screen Shot 2016-03-30 at 12.06.47 PM

Wafer signature – fab root cause

After insuring there was no quality risk (with HTOL and ELFR reliability testing), focus was placed on identi- fying the physical root cause, understanding why the failures were only occurring on a single transistor, and developing a design rule to reduce the risk on future products. Examination of wafer yield maps revealed fallout of less than 500 parts per million (ppm) in a distinctive geometric pattern with failing die at unique radius from the wafer center. Discussions with fab process experts within TI revealed that the geometric pattern aligned with positions of DI water jets on a single wafer oxide chemical mechanical planarization (CMP) tool and that the problem correlated to use of high DI water pressure (60psi) during wafer transfer operation.

Subsequent experiments proved that transistor damage was occurring when DI water was used to elevate the (inverted) wafer from the load chuck to the polish head with jets of water causing static discharge in distinct locations (FIGURES 2, 3). Interim corrective action was taken to match the DI water pressure to the recommended setting of 20psi, with verification provided by both passive data and experimental results [3].

Screen Shot 2016-03-30 at 12.06.53 PM Screen Shot 2016-03-30 at 12.07.01 PM

Since static electricity in triboelectric charging is caused by friction, we can apply the Bernoulli principle to estimate the relative change in static charge when dropping water pressure from 60psi to 20psi (Equation 1). This principle states that the sum of energy (kinetic and potential) in a fluid under steady flow must be equal at all points along the stream. In the case of water being ejected from a fixed nozzle, this would require that a drop in pressure (potential energy) results in a drop in velocity (kinetic energy) thereby reducing friction and static charge.

Equation 1: Bernoulli principle

Screen Shot 2016-03-30 at 12.07.16 PM

Where:
v is the fluid flow (m/s)
g is the value of acceleration due to gravity (9.81m/s2) z is the orifice size
p is the pressure (pascals)
ρ is the density of water (1000 kg/m3)

Solving for relative difference, we find that velocity is a function of pressure, such that reducing pressure from 60psi to 20psi will decrease the velocity by about 40 percent. Thus, we can predict a corresponding drop in static charge due to friction by the same amount. The relative difference in charge was validated by using a surface photovoltage (SPV) tool, which is a method of monitoring the potential of a semiconductor surface [4], FIGURE 4.

Screen Shot 2016-03-30 at 12.07.07 PM

Tool ‘fingerprint’ analysis

Now that a physical explanation for how excess static charge was being applied to the face of product wafers had been defined, the next step was to understand why the resulting damage to the product circuit was always observed in a specific transistor (as opposed to being randomly distributed throughout the circuit). Through yield map signature analysis of the diagonal clusters of product die with a revised test screen, it was noted that while the clusters of failing die appeared at distinct radius dimensions from wafer center, their orientations were not fixed and, at first pass, seemingly random. However, upon closer inspection of the load chucks (FIGURES 2, 3), it was found that the water jets (appearing as a ‘slit’ style nozzle) had fixed orientations that were different from tool to tool.

This information led to an effort of correlating the nozzle position on each CMP tool to the orientation of diagonal clusters in the stacked yield wafer maps. This comparison made it possible to map yield loss sites from individual wafers to specific tools, and to identify that the damage was taking place at a specific layer for the product (second dielectric CMP, after metal-1).

Capacitive coupling

With the knowledge that the source of the physical damage was coming from triboelectric charging at one oxide CMP step , a working theory was created to show how the electric charge could find a path to ground from the front side (DI water jet) to the backside (grounded wafer chuck) of the wafer (FIGURE 5).

Screen Shot 2016-03-30 at 12.07.22 PM

Design considerations

In a design of more than 180 thousand transistors, it was significant that all failures mapped to a single NMOS transistor. This device was one of six identical structures, a two finger minimum sized 5V NMOS and the device was isolated from any external connections so charge coupling from an external pin was eliminated as a potential cause. Also, a review of metal-to-gate antenna design rules confirmed that there were no violations within the failing array and metal to gate ratios were well within the specification, with 10X margin. Since it was unlikely that a traditional antenna was the cause of the gate damage, additional aspects of the layout needed investigation [5].

Two areas of concern at the metal-1 layer under second dielectric were minimum metal spacing and adjacent metal routes for parallel lines. Investigation of the layout and design rules at this layer showed that minimum spacing of parallel lines was smaller than that of other metal layers, which would make the capacitance coupling between metal lines at this layer more significant.

Further analysis of the adjacent metal showed that this one transistor had a considerable amount of floating metal (prior to subsequent metal routing) adjacent to its gate metal compared to the five adjacent transistors. A model of capacitance between the floating metal and gate metal of the six structures showed that the LED5 transistor had a ratio more than 10:1 compared with ratios less than 1:1 for each of the other five transistors.

Our conclusion from these combined efforts was that failure of the single transistor in question was due to the unique layout of tight metal spacing and a high ratio of floating metal-to-gate metal, when under the influence of triboelectric charging from the fab CMP process.

An updated graphic (FIGURE 6) is used to show that charge is induced on the wafer (oxide) surface and coupled to the floating metal and finally, to the gate metal. The floating metal increases the effective gate metal capacitance such that it is now large enough to accumulate adequate charge to damage its gate oxide.

Screen Shot 2016-03-30 at 12.07.32 PM Screen Shot 2016-03-30 at 12.07.40 PM

To prevent this effect from impacting future designs, an electronic design automation (EDA) approach was used to define conditions which would flag combinations of metal:gate antenna ratios and proximity of gate to floating metal.

Summary

Root cause of high leakage from a single transistor within a complex analog design was proven to be due to an interaction between triboelectric charging in the wafer CMP process and the unique layout of this structure. Process modifications were performed to reduce DI water pressure during the wafer handling sequence at CMP, a test screen was developed to yield off any future failures and ELFR / HTOL reliability verification was performed to insure no quality risk on finished goods. EDA design checks have been developed to flag structures with high ratios of spacing for floating metal to gate metal for sites with significant metal antenna ratios.

Acknowledgments

Our thanks to several members of TI who were instrumental in identifying root cause and solutions. These include Dan Clavet, Scott Kolda, Aaron Dries, and Chris Qualey from MaineFab, Jonathan Shu and Michelle Hartsell of SVA Quality, Bill McIntyre of SVA-MDP, Dinh Nguyen of SVA- MLP, Nam Nguyen and Chris S Pereira of ATI, and Mikko Loikkanen of SVA-MLP Design.

References

1. Dela Cruz, W.A.; Marcelo, M.L.D.; Borlongan, M.A.B., “Preventing arcing damage on radio frequency device wafer by

controlling ESD resistivity level of water for saw and wash,” 29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD, vol., no., pp.3B.5-1, 3B.5-4, 16-21 Sept. 2007.

2. Re-Long Chiu (WaferTech) “Scrubber Clean Induced Device IDDQ Fail”, IEEE Proceedings, 2012.

3. S. Larivière (Altis Semiconductor), “Electro-static induced metal breakdown at interlayer dielectric post CMP brush clean process”. ASMC Proceedings, 2009.

4. Schroder, Dieter K. (2006). Semiconductor Material and Device Characterization. Wiley-IEEE Press. ISBN 0-471-73906-5.

5. Ackaert, J.; Greenwood, B., “Design solutions for preventing process induced ESD damage during manufacturing of inter- connects,” IC Design and Technology (ICICDT), 2010 IEEE Inter- national Conference on , vol., no., pp.98,101, 2-4 June 2010.

STEPHEN SWAN is Quality Manager at TI’s MaineFab in South Portland Maine; JOSEPH WILLIAMS and ERIC EVANGELOU are mem- bers of MaineFab Product Engineering; ANN CONCANNON (DMTS) is a member of TI Analog Labs in Santa Clara CA; JIM OHANNES is manager of the TI Design Center in South Portland ME.

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the last in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

In the eighth installment1 in this series, “The Tyranny of Numbers,” we discussed the trend of increasing process steps—the number of steps is expected to double between the 20nm and 10nm nodes—and the impact that those additional steps will have on final yield. In addition to impacting yield, the increased complexity of the process flow will also increase production costs and cycle time. As these trends unfold, managing costs and cycle time will become increasingly important to fab operations.

The tenth fundamental truth of process control for the semiconductor IC industry is:

Adding Process Control Reduces Production Costs and Cycle Time

Instrumental to having an efficient, low-cost fab is the ability to collect meaningful information about the process in a timely fashion. Process control tools (metrology and inspection) are the eyes and ears of the fab in that they provide insight into what’s working and what’s not: they are an investment in “process information.” In a 2007 paper2 the National Institute of Standards and Technology (NIST) estimated that the average return on investment for metrology alone was 300 percent.

Previous articles in this series have illustrated how process control can reduce costs by reducing the scrap and raw material costs associated with lost yield and reliability3 failures. Similarly, improving yield reduces the environmental footprint of fab operations per good die out.4 In this article, we will examine two other elements of cost reduction and factory efficiency enabled by process control:

  1. Process equipment re-use from node-to-node
  2. Improved net cycle time

Equipment Re-Use

The single biggest component of cost in a modern fab is capital depreciation. It can vary from company to company, but typically wafer fab capital equipment is depreciated at 20 percent per year over the course of five years. If you can extend the life of a piece of equipment beyond the point where it is fully depreciated you are essentially getting that tool for free. If you can find a way to re-use an entire group of process tools (scanners, etchers, etc.) the savings could easily be measured in tens or even hundreds of millions of dollars.

Ultimately, a process tool must meet the technical specifications that are demanded by the manufacturing process in which it is used. However, in cases where the tool’s capability is marginal, its lifetime can be extended by closer monitoring—using existing metrology or inspection tools to keep the tool operating within the required process specifications. Performing more frequent process tool qualifications can help improve matching and ensure that a tool does not drift out of spec. For stable feed-back and feed-forward schemes, having more in-line inspections provides better averaging and allows for better control of the actual process. In these situations, process control is helping to extend the life of existing process tools—adding process control in this context can actually save money.

The Process Capability Index (Cpk) is a metric that measures how well the natural variation of a process fits within the spec limits. For a centered process with a symmetric distribution the Cpk is given by equation 1,

Cpk = (USL – LSL) / 6σ                             Eq. 1

where USL and LSL are the upper and lower spec limits respectively and s is the standard deviation of the process. If the Cpk value is greater than one, the process is considered capable. Cpk values less than one indicate that the process is not capable.

Consider an etch process step where the Cpk of the CD measurement is exactly equal to one (i.e., the step is marginally capable in that the upper and lower spec limits are both three standard deviations from the mean). The marginal capability could be the fault of the previous photo step, the etch step or both. Either way it is an expensive proposition to upgrade either tool set to improve the Cpk—the capability —of the process.

Often the capability of the process can be improved by implementing a data feed-forward scheme—using additional metrology to fully characterize the process at one step (e.g., photo) and then feeding that information forward to adjust parameters at etch to effectively customize the process conditions for each lot or wafer. Figure 1 below shows an example Statistical Process Control (SPC) chart of the after-etch CD with and without feed-forward.

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Feed-back and feed-forward schemes can be used to extend the useful lifetime of process tools by effectively increasing the process window in which they operate. CD measurements that are slightly off target at photo can be brought back on target by using that information to adjust the etch bias at the etch process step. 

Cycle Time

Cycle time is another very important production metric. We will give a more detailed account of cycle time in an upcoming paper but would like to touch briefly on the counter-intuitive relationship between cycle time and process control.

Any source of variability that prevents lots from moving through the fab in lock-step fashion will increase the cycle time. Adding inspection steps will add cycle time to those lots that get inspected but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down (because the inspection points are closer together) and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved. This counter-intuitive concept has been demonstrated by several fabs that have both added inspection steps and reduced cycle time simultaneously.

To summarize, adding process control steps contribute to fab efficiency on several levels (figure 2): increasing baseline yield, extending the useful life of existing process tools, limiting the duration of excursions, and reducing cycle time.

Figure 2. The cascading benefits of process control.

Figure 2. The cascading benefits of process control.

As we conclude this series on the 10 fundamental truths of process control1,3,5-11, we thank you for reading. We hope that these articles have provided deeper insight into the value of process control and the base knowledge for successful implementation of process control in IC fabrication. We look forward to exploring additional aspects of process control in future Process Watch articles throughout the coming months.

References:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.