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By Denny McGuirk, SEMI president and CEO

“In like a lion, out like a lamb” is just half the story for 2015.  While initial expectations forecasted a double-digit growth year, the world economy faded and dragged our industry down to nearly flat 2015/2014 results.

However, 2015 will be remembered for a wild ride that fundamentally changed the industry.  In 2015 a wave of M&A activity swept across the industry supply chain — unlike any single year before — with scores of transactions and notable multi-billion dollar companies being absorbed.  In 2016, we all will be working within a newly reconfigured supply chain.

Increasingly, in this business landscape, collaboration is required simultaneously across the extended supply chain — customers’ customers’ customers are now routinely part of the discussion in even unit process development.  Facilitating interaction and collaboration across the extended supply chain is part of what SEMI does and I’ll be updating you in next week’s letter on how, but first, let’s review what’s happened and what’s happening.

2015 Down 1%: “In Like a Lion, Out Like a Lamb”

2015 had an optimistic start with a strong outlook and good pace in Q1 and 1H.  In January 2015 forecasters projected semiconductor equipment and materials growing in a range of 7 percent to nearly 14 percent vs. 2014.  Global GDP, as late as May 2015, was pegged at 3.5 percent for 2015 after coming in at only 3.4 percent in 2014.  In August, estimates dropped to 3.3 percent, in November estimates dropped further to 3.1 percent for the year.

As our industry has matured, semiconductor equipment and materials growth rates are ever more tightly correlated to shifts in global GDP.  With global GDP unexpectedly dropping, the second half saw declining book-to-bill activity and the year will likely end flat or slightly negative for 2015.  Though nearly flat, the numbers are still impressive with a healthy $37.3 billion annual revenue for semiconductor manufacturing equipment and $43.6 billion for semiconductor materials.

An important change is since the 2009 financial crisis, electronics, chips, and semiconductor equipment and materials markets have been much more stable year-to-year than in the years prior to 2009.  Also, the movement of the three segments is much more synchronized compared to the earlier years of boom and bust. For SEMI’s members this means cycles are becoming more muted — enabling members to shift business models accordingly to better maintain prosperity.

Fab-Equipmt-600w Capital-Equip-600w

 

2015’s $125+ Billion M&A:  Inflection Point for Silicon Valley Icons and Global Titans

2015 is a year that will be viewed as an inflection point in our industry.  The unprecedented M&A volume (more than $125 billion for semiconductor related companies) and the size of individual deals through the electronics supply chain will forever  change the industry.

historic-proportions

While there have been waves of consolidation for semiconductor Integrated Device Manufacturers (IDMs) in the 1980s and 1990s, and semiconductor equipment and materials in the 1990s and 2000s, the fabless semiconductor companies are the latest wave undergoing consolidation.  Although, in 2015, not just fabless, but all segments saw major deals — even iconic chemical brands DuPont and Dow Chemical announced their intention to merge.

Large and familiar brands like Broadcom (Avago), SanDisk (Western Digital), Altera (Intel), Freescale (NXP), and KLA-Tencor (Lam Research) have been merged and will continue forward as part of their acquirers.  China is on the move with its ambitions to quickly grow its indigenous semiconductor supply chain with recent acquisitions of ISSI, OmniVision, NXP RF power unit, and notably Mattson in the semiconductor equipment segment.

In an age when new fab costs are pushing double-digit billions of dollars and leading-edge device tapeouts are surpassing $300 million per part, consolidation is a strategy to increase scale, leverage R&D, and compete better.  For SEMI’s members, the winner-take-all stakes increase and raise expectations for technology, product performance, application development, speed, and support.  This, in turn, means that SEMI members have an increased need for a newly drawn pre-competitive collaboration model along the extended electronics supply chain and for Special Interest Groups (SIGs) to drive collective action in focused sub-segments and for specific issues.

Collaboration-is-critical-6

Source: SEMI (www.semi.org), 2015

2016 Up ~1%: Stay Close to your Customer and your Customer’s Customer and …

Current projections for semiconductor equipment and materials suggest that 2016 will not be a high growth year.  The span of forecasts ranges from almost -10 percent to +5 percent.  At SEMI’s Industry Strategy Symposium (ISS), 10-13 January, we will be taking a deep-dive into the 2016 forecast and on the business drivers and will have a much better picture of the consensus outlook.

However, it is already quite clear that following this enormous wave of consolidation, the industry will look different and will offer new and different opportunities.  Listening to SEMI’s members, I’ve heard that during this period of upheaval it’s absolutely critical to stay close to one’s customers – but more than that – to have access and ongoing direct dialogue with the customer’s customer … and customers’ customers’ customers.

In light of the cost of research and development, the magnitude of risks, and the speed of new consumer electronics adoption, SEMI members find that they need to intimately know emerging requirements two to three steps away in the supply chain, and may require rapid and innovative development from their own sub-suppliers to meet product delivery in time.  In parallel, we see system integrators (electronics providers) staffing up with semiconductor processing engineers and equipment expertise, both for differentiation of their own products and for potential strategic vertical manufacturing.

2016 will mark an acceleration of collaboration and interdependence across the extended supply chain.  Next week, I’ll provide an update letter on SEMI’s related activities with an overview of what SEMI is doing to meet the realities of a reshaped industry.  SEMI’s role is evolving, and more important now than ever, in helping the industry achieve together, what it cannot accomplish alone.

SEMI-Infographic--Achieving

Learn more about SEMI membership and upcoming events.

By Shannon Davis, Web Editor 

2015 was a year of unprecedented consolidation in the semiconductor industry, as well as a technological crossroads in Moore’s Law. Below is a round-up, based on reader popularity, of the most read stories on Solid State Technology from 2015.

1) 2015 outlook: Tech trends and drivers

Leading industry experts provided their perspectives on what to expect in 2015. 3D devices and 3D integration, rising process complexity and “big data” are among the hot topics.

2) Reframing the Roadmap: ITRS 2.0

The International Technology Roadmap for Semiconductor (ITRS) is being reframed to focus more on end applications, such as smartphones and micro-servers. Labeled ITRS 2.0, the new roadmap is a departure from a strong focus maintaining the path defined by Moore’s Law.

3) Freescale and NXP agree to $40B merger

Chipmaker NXP Semiconductors NV announced that it has agreed to buy Freescale Semiconductor Ltd for $11.8 billion and merge business operations. The combined enterprise values at just over $40 billion and will create a new leader in the auto and industrial semiconductor markets.

4) Samsung’s FinFETs are in the Galaxy S6!

The much-anticipated Samsung Galaxy S6 made an early appearance in Chipworks’ teardown labs last week, thanks to the diligent skills of their trusted logistics guru.

5) Moore’s Law to keep on 28nm

Scaling is now bifurcating – some scaling on with 28/22nm, while other push below 14nm.

6) More change for the chip industry

As if scaling to 7nm geometries and going vertical with FinFETs, TSVs and other emerging technologies wasn’t challenge enough, the emerging market for connected smart devices will bring more changes to the semiconductor sector. And then there’s 3D printing looming in the wings.

7) EUV: Unlike anything else in the fab

Imagine EUV lithography in high volume production. ASML has been working for years to make it happen. Earlier this year, ASML said that one of its major chip-manufacturing customers has placed an order for 15 EUV systems, including two that are set to be delivered before the end of this year. ASML did not name the customer, but it is almost certainly Intel (according to research firm IHS).

8) Apple Watch and ASE start new era in SiP

Back in April the Apple watch appeared in the Chipworks’ labs, and of course they pulled it apart to see its contents.

9) New AMS fab going to Marcy, NY

Austria-based ams AG, formerly known as Austriamicrosystem, announced plans to locate a new 360,000 ft2 fab in upstate New York at the Nano Utica site in Marcy, NY. The fab will be used to manufacture analog devices on 200/300mm wafers.

10) Historic era of consolidation for chipmakers

We are in a historic era for consolidation among semiconductor manufacturers. Solid State Technology compiled the latest consolidation news, as well as analysis on the implications for the industry.

11) Lithography alternatives: Why are they essential?

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT.

12) A look ahead at IEDM 2015

In the second week of December, the good and the great of the electron device world made their usual pilgrimage to Washington D.C. for the 2015 IEEE International Electron Devices Meeting.

Bonus: Top Webcasts of 2015 – Available On Demand Now!  

How the IoT is Driving Semiconductor Technology

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the Internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will be rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology. 

Sensor Fusion and the Role of MEMS in the IoT

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion and the important role that MEMS will play in the Internet of Things (IoT). Marcellino Gemelli, Head of Business Development at Bosch Sensortec will discuss how smart systems are enabled through sensor fusion. Karen Lightman, Executive Director of MEMS Industry Group (MIG), provided a “debrief” from the recent MEMS Technical Congress and a preview of a SEMICON West workshop focused on back-end challenges.

3D NAND Challenges and Opportunities

Flash memory has revolutionized the world of solid-state data storage, mainly because of the advent of NAND technology. However, from the technical point of view, this requires a major change in how these memories are being fabricated. This presentation discusses this (r)evolution as well as its major scaling limitations.

Resolve to stay up-to-date on industry news in 2016! Here’s how.

By Dr. Phil Garrou, Contributing Editor

At the 12th annual 3D ASIP [Architectures for Semiconductor Interconnect and Packaging] Conference, sponsored by RTI Int, in Redwood City CA last week, Professor Mitsumasa Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the conference’s first recipients of the “3DIC Pioneer Award”.

Conference Chair Dr. Phil Garrou from Microelectronic Consultants of NC commented, “Since we are now more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, we are convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first in the field, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Profesor Koyanagi’s work started back with his seminal paper “Roadblocks in achieving 3-dimensional LSI” presented at the Symposium on Future Electronic Devices in 1989. His 1995 paper “Three dimensional Integration Technology Based on a Wafer Bonding Technique Using Micro Bumps” showed a process sequence similar to todays TSV etch, thin and bond for an image sensor circuit.

Dr. Ramm began his work in the early 1990s in collaboration with Siemens under the German sponsored R&D program “Cubic Integration – VIC”. Their paper “Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology,” which appeared in IEEE Trans on Components, Packaging and Manufacturing Technology in 1996 woke up the larger community to the possibilities of using 3DIC. A key patent from that era was USP 5,563,084 “Method of Making a 3 Dimensional Integrated Circuits” which issued in 1996.

According to the newly released “Global Semiconductor Packaging Materials Outlook — 2015/2016 Edition,” the $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. The new report by SEMI and TechSearch International covers laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key observations include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging (see Figure).

metal compound consump

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook 2015/2016 Edition

The findings in the report are based on over 150 in-depth interviews conducted with semiconductor manufacturers, fabless semiconductor companies, packaging subcontractors, and packaging materials suppliers throughout the world. The report covers details about the industry growth and trends for the various material segments. Information includes market size, regional data, unit trends, and market share. It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units from 2015 to 2019; supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size. All of the information was derived from the SEMI Global Packaging Materials Outlook from 2015 to 2019 produced by SEMI and TechSearch International.

2016 bounce to modest gains


December 14, 2015

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI

SEMI just published the latest quarterly update of its World Fab Forecast report.  While the year started with a positive outlook, the initial optimism has largely deflated, and the year will end largely flat. Fab equipment spending growth (new and used) for 2015 is expected to be 0.5 percent (US$ 35.8 billion). For 2016, spending is forecast to grow by 2.6 percent ($36.7 billion), with a possible continued upward trend.

Past trends prove again the close correlation of spending to global GDP and revenue.  The IMF predicted worldwide GDP to grow by 3.5 percent back in May, and has revised it down to only 3.1 percent.  Likewise, as of May, the year’s average revenue growth for the semiconductor industry was predicted to be in the mid- to high-single digits (according to ten leading market research firms).  Now these firms have revised their 2015 predictions to an average of just 1.3 percent.

Fab equipment spending (new, used and in-house) follows the same rollercoaster as revenue, and is now expected to grow by only 0.5 percent by the end of 2015, possibly 1 percent, according to SEMI.

Fab-Equipment-Spending

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Cherish the Memory

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016. In 2015, DRAM spending was second in place but in 2016 3D Flash will, by far, outspend DRAM.

Most DRAM spending in 2015 went towards 21/20nm ramp.  In 2016, DRAM companies are expected to start risk production of 1xnm (for example, Samsung in 1H 2016; Hynix in 2H 2016; and Micron in 2016).

While 2015’s spending was dominated by DRAM, SEMI reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge.  SEMI’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

Foundry Segment Holds Steady

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. The largest foundry player, TSMC, has a strong impact on the foundry industry.  In the second half of 2015, TSMC cut 2015 capex from $10.5 billion to $8 billion, due to a flagging market.  SEMI expects a stronger fourth quarter in 2015 for equipment spending for foundry as TSMC fulfills its capital expenditure for the year and we expect an increased capex in 2016.

TSMC recently announced revenue expectation for 2016 to be in double digits and expects to increase capex for 2016 as it ramps 16nm and adds initial 10nm capacity.

It’s Only Logical (and MPU)

Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Intel revised its planned capex down four times, from $10 billion to $8.7 billion then to $7.7 billion, and finally to $7.3 billion, and it decided to delay the launch of 10nm products (Cannonlake) to 2H17.  Intel still announced lofty plans for 2016 capex, around $10 billion.  Especially in 2H16, spending will pick up for anticipated 10nm activities.

Meanwhile for Logic spending has been very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.  This exuberant growth, however, is expected to slow down in 1H16.

Consequence of Consolidations: the End of Wild Times?

Between 2010 and 2014, change rates for equipment spending fluctuated wildly, from +16 percent in 2011 to -16 percent in 2012, -8 percent in 2013 to 15 percent in 2014. These drastic changes have been replaced by dampened spending growth rate for 2015 and into 2016.  Multiple reasons may apply: a more mature and lower growth industry, increased caution regarding capacity ramp, or perhaps the recent frenzy of consolidations further concentrating capex spending.  SEMI’s next quarterly publication, in February 2016, will give further insight into early indicators of 2017.  Will sedate, positive spending growth continue?

The SEMI World Fab Forecast Report in Excel format, tracks spending and capacities for 1,167 facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. It uses a bottoms-up approach methodology, providing high-level summaries and graphs and in-depth analyses of capital expenditures, capacities, technology and products by fab.  Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

At this week’s IEEE IEDM conference, nano-electronics research center imec showed for the first time the integration of high mobility InGaAs as a channel material for 3D vertical NAND memory devices formed in the plug (holes) with the diameter down to 45nm. The new channel material improves transconductance (gm) and read current which is crucial to enable further VNAND cost reduction by adding additional layers in 3D vertical architecture.

Non-volatile 3D NAND flash memory technology is used to overcome the scaling issues in conventional planar NAND flash memory technology, suffering from severe cell to cell interferences and read noise due to aggressively scaled dimensions. However, current 3D NAND devices, featuring a poly-Si channel, are characterized by drive current that will linearly decrease with the number of memory layers, which is not sustainable for long-term scaling. This is because the conduction in the poly-silicon channel material is ruled by grain size distribution and hampered by scattering at the grain boundaries and charged defects.

To boost the drive current in the channel, imec replaced the poly-Si channel material with InGaAs through a gate first-channel last approach. The channel was formed by metal organic vapor phase epitaxy (MOVPE) showing good III-V growth selectivity to silicon and holes filling properties down to 45nm. The resulting III-V devices proved to outperform the poly-Si devices in terms of on-state current (ION) and transconductance (gm), without degrading memory characteristics such as programming, erase and endurance.

“We are extremely pleased with these results, as they provide critical knowledge of Flash memory operations with a III-V channel as well as of the III-V interface with the memory stack,” stated An Steegen, Senior Vice president Process Technology at imec. “While these results are shown on full channels, they are an important stepping stone to develop industry-compatible macaroni-type III V channels.”

Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including Samsung, Micron-Intel, Toshiba-Sandisk, SK Hynix, TSMC, GlobalFoundries.

Typical ID-VG. In0.6Ga0.4As presents improved ID-VG characteristic. Ion/Ioff ratio of 3 order of magnitude is sufficient for typical NAND operation

Typical ID-VG. In0.6Ga0.4As presents improved ID-VG characteristic. Ion/Ioff ratio of 3 order of magnitude is sufficient for typical NAND operation

Worldwide semiconductor fab equipment capital expenditure growth (new and used) for 2015 is expected to be 0.5 percent (total capex of US$35.8 billion), increasing another 2.6 percent (to a total of $36.7 billion) in 2016, according to the latest update of the quarterly SEMI World Fab Forecast report.

SEMI reports that in 2015, Korea outspent all other countries ($9.0 billion) on front-end semiconductor fab equipment, and is expected to drop to second place in 2016 as Taiwan takes over with the largest capex spending at $8.3 billion. In 2015, Americas ranked third in overall regional capex spending with about $5.6 billion and is forecast to increase only slightly to (5.1 percent) in 2016.

fab equipment spending 2016

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016.  While 2015’s spending was dominated by DRAM, the SEMI World Fab Forecast reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge. SEMI’’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Logic spending was very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.

Throughout 2015, SEMI anticipates that there will be 1,167 facilities worldwide investing in semiconductor equipment in 2016, including 56 future facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. For further details, please reference to the latest edition of SEMI’s World Fab Forecast report.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

“Advanced packaging will reach 44% of packaging services and a revenue of US$ 30 billion by 2020,” Yole Développement (Yole) announced. Overall, the main advanced packaging market is the mobile sector with end products such as smartphones and tablets. Other high volume applications include servers, PC, game stations, external HDD/USB and more.

According to Yole’s latest advanced packaging report entitled “Status of the Advanced Packaging Industry” (2015 Edition), emerging applications are coming from the IoT world, with wearables and home appliances (connected home) solutions already penetrating the market. Other early stage IoT investments have been also made in smart cities, connected cars, industrial devices, medical applications…

In parallel, the Chinese companies play an important role in the advanced packaging market growth: “At Yole, we see an increased activity of Chinese capital in the advanced packaging industry,” explains Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. “The objective of the semiconductor transformation in China is to decrease external dependency and set up a complete internal supply chain that can serve domestic and international customers.”

In this context, what would be the evolution of the advanced packaging industry? What will be the status of the supply chain by 2020? Which packaging technologies will be the most critical tomorrow and after? With the emergence of IoT applications, the development of local Chinese industry and numerous M&A coming from the overall semiconductor industry and the direct impact on the advanced packaging supply chain. Yole’s advanced packaging analysts offer you insight into the new advanced packaging world.

“Status of the Advanced Packaging Industry” report (2015 edition) released by Yole, the “More than Moore” market research and strategy consulting company, provides an high added-value market overview of the industrial landscape; under this new report, Yole’s advanced packaging team proposes a comprehensive analysis of the technology trends and also assesses the future development of the advanced packaging market.

packaging industry graph

This analysis confirms the market positioning of Yole and highlights the knowledge and deep understanding of the company within this industrial field.

According to Yole’s estimates, advanced packaging services revenue will increase by US$9.8 billion from 2014 to 2020 at a CAGR of 7%, in majority due to high volume adoption of Fan-Out WLP, 2.5D/3D and evolution and growth of Fan-In WLP and flip-chip. Advanced packages currently account for 38% of all packaging services or US$ 20.2 billion and are expected to grow share to 44% and US$ 30 billion by 2020.

The mobile sector remains the main advanced packaging market with smartphones and tablets as end products. Other high volume applications include servers, PC, game stations, HDD/USB, WiFi hardware, base stations, TVs and set top boxes. The scent of IoT is spreading with first products already on the market in the form of wearables and smart home appliances. Further early stage investments are made in sectors such as smart cities, connected cars, various industrial devices and medical applications.

The flip-chip platform represents a large mature market and leads in packaging services revenue and wafer count. Fan-In WLP leads in unit count due to small size compared to demanded volume. Adoption of wafer level packages continues. Teardowns performed by Yole and its sister company, System Plus Consulting on 3 high end smartphones (more info on i-micronews.com, reports section or click here directly for iPhone 6+, Samsung Galaxy S6 as well as the Huawei Ascend Mate 7 analysis, that will be available soon) indicated a high penetration rate of WLP, 30% on average. Fan-Out WLP is expected to make a major breakthrough within the next year, likely led by TSMC inFO PoP and followed by other Fan-Out multi die solutions. Long term, a bright future lies ahead for wafer level packages with respect to IoT requirements as they are well position to answer related cost, form and functional integration demands. When it comes to advanced feature sizes, a competitive sub 10 µm / 10 µm arena is established where organic wafer level packages aggressively compete with advanced organic flip-chip substrates and 2.5D / 3D Si/glass interposers.

As WLP pin counts grow, thicknesses and overall cost decrease, the evolution of Fan-In WLP and in particular a breakthrough of Fan-Out WLP are expected to result in a takeover of a part of the flip-chip market. With the breakthrough of Fan-Out WLP, the packaging landscape might drastically change, with an IDM and foundry leading all packaging services by wafer count.

The full advanced packaging analysis is today available; in the report Yole’s analysts present revenue, wafer and unit forecasts per advanced packaging platform and production breakdown by device type such as analog/mixed signal, wireless/RF, logic and memory, CMOS image sensors, MEMS, LED and LCD display drivers.

Intel and ASM look to TCB


November 17, 2015

BY PHIL GARROU, Contributing Editor

In the September column, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology? The focus this month is more on this very important new assembly process from Intel and ASM.

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). FIGURE 1 shows these various defects.

Phil Garrou

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140°C) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100°C/s and cooling ramp rate exceeding 50°C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

In another ASM paper on TCB they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Then the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predeter- mined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder. They claim this results in attachment of 1200 units/hr vs 600 for the standard TCB flux process.