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Process Watch: Risky business


September 18, 2015

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

By Zvi Or-Bach, Contributor

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those that drive the high-volume PC and smart-phone market. The Gartner slide below illustrates this industry bifurcation where traditional mass products follow the ever more expensive scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek a place near its minimum.

S3S_Gartner

The current high-volume market is focused on a few foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs and a broad range of process options, and has many more players both at the foundry side and the design side.

The key enabling technologies for the IoT market are extremely low power as enabled by SOI and sub-threshold design, integrated with multiple sensor and communication technologies that are both enabled by 3D integration. All of these combine in forming the IEEE S3S unified conference.

This year’s conference includes many exciting papers and invited talks. It starts with three plenary talks:

  • Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  • Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  • Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration

The following forecast from BI Intelligence suggest that the semiconductor technologies that are a good fit for the future market of IoT should be of prime interest for the semiconductors professional.

S3S_BI

Jim Walker, Research VP at Gartner, argued at the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy” market symposium that 3D ICs are the key enabler of performance and small form factor of products required for IoT.

The upcoming IEEE S3S conference provides an important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” which will present a process technology to fabricate flexible devices 6-20 microns thin. This process flow is currently in manufacturing in their Stuttgart fab, as depicted below:

S3S_Fig3

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share  Qualcomm’s views on monolithic 3D IC, which they term 3DVLSI and illustrate below, which seems very fitting for IoT applications.

S3S_Fig2

Globalfoundries will present joint work with Georgia Tech on “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimensional scaling as illustrated by the following chart.

S3S_Fig4

Monolithic 3D will present “Modified ELTRAN (R) – A Game Changer for Monolithic 3D” that shows a practical flow for existing fabs to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

S3S_Final

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short courses on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors were $27.9 billion for the month of July 2015, a decrease of 0.9 percent from July 2014 when sales were $28.1 billion. Global sales from July 2015 were 0.4 percent lower than the June 2015 total of $28.0 billion. Regionally, sales in the Americas were roughly flat in July compared to last year, while sales in China increased by nearly 6 percent. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales have slowed somewhat this summer in part due to softening demand, normal market cyclicality, and currency devaluation in some regional markets,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite these headwinds, year-to-date global sales through July are higher than at the same time last year, which was a record year for semiconductor revenues.”

Regionally, year-to-year sales increased in China (5.6 percent), Asia Pacific/All Other (1.0 percent), and the Americas (0.8 percent), but decreased in Europe (-12.5 percent) and Japan (-13.3 percent), in part due to currency devaluation. On a month-to-month basis, sales increased in Japan (2.7 percent), China (0.6 percent), and Europe (0.4 percent), but fell slightly in the Americas (-0.3 percent) and Asia Pacific/All Other (-2.5 percent).

“One key facilitator of continued strength in the U.S. semiconductor industry is research, the lifeblood of innovation,” Neuffer said. “SIA and Semiconductor Research Corporation this week released a report highlighting the urgent need for research investments to advance the burgeoning Internet of Things and develop other cutting-edge, semiconductor-driven innovations. Implementing the recommendations in the report will help the United States harness new technologies and remain the world’s top innovator.”

July 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.53

5.52

-0.3%

Europe

2.83

2.84

0.4%

Japan

2.57

2.64

2.7%

China

8.13

8.18

0.6%

Asia Pacific/All Other

8.94

8.71

-2.5%

Total

27.99

27.88

-0.4%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.47

5.52

0.8%

Europe

3.24

2.84

-12.5%

Japan

3.04

2.64

-13.3%

China

7.75

8.18

5.6%

Asia Pacific/All Other

8.63

8.71

1.0%

Total

28.13

27.88

-0.9%

Three-Month-Moving Average Sales

Market

Feb/Mar/Apr

May/Jun/Jul

% Change

Americas

5.61

5.52

-1.7%

Europe

2.89

2.84

-1.8%

Japan

2.54

2.64

3.8%

China

7.77

8.18

5.2%

Asia Pacific/All Other

8.74

8.71

-0.3%

Total

27.56

27.88

1.2%

Related news: 

Tech, academic leaders call for robust research investments to bolster U.S. tech leadership, advance IoT

Asia-Pacific’s grip as the dominant market for IC sales is forecast to strengthen in 2015 with the region expected to account for 58.9 percent of the $295.0 billion IC market this year, based on analysis published in IC Insights’ mid-year Update to its IC Market Drivers 2015 report.  The forecast marketshare represents an increase of 0.5 percentage points over the 58.4 percent share that the Asia-Pacific region captured in 2014. The Asia-Pacific region is particularly dominant with regard to IC marketshare in the computer and communications categories, and to a lesser extent in the consumer and industrial categories (Figure 1).  Globally, the communications segment first surpassed the computer segment to become the largest end use market for ICs in 2013 and it is forecast to extend its marketshare lead to 2.7 points in 2015.

ic sales asia pacific

Europe is forecast to account for the largest share of the automotive IC market in 2015, but IC Insights expects the Asia-Pacific region will achieve top share of that segment in 2016 as China continues to account for a large and growing portion of new car shipments.  That will leave only the Government/Military end use segment where Asia-Pacific does not have top IC marketshare—a condition that is forecast to hold through 2018.

IC Insights’ Update to the IC Market Drivers 2015 report forecasts total IC usage by system type through the year 2018.  Highlights from the forecast data include the following items.

•    The two largest end-use market segments in 2015—computer and communications—are forecast to account for 73.9 percent of the total IC sales this year.

•    From 2012-2018, the two highest growth end-use markets for ICs are forecast to be the industrial and communication segments, having CAGRs of 9.1 percent and 8.2 percent, respectively.

•    The automotive IC market is forecast to a CAGR of 6.1 percent from 2012-2018, yet automotive’s share of the total IC market is forecast to remain below 8.0 percent throughout this time.

•    In 2015, analog ICs are forecast to represent the greatest share of IC sales among automotive (43 percent) and industrial (50 percent) applications; logic devices are expected to account for the greatest share of IC sales within government (33 percent) and consumer (19 percent) systems, and MPUs (60 percent) are forecast to account for the greatest share of IC sales in the computer segment.

By Pete Singer, Editor-in-Chief

Austria-based ams AG, formerly known as Austriamicrosystem, announced plans to locate a new 360,000 ft2 fab in upstate New York at the Nano Utica site in Marcy, NY. The fab will be used to manufacture analog devices on 200/300mm wafers. Total buildout at the site, including support buildings and office space, will be close to 600,000ft2.

An artist’s rendering of a semiconductor fab at the Marcy site.

An artist’s rendering of a semiconductor fab at the Marcy site.

This will be the first fab going into the 428 acre Marcy site, which is large enough to accommodate three fabs and an R&D or packaging facility.

Construction of the ams fab is scheduled to begin in spring 2016, with first wafer ramp in the last quarter of 2017.

In what might become the new business model for fabs, the building itself will be publicly owned and leased to ams, which will assume operating costs and most of the costs of the capital equipment. Capital purchases, operating expenses and other investments in the facility over the first 20 years are estimated at more than $2 billion. ams will create and retain more than 700 full time jobs and anticipates the creation of at least 500 additional support jobs from contractors, subcontractors, suppliers, and partners necessary to establish the full ecosystem necessary to enable advanced manufacturing operations.

Fort Schuyler Management (FSMC) will handle the construction, with the goal of turning the fab over to ams in Q2 2017. A key part of N.Y. Governor Andrew Cuomo’s START-UP NY initiative, FSMC is a State University of New York (SUNY Polytechnic Institute) affiliated, private, not-for-profit, 501c(3) corporation that facilitates research and economic development opportunities in support of New York’s emerging nanotechnology and semiconductor clusters.

“If jobs are being created, everything else will take care of itself,” Cuomo said.

Mohawk Valley EDGE President Steve DiMeo said site work has already started. “We’re putting roads in, storm drainage, utilities and we just approved the change order for clearing the land where ams will be located. We’ll be doing some additional site development this fall, and work closely with Fort Schuyler so that they will be in a position to begin construction the early part of next year.”

In a related announcement, GE Global Research said it will expand its New York global operations to the Mohawk Valley, serving as the anchor tenant of the Computer Chip Commercialization Center (QUAD C) on the campus of SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering in Utica. Nearly 500 jobs are expected to be created in the Mohawk Valley in the next five years from SUNY Poly, GE and affiliated corporations and another 350 in the subsequent five years.

These public-private partnerships represent the launch of the next phase of the Governor’s Nano Utica initiative, which now exceeds more than 4,000 projected jobs over the next ten years. Designed to replicate the dramatic success of SUNY Poly’s Nanotech Megaplex in Albany, NANO Utica further cements New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

“This is a transformative moment that will make a difference in peoples’ lives in the Mohawk Valley for generations to come,” said Governor Cuomo. “Over the past few years, we have worked to reverse the negative and invest in Upstate NY – and today we’re taking another huge step forward. With GE and ams joining the Nano Utica initiative, we’re seeing the region’s economy gathering momentum unlike ever before. The Mohawk Valley is beginning an economic revolution around nanotechnology, and I am excited to see the region take off and thrive, both today and in the years ahead.”

Dr. Alain Kaloyeros, President and Chief Executive Officer of SUNY Polytechnic Institute, said, “Today’s announcement by Governor Andrew Cuomo represents a major expansion for Quad-C and the Nano Utica initiative and is a tremendous victory for the Mohawk Valley and the entire State of New York. World renowned partners such as GE Global Research and AMS raise the level of prestige for the entire region and accelerate the development of this international hub for technology and innovation. Governor Cuomo’s pioneering economic development model, coupled with SUNY Poly CNSE’s world class expertise and resources, continues to generate historic investment and job creation throughout the state. We welcome GE and AMS and their leadership teams and look forward to their partnership in the continued growth of Nano Utica.”

ams Chief Operating Officer Dr. Thomas Stockmeier said, “Building a new wafer fab will help us achieve our growth plans and meet the increasing demand for our advanced manufacturing nodes. Our decision to locate the facility in New York was motivated by the highly-skilled workforce, the proximity to esteemed education and research institutions, and the favorable business environment provided by Governor Cuomo and all the public and private partners we are working with on this important project.”

Additionally, ams will collaborate with FSMC and SUNY Poly on a joint development program to support complimentary research, commercialization and workforce training opportunities at SUNY Poly facilities throughout New York State.

Startups and small electronics companies spent $78.3 billion on semiconductors in 2014, representing 23 percent of the total market, compelling semiconductor companies to revisit their sales strategy to focus on the large number of smaller organizations than relying on big deals from large customers, research firm Gartner said.

Gartner estimates that there are more than 165,000 companies that buy semiconductor chips around the world: The top 10 spend nearly 40 percent of the total semiconductor revenue; the top 11 to 100 spend about 30 percent; and the remainder spend 30 percent.

Despite the top 10 accounting for such a large percentage of the market, some of the largest customers have decreased orders in the past five years, challenging the semiconductor vendors that mainly supplied to them.

While Samsung and Apple have significantly increased orders in the same period due to success in the smartphone market, semiconductor vendors are concerned about the risk of relying on large customers such as these.

“The industry has seen some fairly significant disruption in recent years, which has highlighted the risks associated with semiconductor vendors putting all of their focus on a limited number of large customers, when small companies offer highly profitable and stable growth,” said Masatsune Yamaji, Principal Research Analyst at Gartner. “To overcome the risk, some semiconductor vendors have tried to increase their business with small customers, while others are also realizing that they should adjust their strategies to do this.”

China is the fastest-growing among the major small-customer regions, with spending by these organizations on semiconductors growing from US$7.5 billion in 2007 to US$14.9 billion in 2014; growth in the smartphone and media tablet markets has been strong. In the Americas, EMEA and Japan, revenue from each customer is small, but the total market size of small customers is big due to the large number of such customers.

Gartner maintains that the number of customers will significantly increase after 2017, due to future growth of the electronics market and the increase in the number of Internet of Things solutions. It is anticipated that the maker movement, which creates and markets products that are recreated and assembled using unused, discarded or broken products from computer-related devices, will drive the foundation of startups and growth of small customers.

According to Gartner, big deals are not confined to large organizations, with many successful vendors having success in the small-customer market by leveraging distributors. Limited sales resources can be compensated for by aligning with good sales partners. Strong adherence to direct sales restricts the opportunities with small customers, especially among general-purpose semiconductor vendors. In fact, semiconductor distributors earn a large part of their revenue from general-purpose semiconductors.

“Semiconductor vendors should focus more on the high-tier customers and outsource sales activities with small customers to distributors,” said Yamaji. “Distributors can bring various products to market at the same time, so this outsourcing will reduce the load, not just for semiconductor vendors, but also for customers. Some distributors offer end-of-life product delivery services, so vendors should partner with these distributors to help small customers avoid having to order excessive loads.”

Gartner recommends that vendors need to evaluate how much revenue can be expected, compared with the large customers. The importance of the small customers for each vendor differs by its product type and its target sales region, so vendors need to have their own unique goals in the small-customer market.

“Before jumping in, semiconductor vendors also need to be aware of the risks associated with the small-company market, which is prone to shrinking when the macro economy weakens,” said Yamaji. “Revenue can also shrink even faster than large customers in many cases, so it is important to be aware of risk levels regarding any revenue decline. Vendors can reduce the risks by diversifying their customer base, which can spread the liability to allow for lost orders.”

By Jeongdong Choe, PhD., TechInsights

A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm or sub-20nm generation. Do we still think the 2D NAND Flash technologies have hit the scaling wall? According to TechInsights’ deep-dive analysis on current and future NAND Flash technologies, although 3D V-NAND architecture could help with the scaling limit, we believe the 2D MLC and TLC NAND Flash technologies remain strong and cost effective for 14nm, 12nm and even for single-digit nanometer node.

When it comes to 3D NAND technology, Samsung has been developing and mass-producing 32-tier V-NAND architecture (for technical analysis related to the Samsung 3D V-NAND click here) with MLC and TLC for their 850 PRO and 850 EVO since 2014, although, this is not the final goal for Samsung due to a relatively low yield, process complexity and bit-cost viewpoints. More 3D Flash products may appear at the end of this year, or early in 2016, as major NAND players such as Toshiba, SanDisk, Micron, Intel, and SK-Hynix bring out their 3D products with 24-tier, 32-tier or 48-tier FG (floating gate)/CTF (charge-trap-flash) architecture (Figure 1).

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

However, the ultimate target for 3D NAND is 128-tier or at least 64-tier structure from the bit-cost viewpoints. In that case, the aspect ratio of Si-channel and common source contacts would be over 80:1, which is a strong burden for process integration engineers. In addition, the uniformity of the 64-tier or 128-tier NAND cell characteristics in a NAND string and their endurance/retention/reliability properties during program/erase operation would be another big challenge for the vertical NAND string architecture.

The scaling limits for 10 nm-class and sub-10 nm 2D planar NAND structures include patterning technology including QPT (Quadruple Patterning Technology), cell-to-cell interference such as cross-talk, poly-Si gap-filling process for control gate (CG), self-aligned STI (SA-STI) for isolation patterning, self-aligned process (SAP) for CG/FG, interconnection methodology including pad layout/design, inter-poly dielectric (IPD) layer engineering, and cell transistor channel/source-drain (S/D) engineering. According to TechInsights’ detailed structural analysis and comparison of 15nm and 16nm NAND flash devices (so called 1Y NAND technology node) such as Samsung 16nm, Toshiba 15nm, Micron 16nm and SK-Hynix 16nm products, we may expect that at least two more next generation 2D planar NAND products having 12nm and less than 12 nm technology would be developed and released from major players near future. As for NAND memory density and die size, Toshiba/SanDisk 15nm TLC products have 1.28 Gb/mm2 which is double from other MLC products although Samsung 32-tier 3D V-NAND TLC products have 1.87 Gb/mm2 (Figure 2).

Fig 2

Figure 2. Comparison of NAND memory density for each product (Source: TechInsights)

For patterning the three finest lines of the NAND cell structure such as active/STI, gate/wordline (CG/FG) and bitline (usually, metal-2 lines), a quadruple patterning technology (QPT) seems to be very mature for each of the major NAND players. They use their own QPT integration on three critical layers with three or four masks, SOH etching and two-step self-align reverse patterning (SARP) process. Although the critical dimensions have a little skew on every four patterns, they have successfully developed QPT integration with less than 1nm CD (Critical Dimension) and it could be extended into 10nm and even single-digit nanometer NAND products. Fortunately and thanks to state-of-the-art anisotropic plasma etching and ALD/CVD technology, uniformly repeated 8nm patterns would be possible for NAND cell array. Figure 3 shows a comparison of DPT/QPT patterns for each product.

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Micron uses a 3.3nm thin-FG poly-Si storage node to decrease cell-to-cell interference, while other manufacturers introduce an air-gap process for active, gate wordline (FG/CG) and bitline (metal-2) for thick-FG structure. Especially, the air-gap process has been developed and applied on the channel region of active patterns and FG/CG pillars help decrease the cross-talk.

For an IPD (Inter-Poly Dielectric) or a barrier layer between CG and FG, a multi-layer stacked with thin oxide (O) and nitride (N) layers such as ONO or NONON structure has been used for mid-10 nm class NAND devices, while Micron uses a high-k dielectrics such as HfO/SiO/HfO/Nitrided-SiO which is the same as their 20 nm NAND products. Micron successfully integrated IPD/FG/Tunnel-oxide and decreased FG thickness from 5 nm to 3.3 nm with high-k IPD. It might be further reduced to 10ish nm NAND products by optimizing IPD/FG quantum well structure for their unique thin-FG architecture. A 6 nm tunnel oxide (SiO) is used on Micron, Toshiba/SanDisk and SK-Hynix, while Samsung uses nitrogen-doped oxide in its top and bottom portion.

Triple-row staggered bitline contacts (BC) are used on Toshiba/SanDisk for the first time which is an excellent choice to make things smooth for cell layout and process integration although NAND string overhead is increased from 13% to 19%. Other players still use double-row staggered BC layouts on their 15nm/16nm NAND products (Figure 4).

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Other barriers to extend 2D planar NAND to 10nm such as CG poly fill-ability, anisotropic etching for SA-FG/STI and CG/FG, cell transistor S/D engineering and leaning effect during the process integration are still there. Nevertheless, major players and their equipment vendors will successfully develop and integrate the 10 nm 2D NAND architecture in a few years.

I believe most of the major NAND players have their own matured process integration capability with assistance from ECC and circuit/layout optimization. 2D NAND technology will be further scaled down to 12nm, 10nm, or even 8ish nm which is more cost-effective than 3D V-NAND for near future NAND products.

HeadshotJeongdong Choe has more than 20 years of experience on semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a consulting engineer especially focusing on memory and logic process integration.

After leveling off in the second half of the last decade, CMOS image sensors are in the midst of a strong new wave of growth, which is being driven by a broad range of applications and promises to lift worldwide sales to record-high levels each year through 2019, according to the 2015 edition of IC Insights’ O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. The O-S-D Report’s forecast shows CMOS image sensor sales climbing 15 percent in 2015 to reach an all-time high of $10.1 billion after a strong 19 percent increase in 2014 and subpar 4 percent growth in 2013 that primarily resulted from steep price erosion and inventory corrections in camera phones.  CMOS image sensor unit shipments are now projected to grow 19 percent in 2015 to a record-high 3.7 billion after rising 20 percent in 2014 and 2013 (Figure 1).

Figure 1

Figure 1

For about 15 years, digital cameras in cellphone handsets have been the dominant system application in CMOS image sensors and that will continue to be the case in the second half of this decade, but growth rates in this optoelectronics semiconductor category are expected to be pushed higher by new automotive and machine-vision applications, security and surveillance systems (including body cameras), medical imaging, and a wide assortment of optical-sensing nodes tied to the Internet of Things (IoT).  In 2014, about 70 percent of CMOS image sensor sales ($6.2 billion) were for embedded cameras in cellphones, but that percentage is expected to fall to 49 percent in 2019 ($7.3 billion), which represents a compound annual growth rate (CAGR) of just 3.4 percent, based on the forecast presented in the 2015 O-S-D Report.  In comparison, total CMOS image sensor sales are projected to grow by a CAGR of 11.1 percent in the five-year forecast period to reach $15.0 billion in 2019.

The 2015 O-S-D Report forecasts sales of CMOS image sensor sales for automotive safety systems will climb by a CAGR of 57.4 percent to $2.1 billion in 2019 and represent 14 percent of the market’s total dollar volume that year compared to just 3 percent in 2014.  CMOS image sensor sales for security systems and surveillance applications are expected to grow by a CAGR of 38.4 percent in the five-year forecast period to $899 million in 2019, which will represent 6 percent of the market’s total sales that year versus 2 percent in 2014. The O-S-D Reportshows medical and scientific instrument applications driving up CMOS image sensors sales by a CAGR of 36.0 percent to $824 million in 2019 or about 6 percent of the total market compared to about 2 percent in 2014. Toys and video game applications are expected to increase sales of CMOS image sensors by a CAGR of 32.7 percent to $255 million by 2019, which will represent 2 percent of the market’s total revenue compared to 1 percent in 2014.

Major suppliers of CMOS image sensors are responding to the shift in what’s driving sales growth.  For instance, CMOS image sensor leader Sony now aims to become the largest supplier of imaging solutions for automotive systems by the middle of the next decade after it accomplished its goal of taking the top spot in camera phones in the past few years. Sony’s CMOS image sensor sales grew 31 percent in 2014 to about $2.8 billion, which represented a 32 percent share of the market’s total revenues, based on the supplier ranking in the 2015 O-S-D Report.  After Sony, U.S.-based OmniVision was second in CMOS image sensor sales ($1.4 billion in 2014) followed by Samsung ($1.2 billion), Sharp ($720 million), SK Hynix ($488 million), and China’s GalaxyCore ($360 million), according to IC Insights’ supplier ranking.

IC Insights will release its August Update to the 2015 McClean Report later this month.  The August Update will include an in-depth analysis of the IC foundry market and a look at the top 25 1H15 semiconductor suppliers’ sales results and their outlooks for 3Q15 (the top 20 1H15 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1H15 is depicted in Figure 1.  As shown, it took just over $2.2 billion in sales just to make it into the 1H15 top-20 ranking and eight of the top 20 companies had 1H15 sales of at least $5.0 billion. The ranking includes seven suppliers headquartered in the U.S., four in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore.  The top-20 supplier list includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and four fabless companies.

IC Insights includes foundries in the top 20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.

It should be noted that not all foundry sales should be excluded when attempting to create marketshare data. For example, although Samsung had a large amount of foundry sales in 1H15, some of its foundry sales were to Apple and other electronic system suppliers.  Since the electronic system suppliers do not resell these devices, counting these foundry sales as Samsung IC sales does not introduce double counting.  Overall, the top-20 list in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

semi sales 2q15 fig 1

In total, the top 20 semiconductor companies’ sales increased by only 1% in 2Q15/1Q15, the same growth rate as the total worldwide semiconductor industry.  Although the top-20 semiconductor companies registered a 1% sequential increase in 2Q15, there was a 23-point spread between Samsung, the fastest growing company on the list (10 percent growth), and Qualcomm, the worst performing supplier (13 percent decline) in the ranking.  Moreover, given Qualcomm’s currently dismal guidance for 3Q15, the company is on pace to post a semiconductor sales decline of 20 percent in calendar year 2015.

Samsung’s excellent growth rate in 2Q15 put the company closer to catching Intel and becoming the world’s leading semiconductor supplier.  In 2014, Intel’s semiconductor sales were 36 percent greater than Samsung’s.  In 2Q15, the delta dropped by a whopping 20 percentage points to only 16 percent.  However, with Intel providing guidance for a 3Q15/2Q15 sales increase of 8 percent and Samsung facing a lackluster DRAM market (primarily due to pricing pressures), additional gains toward the number one position may be difficult for Samsung to achieve in the near future.

There were two new entrants into the top 20 ranking in 1H15—Japan-based Sharp and Taiwan-based pure-play foundry UMC, which replaced U.S.-based Nvidia and AMD.  AMD had a particularly rough 2Q15 and saw its sales drop 35 percent year-over-year.  In fact, in 2Q15, the company’s sales fell below $1.0 billion for the first time since 3Q03, almost 12 years ago.  It currently appears that AMD’s 2013 restructuring and new strategy programs to focus on non-PC end-use segments have yet to pay off (in addition to its sales decline, AMD lost $361 million in 1H15 after losing $403 million in 2014).

IC Insights has recently lowered its 2015 worldwide semiconductor market forecast from 5 percent to 2 percent.  As was shown in Figure 1, the top 20 semiconductor suppliers in total had $128.3 billion in sales in 1H15.  This figure was just under 50 percent of the top 20 companies’ full year 2014 sales of $259.1 billion.  With only modest growth expected in the second half of this year for the worldwide semiconductor market, the top 20 semiconductor suppliers’ combined sales in 2015 are expected to be only about 1-2 percent greater than in 2014.

Figure 2 shows how the 1H15 top 20 ranking would have looked if the Avago/Broadcom and NXP/Freescale mergers were in place.  As shown, Avago/Broadcom would have been ranked 7th and NXP/Freescale would have moved into the 10th spot.  IC Insights believes that additional acquisitions and mergers over the next few years are likely to continue to shake up the future top 20 semiconductor company rankings.

semi sales 2q15 fig 2

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $84.0 billion during the second quarter of 2015, an increase of 1.0 percent over the previous quarter and 2.0 percent compared to the second quarter of 2014. Global sales for the month of June 2015 reached $28.0 billion, an uptick of 2.0 percent over the June 2014 total of $27.4 billion and a decrease of 0.4 percent from last month’s total of $28.1 billion. Year-to-date sales during the first half of 2015 were 3.9 percent higher than they were at the same point in 2014. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Macroeconomic headwinds and softening demand have slowed global semiconductor market growth somewhat, but the industry still posted its highest-ever second-quarter sales and remains ahead of the pace of sales set in 2014, which was a record year for semiconductor revenues,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas market continues to post solid year-to-year sales increases, and the global market has now grown on a year-to-year basis for 26 consecutive months.”

Regionally, sales increased compared to June 2014 in China (7.8 percent), the Americas (5.6 percent), and Asia Pacific/All Other (5.2 percent), but fell in Europe (-11.5 percent) and Japan (-13.6 percent). Sales were up slightly compared to last month in Japan (1.0 percent) and China (0.6 percent), but down somewhat in Asia Pacific/All Other (-0.6 percent), the Americas (-1.6 percent), and Europe (-1.7 percent). Sales figures in Europeand Japan have been impacted somewhat by currency devaluation.

“Global semiconductor sales are one indicator of the strength of the U.S. industry, which accounts for more than half of total global sales,” Neuffer said. “Policymakers in Washington should enact policies that do more to promote innovation and allow our industry to compete more effectively globally. We applaud the newly formed Congressional Semiconductor Caucus – led by Sen. James Risch (R-Idaho), Sen. Angus King (I-Maine), Rep. Pete Sessions (R-Texas), and Rep. Zoe Lofgren (D-Calif.) – for working to advance pro-growth policies that will strengthen the U.S. semiconductor industry and our economy.”

June 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.62

5.53

-1.6%

Europe

2.87

2.83

-1.7%

Japan

2.54

2.57

1.0%

China

8.08

8.13

0.6%

Asia Pacific/All Other

9.00

8.94

-0.6%

Total

28.11

27.99

-0.4%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.24

5.53

5.6%

Europe

3.19

2.83

-11.5%

Japan

2.97

2.57

-13.6%

China

7.54

8.13

7.8%

Asia Pacific/All Other

8.50

8.94

5.2%

Total

27.44

27.99

2.0%

Three-Month-Moving Average Sales

Market

Jan/Feb/Mar

Apr/May/Jun

% Change

Americas

5.81

5.53

-4.7%

Europe

2.96

2.83

-4.4%

Japan

2.55

2.57

0.8%

China

7.83

8.13

3.8%

Asia Pacific/All Other

8.57

8.94

4.4%

Total

27.70

27.99

1.0%