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System Plus Consulting, sister company of Yole Développement (Yole), released this month its new reverse costing report, Samsung 3D TSV stacked DDR4 DRAM. In August 2014, Samsung announced the mass production of the first analyzed 3D TSV technology based DDR4 modules for enterprise servers. According to Samsung, this new module, because of its high density and high performance will play a key role in supporting the enterprise servers’ development and cloud-based applications, as well as further diversification of data center solutions.

Reverse costing analysis from System Plus Consulting includes a physical analysis at the module, package, DRAM die and cross-section level, the dedicated manufacturing process flow (TSV & bumping manufacturing step – Flip-chip & stacking process – package assembly unit) and a detailed cost analysis per process step.

According to Yole, 3D TSV technology is expected to reach $4.8B billion in revenues by 2019, mainly driven by 3D stacked DRAM and followed by 3D Logic/Memory and Wide I/O (Source: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Business Update, October 2014). With 40 percent share in the DRAM market, Samsung is by far the number 1 player. By introducing 3D TSV stacking in their latest 64Gb DDR4, Samsung allows this technology to enter in the main stream.
Samsung portfolio of DDR4-based modules using 20nm-class process technology includes registered dual in line memory modules (RDIMMs) and load-reduced DIMMs (LRDIMMs). These memory modules are available with initial speeds up to 2400 Mbps, increasing to the Joint Electron Devices Engineering Council (JEDEC)-defined 3200 Mbps.

This registered dual Inline memory module (RDIMM) includes 36 DDR4 DRAM chips (ref. K4AAG045WD), each of which consists of four 4Gb DDR4 DRAM dies (Ref. K4A4G085WD). The chips are manufactured using Samsung’s 20nm process technology and 3D TSV via-middle package technology.

As a result, the new 64Gb TSV module performs twice as fast as a 64Gb module that uses wire bonding packaging, while consuming approximately half the power.

“On the process side, Samsung used a temporary bonding approach using adhesive glue material and copper via-filled using bottom up filling,” detailed Romain Fraux, Project Manager, MEMS Devices, IC’s and Advanced Packaging at System Plus Consulting. And he adds: “At System Plus Consulting, we paid particular attention in identifying all technical choices made by Samsung on process and equipment (wafer bonding, DRIE via etching, via filling, bumping, underfill).”

System Plus Consulting has published more than 100 reverse costing reports on advanced packaging, MEMS and more.

“Reverse Costing is the process of disassembling a device to identify manufacturing technology and calculate cost”, explains Michel Allain, CEO of System Plus Consulting. Since 1993 the company has analyzed hundreds of integrated circuits, modules, electronic boards and systems for the benefit of large corporations in the semiconductor, automotive and telecom, consumer and energy sectors.

By Zvi Or-Bach, President and CEO, MonolithIC 3D Inc.

SEMICON West 2015 had a strong and rich undercurrent – the roadmap forward is most certainly 3DIC. Yes, the industry can and we will keep pushing dimensions down, but for most designs the path forward would be “More than Moore.” As Globalfoundries’ CEO Jha recently voiced: It’s clear that More-than-Moore is now mainstream rather than niche. Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundreds of millions of units per year.”

CEA Leti’s CEO in her opening presentation for the SEMICON West–Leti day presented the following slide:

3DIC CEA-Leti

Calling the 28nm as the ‘switch node’ from the homogeneous march of the industry with dimensional scaling to the bifurcation we now see, where “More than Moore” approaches such as SOI and 3DIC are taking on an important portion of future progress.

CEA Leti went even further by dedicating its SEMICON West day entirely to 3D technologies, as is seen in their invitation:

leti day logo

GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies

  • Welcome– Leti’s 3D integration for tomorrow’s devices > N Semeria
  • CoolCubeTM: 3D sequential integration to maintain Moore’s Law > Faynot
  • Photonics: why 3D integration is mandatory > Metras
  • Computing: 3D technology for better performance > Cheramy
  • Lighting: 3D integration for cost effectiveness > C Robin
  • Nanocharacterization for 3D>  Bleuet
  • Conclusion– Silicon Impulse > N Semeria

Olivier Faynot, Microelectronic Section Manager at LETI, presented the following slide in his CoolCube presentation.

3DIC Cea-Leti coolcub

This illustrates that monolithic 3DIC of 4 tiers could provide the equivalent scaling value of the 5nm node at a far less infrastructure or NRE cost. As the slide states: “New scaling path, compared to 2D.” The time is now for monolithic 3D approaches to take hold a grow.

A similar message is projected by a slide presented by An Steegen of IMEC at their pre-SEMICON Technology Forum:

3DIC device stacking

The same assessment was also presented by Intel’s Jeff Groff from his synopsis of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore’s Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This resonates with our blog Intel Calls for 3D IC, and was recently voiced by Intel process guru Mark Bohr: “Bohr predicted that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” Bohr’s ISSCC slide from earlier this year reasserts this:

3DIC ISSCC

The key two concerns regarding 3DIC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost,” and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”

These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following slide of CEA Leti.

3DIC coolcube 2

A 1,000x improvement in energy efficiency using monolithic 3D was calculated by Stanford Prof. Subhasish Mitra. His sum-up at a SEMICON West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”

Until recently, all monolithic 3D process flows required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is strengthening for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.

A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders – A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.

P.S.

A good conference to learn more about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D – 3DV, and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

More blog posts from Zvi Or-Bach: 

Moore’s Law to keep on 28nm

Paradigm shift in semi equipment – Confirmed

Moore’s Law has stopped at 28nm

Paradigm shift: Semi equipment tells the future

By David W. Price and Douglas G. Sutherland

Author’s Note: This is the seventh in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

The December 2014 edition of Process Watch suggested that the most expensive defect is the one that goes undetected until the end of line. Indeed, undetected excursions typically result in the scrap of millions of dollars per year of defective semiconductor chips.

But many electronics suppliers and OEMs would argue that the consequences of field failures (reliability defects) are much worse than those of non-functioning devices detected at electrical test (killer defects). Reliability defects result in angry customers, expensive failure analysis, the possibility of lost business, or worse. Consider all the IC devices in places such as automobiles, airplanes, and medical diagnostic and treatment equipment. Reliability in these applications is critical—devices simply cannot fail out in the field. Hence, many fabs place a high priority on reducing the potential for reliability defects.

The seventh fundamental truth of process control for the semiconductor IC industry is:

Improving Yield Also Improves Device Reliability.

For a well-designed process and product, early-life factory reliability issues are dominated by random defectivity. This correlation has been confirmed by numerous researchers over the last two decades [1-6]. More recently, the authors interviewed the quality managers at multiple automotive OEMs who confirmed that the vast majority of reliability failures were ultimately traced to random defectivity in the fab.

Latent vs. Killer Defects:

By definition, a killer defect (a.k.a. yield defect) is a defect that causes the device to fail at t = 0 (electrical test). We use the term “latent defect” (a.k.a. reliability defect) to refer to a defect that causes the device to fail at t > 0 (burn-in to ~6 months).

The relationship between yield and reliability stems from the observation that the same defect types that impact yield also impact reliability. The two are distinguished primarily by their size and where they land on the device structure, as shown in Figure 1.

Figure 1. The same defect types that impact yield also affect reliability. They are distinguished primarily by their size and where they land on the die structure.

Figure 1. The same defect types that impact yield also affect reliability. They are distinguished primarily by their size and where they land on the die structure.

Experiments conducted at multiple device manufacturers have shown that for every 100 killer defects that cause yield loss, there are approximately 1-2 latent defects that will result in a reliability failure. This relationship between killer and latent defects is unequivocal and applies to a broad spectrum of defect types. Furthermore, the preponderance of these defects also correlates with overall defectivity. In other words:

  • Lots with poor yield also have poor reliability
  • Wafers with poor yield also have poor reliability
  • Die locations with poor yield also have poor reliability

For this reason, many fabs will ink out a good die if it is in a suspicious neighborhood on the wafer. These good dies, located in neighborhoods where the surrounding dies fail (Figure 2), have a higher probability of a latent defect, which may activate in the field and create a reliability problem.

Figure 2. A good die in a bad neighborhood. Even though the highlighted die may pass final test, there is an elevated likelihood that this die represents a potential reliability problem. Many device manufacturers would ink out such a die at final test.

Figure 2. A good die in a bad neighborhood. Even though the highlighted die may pass final test, there is an elevated likelihood that this die represents a potential reliability problem. Many device manufacturers would ink out such a die at final test.

Reliability Defect Reduction Strategies

IC makers who supply the automotive industry have long adopted the following strategy: The best way to reduce the possibility of latent (reliability) defects is to reduce the fab’s overall random defectivity levels. This is accomplished through the following:

  1. Increased investment in process control in order to achieve higher baseline yields and fewer excursions for the entire fab (both automotive and non-automotive flows; See Figure 3)
  1. Dedicated automotive process flows that utilize only the most stable process equipment
  1. Use of screening inspections on a few layers in which every wafer is scanned for defects. This is typically accomplished using high speed inspection tools, such as KLA-Tencor’s 8-Series  systems
Figure 3. Fabs set their process control budget by attempting to find the minimum total cost (the cost of process control investment plus the cost of lost yield). For some product types, the total cost must also include the cost of reliability failures. These fabs typically spend more on process control strategies compared to those which are only focused on the cost of lost yield.

Figure 3. Fabs set their process control budget by attempting to find the minimum total cost (the cost of process control investment plus the cost of lost yield). For some product types, the total cost must also include the cost of reliability failures. These fabs typically spend more on process control strategies compared to those which are only focused on the cost of lost yield.

Conclusion

Because yield and reliability defects stem from the same source, reducing the source of yield defects will have the side benefit of also reducing reliability defects. Depending on the nature of the product, this could play a significant role in the fab’s determination of the cost-optimal investment in process control. For more information on the correlation of random defectivity and reliability, please contact the authors or refer to the papers listed below.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

1. Shirley, Glenn and Johnson, Scott. “Defect Models of Yield and Reliability.” Published lecture #13 for Quality and Reliability Engineering ECE 510 course at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm

2. Roesch, Bill. “Reliability Experience.” Published lecture #12 for Quality and Reliability Engineering ECE 510 at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm

3. Kim et al. “On the Relationship of Semiconductor Yield and Reliability.” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3 (2005).

4. Riordan et al. “Microprocessor Reliability Performance as a Function of Die Location for a .25um, Five Layer Metal CMOS Logic Process.” 37th Annual International Reliability Physics Symposium Proceedings (1999): 1-11. DOI (http://dx.doi.org/10.1109/RELPHY.1999.761584).

5. Barnett et al. “Extending Integrated-Circuit Yield Models to Estimate Early-Life Reliability.” IEEE Transactions on Reliability, Vol. 52, No. 3. (2003).

6. Kuper et al. “Relation between Yield and Reliability of Integrated Circuits: Experimental results and Application to Continuous Early Failure Rate Reduction Programs.” Proceedings of the International Reliability Physics Symposium (1996): 17-21.

Read more from Process Watch:

Increasing process steps and the tyranny of numbers

Time is the enemy of profitability

Know your enemy

The most expensive defect

Fab managers don’t like surprises

The 10 fundamental truths of process control for the semiconductor IC industry

“Exploring the dark side,” “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

IC Insights’ new 185-page Mid-Year Update to The McClean Report, which will be released later this week, examines the recent surge of M&A activity, including China’s aggressive new programs aimed at bolstering its presence in the semiconductor industry.

It would be hard to characterize the huge wave of semiconductor mergers and acquisitions occurring in 2015 as anything but M&A mania, or even madness.  In just the first six months of 2015 alone, announced semiconductor acquisition agreements had a combined total value of $72.6 billion (Figure 1), which is nearly six times the annual average for M&A deals struck during the five previous years (2010-2014).

Figure 1

Figure 1

Three enormous acquisition agreements in 1H15 have already catapulted 2015 into the M&A record books.  First, NXP announced an agreement in March to buy Freescale for $11.8 billion in cash and stock.  In late May, Avago announced a deal to acquire Broadcom for about $37 billion in cash and stock, and then four days later (on June 1), Intel reported it had struck an agreement to buy Altera for $16.7 billion in cash.  Avago’s astonishing deal to buy Broadcom is by far the largest acquisition agreement ever reached in the IC industry.

In many ways, 2015 has become a perfect storm for acquisitions, mergers, and consolidation among major suppliers, which are seeing sales slow in their existing market segments and need to broaden their businesses to stay in favor with investors.  Rising costs of product development and advanced technologies are also driving the need to become bigger and grow sales at higher rates in the second half of this decade.  The emergence of the huge market potential for the Internet of Things (IoT) is causing major IC suppliers to reset their strategies and quickly fill in missing pieces in their product portfolios.  China’s ambitious goal to become self-sufficient in semiconductors and reduce imports of ICs from foreign suppliers has also launched a number of acquisitions by Chinese companies and investment groups.

IC Insights believes that the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrate the maturing of the industry.  In addition to the monstrous M&A wave currently taking place, trends such as the lack of any new entry points for startup IC manufacturers, the strong movement to the fab-lite business model, and the declining capex as a percent of sales ratio, all promise to dramatically reshape the semiconductor industry landscape over the next five years.

Within the photolithography equipment market reaching $150M in 2014, advanced packaging applications experienced the strongest growth. Yole Développement (Yole)estimates that more than 40 systems have been installed in 2014, with a compound annual growth rate (CAGR) representing 10 percent between 2014 and 2020. In the meanwhile, MEMS photolithography equipment looks set for 7 percent CAGR and LEDs 3 percent.

Yole released last month its technology & market analysis dedicated to the manufacturing process, photolithography. Under this analysis entitled “Photolithography Equipment & Materials for Advanced Packaging, MEMS and LED Applications”, the “More than Moore” market research and strategy consulting company proposes a comprehensive overview of the equipment and materials market dedicated to the photolithography step. Yole’s analysts performed a special focus on the advanced packaging area. They highlighted the following topics: current and emerging lithography technologies, technical specifications, challenges and technology trends, market forecast between 2014 and 2020, market shares and some case studies.

yole packaging july

“The advanced packaging market is very interesting and is growing dynamically as it includes many different players along the supply chain,” said Claire Troadec, Technology & Market Analyst at Yole. It encompasses outsourced assembly at test firms (OSATs), integrated manufacturers (IDMs), MEMS foundries and mid-stage foundries.
In comparison, even if the MEMS & Sensors industry is growing at a fast pace, components are also experiencing die size reduction due to strong cost pressure in the consumer market. Consequently wafer shipments are not following the same trend as unit shipments. Lastly, LED equipment growth is back to a normal rhythm, after big investments made in recent years.

Advanced packaging has very complex technical specifications. Warpage handling as well as heterogeneous materials represent big challenges to photolithography. Due to aggressive resolution targets in advanced packaging, performance must be improved. The current minimum resolution required is below 5µm for some advanced packaging platforms, like 3D integrated circuits, 2.5D interposers, and wafer level chip scale packaging (WLCSP). A lot of effort is being made to reduce overlay issues due to shifting dies and obtain vertical sidewalls for flip-chip and WLCSP. Although steppers are already well established in the packaging field, new disruptive lithography technologies are also emerging and could contribute to market growth from 2015-2016.

“Huge business opportunities in the advanced packaging market are therefore driving photolithography equipment demand,” highlighted Amandine Pizzagalli, Technology & Market Analyst at Yole. “Given the high growth rate of this market, there is no doubt that already established photolithography players and new entrants will be attracted,” she added.

yole packaging july fig 2

By Pete Singer, Editor-in-Chief

As packaging technology continues to advance to maintain the ever-increasing demand for faster, higher capacity, and lower power devices, wafer bumping plays an important role in enabling these capabilities. Bumps can be placed almost anywhere on the die, giving chip makers the ability to put more and more I/O points on an individual die compared to previous methods.

Inspecting bumps is becoming more challenging. The number of I/O points continues to increase. “As chip makers and OSATs need to put more bumps on an individual die, the geometries are being driven smaller and smaller just like transistor technology,” notes Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit.

Materials are also changing. The industry is experiencing a transition from solder bump to Cu pillar, just as it moved from an evaporated bump to a plated process, according to a new report from TechSearch International. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice.

Laser triangulation technology in conjunction with specially designed optics and analytical algorithms is used on bump inspection systems to provide high-quality measurements of micro-bump critical dimensions at full production speeds.

“Manufacturers need to make sure all the bumps are at the same height. If you have one bump that’s too tall or too short, you start to run into connection issues that result in poor yield or a failed device,” says Goodrich. “Our systems measure bump height to make sure coplanarity is uniform across an individual die,” he added, referring to Rudolph Technologies’ Wafer Scanner Inspection Series. Combined with Discover Enterprise, Rudolph Technologies’ yield and defect management software, the tools provide yield management for 3D/2D bump and RDL metrology, bump and RDL defect detection, and macro defect inspection throughout post-fab processes.

The tools can be used in either a characterization mode, where the dimensions of every bump on every wafer is analyzed, or in a high volume manufacturing mode, where the norm is to do a sampling scenario to monitor for process excursions.

One of the biggest challenges is handling vast amounts of data. “An individual die can have several thousand bumps, which results in millions of bumps on a wafer,” Goodrich said. “The amount of data generated becomes pretty unwieldy, really fast. Being able to manage that data and turn it into information and make decisions is extremely important. We are working with customers to implement that into their process flow.”

Utilizing laser triangulation technology, the Wafer Scanner enables 3D inspection of bumps and RDL of different sizes at high speed. An optional ultra high resolution sensor enables inspection of micro bumps and RDL heights as low as 1µm. Film frame handling capability allows inspection of thin and diced wafers and features a quick-change wafer platform to switch between film frame and whole wafers.

Inspection Smooths a Bumpy Road photo

By Shannon Davis, Web Editor

China’s state-owned Tsinghua Unigroup Ltd. is preparing a $23 billion bid for chipmaker Micron Technology, in what analysts say would be the biggest Chinese takeover of a U.S. company.

Tsinghua, China’s largest state-owned chip design company, is prepared to bid $21 per share for Micron, according to Dow Jones.

As of Tuesday, a Micron spokesman told Reuters that the company had not yet received an offer, while Tsinghua chairman Zhao Weiguo told Bloomberg that the Chinese company was “very interested in cooperation” with Micron.

Tsinghua’s potential purchase of Micron is regarded as a strategic move to help the advancement of China’s own chip sector. The country currently has no major home-grown memory makers, according to Reuters.

Micron is the last remaining U.S. producer of DRAM memory chips, and any foreign takeover would still have to pass a review by the Committee on Foreign Investment in the United States, to examine the national security implications of the deal. The deal would also need to be examined by the Chinese National Development and Reform Commission.

This would not be the first significant consolidation in the memory sector this year. In May, Hewlett-Packard sold a 51 percent stake in its data-networking business to Tsinghua for approximately $2.3 billion.

What the analysts are saying

“Valuation appears low as a potential $21 a share bid is 8.3 times fiscal year PE or low end of the historic range of 7 to 15 whereas Micron was at $32 just 5 months ago,” UBS analyst Stephen Chin told MarketWatch.

MarketWatch speculated that a cheap valuation could encourage other companies to launch their own bids.

BY JIN YOU ZAO, STATS ChipPAC, Singapore, and JOHN THORNELL, Rudolph Technologies, Inc. Bloomington, MN, USA

The demand for 4-mask layer Cu-plated wafer-level chip scale packaging (WLCSP) is increasing rapidly, and the current capability for in-line Cu height measurements is not suitable for high volume manufacturing (HVM). Thus, metrology constrains production capacity and limits volume ramp. Furthermore, the bottleneck created by a backlog of Cu step height measurements risks the timely detection of process drift and control. For a 4-mask layer Cu-plated WLCSP, accurate Cu step height measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.

In this article, the current measurement methodology is reviewed and an alternative measurement solution is derived. Full automation capability is delivered, yet the solution is reliable and versatile enough for high-mix production volumes. For quick-turn and high-mix volume manufacturing, accurate and fast in-line monitoring is crucial for timely process drift detection and control.

WLCSP in-line process measurement challenges

Contact-based profilometers are commonly used in wafer bumping for measurement of metal feature (RDL, UBM) thicknesses due to their ease of use and their low cost of ownership. However, the method of measurement is largely semi-automatic, and the identification of exact features and measurement locations is challenging.

This becomes more acute in a high product-mix HVM environment, where measurement needs to be highly adaptive to different features on different products. As such, contact-based profilometers are limited to sampling measurements, and cannot perform 100% die inspection for process characterization.

It is thus desirable to have an automated feature measurement system capable of measuring features at precise locations on different topology on wafers in both sampling and full inspection modes.

Specifically, feature measurement for wafer bumping comprises the following configurations (FIGURE 1):

HVM Fig 1

a) Cu RDL feature height measurement after Cu electro-plating, where the sputtered metal seed layer to enable Cu plating remains on the first layer polyimide surface

b) Final Cu RDL feature thickness measurement on first layer polyimide surface (PI-1) after the Cu seed layer is etched away. Accurate final Cu RDL thickness measurement would require a good gauging of the PI-1 thickness underneath, especially if the topology is not flat.

c) Cu UBM feature height measurement after Cu electroplating

d) Final Cu UBM feature thickness measurement on second layer polyimide surface (PI-2)

The development for automated feature measurement proceeded in two phases: (Phase-1) Cu step height highlight measurement on reflective metal surfaces, and (Phase-2) Cu thickness and polyimide thickness measurement on non-reflective surfaces.

Phase-1: Auto Cu height measurement

In this phase, the 3D inspection (3DI) system commonly used for solder bump height (typically greater than 20μm) measurement is explored for auto Cu feature height measurement. Typical 3DI system such as Rudolph’s WaferScanner, is equipped with the 3D triangulation laser sensor (FIGURE 2). Laser triangulation, where a laser is directed at the wafer surface at an angle of 45° and focused to a spot size of 8μm, provides fast, precise measurements of bump height and coplanarity. Through a combination of laser-scanning and wafer movement, the beam scans the entire wafer surface. A lens collects the reflected/scattered laser light and focuses it on a position sensitive detector.

HVM Fig 2

To enable Cu feature height measurement (typically in the range of 2- 20μm), the Triangular laser sensor was redesigned with a spot size of 5μm, providing accuracy down to +/-0.2 μm. The laser scanning algorithm was also improved from an array to a stagger method to improve the repeatability of scanning signals. As Cu feature height measurement is influenced by the surrounding topology, the ability to select any datum for measurement is critical. This was achieved through the integration of camera-based 2D inspection to the improved triangular laser sensor system using the developed datum selection program. An automated height measurement report can be conveniently generated for further analysis through the program (FIGURE 3).

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

To verify the consistency of measurement performance, both the improved 3D triangulation laser sensor system and contact profilometer were used to measure feature Cu height on correlation device wafers. It confirmed that the automated 3D triangulation laser sensor system registers statistically similar Cu feature height mean compared to the manual contact profilometer, but required only one-fifth of the measurement time taken by the profilometer. Wafer bumping facilities which already have an existing pool of 3DI inspection tools can be modified to extend measurement application to Cu feature height without the need for excessive new investment.

Phase-2: Auto Cu/ PI thickness measurement

While a strong signal can be derived using the 3D triangular laser signal for Cu feature height measurement after electroplating (Fig. 1, a and c), it is more difficult to establish a stable signal for Cu feature height measurement after the reflective metal seed layer is etched away, and a reference datum needs to be established on the remaining transparent polyimide surface (Fig. 1, b and c). Several conventional methods exist for non-contact measurement of step heights, such as various confocal sensors, triangulation sensors, and scanning white light interferometry. These sensors typically have difficulty differentiating between reflections from the top and bottom surfaces of a layer, that is, layer thickness. This limitation comes from the depth of focus of the objective, which in turn depends on its numerical aperture (NA). Thus, for all these techniques, sensor performance is highly dependent on objective lens.

To overcome this technical constraint, it was necessary to develop a metrology system that can measure concurrently the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This can be achieved through the integration of reflectometry and visible light interferometry principles [3]. In this method, the direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature. This technique is called the visible thickness and shape sensor (VT-SS) system.

In the following sections we provides further description of how the VT-SS system can be adapted for feature height/thickness measurement on varying topology and opaque materials. For this work, we used the Rudolph Technologies NSX System configured with the VT-SS sensor.

VT-SS system MSA study

Measurement system analysis (MSA) seeks to qualify a measurement system for use by quantifying its accuracy, precision and stability. VLSI standard wafers with 8μm, 24μm, and 48μm step heights were used to assess gauge repeatability and reproducibility (GR&R) and accuracy of the VT-SS system, as well as system correlation on two different NSX Systems (tool matching) that were retrofitted with the VT-SS system.

A. Gauge repeatability and reproducibility
For the GR&R study, a total of ten parts on VLSI wafers (4 parts from 8μm, 3 parts from 24μm and 48μm respectively) were measured three times each, including wafer loading and unloading. FIGURE 4 shows gauge R&R for VT-SS is 1.35% of tolerance and fully meeting AIAG standard of <10%.

HVM Fig 4

B. Accuracy
Step height measurement accuracy was evaluated by means of bias and linearity analysis using the VLSI step height wafers. For this study, one location on each standard wafer was measured ten times and compared to the VLSI specification for the wafer.

Based on the studies in FIGURE 5, measurement with VT-SS system shows an average bias of 0.95%, and linearity error of 0.0059%, meeting the AIAG standard of <5%.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

C. Correlation of Multiple Systems
Having established VT-SS capability, the next evaluation is system correlation on multiple tools of the same configuration. The same VLSI wafers described above were measured on a second system with the same hardware and software configuration.

HVM Table 1

A summary of results are shown in TABLE 1, and a detailed example of the 24μm step height is shown in FIGURE 6. For each wafer, the two systems produce similar results, with an offset that ranges from approximately 10nm to 30nm. Considering that the measurement uncertainty is on the order of 5nm (1-), the small system offset is within expectations.

HVM Fig 6

VT-SS system application assessment

VT-SS system allows capturing of both the transparent polyimide thickness and opaque Cu feature height with a single scan from polyimide layer to Cu feature. From the part of the scan covering the polyimide, signals representing the direct measure of the polyimide thickness, the distance to the first surface of the polyimide, and the distance to a metal surface under the passivation stack are measured. The direct measure of the polyimide thickness is the measurement a standard spectroscopic reflectometer would produce. In that part of the scan where the sensor spot illuminates the Cu step height, the direct thickness peak and one of the distance peaks disappear. Only a distance peak to the surface of the Cu feature is present since the copper is opaque. The Cu step height above the first polyimide layer is then determined from the appro- priate distance measures from each part of the scan. Thus, all the desired thickness and Cu thickness measurements are reported.

To aid interpretation of measured signal peaks, a visualization program was developed for automated generation of feature thickness. FIGURE 7 shows an illustration of the program interface for visualization of measured thickness. Raw data can also be exported for further analysis.

HVM Fig 7

A. VT-SS Cu RDL Layer thickness measurement
To assess VT-SS system’s measurement performance on an actual device feature, it was used to measure the Cu feature RDL thickness layer above the first polyimide (PI) layer (refer to Fig. 1, for a pictorial illustration) on a correlation device wafer. The measured RDL thickness was then cross verified with the actual measured Cu feature step height from a contact profilometer and WaferScanner

B. VT-SS Polyimide cum RDL layer Thickness
Further evaluation of the VT-SS system accuracy was achieved through comparison with cross sectional scanning electron microscopy (X-SEM) measurements. X-SEM allows evaluation of both RDL step height and PI thickness (Fig. 1, b). As discussed above the measurement sensor has the unique capability to simultaneously measure step height, i.e. a distance measurement, and film thickness. Both types of measurements must be independently evaluated for accuracy.

Conclusion

We have reported the development of VT-SS-based system on a fully automated platform for in-line process measurement of wafer bumping processes. This new metrology integrates both reflectometry and visible light interferometry principles. Based on MSA studies, VT-SS on a fully automated platform is a precise, accurate and fast metrology system. Engineering validations have shown VT-SS is highly capable in measuring critical dimensions such as RDL/UBM metal thickness, transparent polyimide/ passivation thickness, and feature sizes in one single step. It relieves the current constraints imposed by existing measurement tools on in-line process control, especially in a high mix, high volume production environment. This allows WLCSP production to move to new milestones of quality, yield, cycle time and productivity.

Acknowledgment

The authors would like to thank Harry Kam of STATSChipPAC Singapore (SCS) for his sponsorship in this project, and other team members from SCS and Rudolph Technologies, Inc. for supporting the development work.

References
1. Yole Development, WLCSP Market & Industrial Trends: 2012, Jan2012
2. Robert F. Kunesh, “Wafer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space”, Adv. Microelectronics, Jan/Feb 2013, Vol. No.1, pp14-16.
3. J. Schwider and Liang Zhou, “Dispersive Interferometric Profilometer,” Opt. Lett., Vol. 19, p. 995, 1994.

JIN YOU ZAO is with STATS ChipPAC in Singapore, and JOHN THORNELL is with Rudolph Technologies, Inc., in Bloomington, MN.

 GLOBALFOUNDRIES today launched a new semiconductor technology developed specifically to meet the ultra-low-power requirements of the next generation of connected devices. The “22FDX” platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies, providing an optimal solution for the rapidly evolving mainstream mobile, Internet-of-Things (IoT), RF connectivity and networking markets.

While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications by leveraging the industry’s first 22nm two-dimensional, fully-depleted silicon-on-insulator (FD-SOI) technology. It offers industry’s lowest operating voltage at 0.4 volt, enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Sanjay Jha, chief executive officer of GLOBALFOUNDRIES. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”

22FDX leverages the high-volume 28nm platform in GLOBALFOUNDRIES’ 300mm production line in Dresden, Germany. This technology heralds a new chapter in the “Silicon Saxony” story, building on almost 20 years of sustained investment in Europe’s largest semiconductor fab. GLOBALFOUNDRIES launches its FDX platform in Dresden by investing $250 million for technology development and initial 22FDX capacity. This brings the company’s total investment in Fab 1 to more than $5 billion since 2009. The company plans to make further investments to support additional customer demand. GLOBALFOUNDRIES is partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering.

GLOBALFOUNDRIES’ 22FDX platform enables software-control of transistor characteristics to achieve real time tradeoff between static power, dynamic power and performance. This platform consists of a family of differentiated products architected to support the needs of various applications:

  • 22FD-ulp: For the mainstream and low-cost smartphone market, the base ultra-low power offering provides an alternative to FinFET. Through the use of body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.
  • 22FD-uhp: For networking applications with analog integration, this offering is optimized to achieve the same ultra-high performance capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.
  • 22FD-ull: The ultra-low leakage offering for wearables and IoT delivers the same capabilities of 22FD-ulp, while reducing leakage to as low as 1pa/um. This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.
  • 22FD-rfa: The radio frequency analog offering delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.

GLOBALFOUNDRIES has been working closely with key customers and ecosystem partners to enable optimized design methodology and a full suite of foundational and complex IP. Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.

Strong support from Customers and Partners for 22FDX

​“GLOBALFOUNDRIES’ FDX platform, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum of this technology by expanding the ecosystem and assuring a source of high-volume supply,” said Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”

“Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino vice president of applications processors and advanced technology adoption for Freescale’s MCU group.  “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”

“The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the IP ecosystem needed for customers to benefit from the unique value of 22FDX technology.”

“VeriSilicon has experience designing IoT SoCs in FD-SOI technology and we have demonstrated the benefits of FD-SOI in addressing ultra-low power and low energy applications,” said Wayne Dai, president and CEO of VeriSilicon Holdings Co. Ltd. “We look forward to collaborating with GLOBALFOUNDRIES on their 22FDX offering to deliver power, performance and cost optimized designs for smart phones, smart homes, and smart cars especially for the China market.”

“Next-generation connected devices, in markets from wearables and IoT to mobile and consumer, require semiconductor solutions that provide an optimal balance of performance, power and cost,” said Tony King-Smith, EVP Marketing, Imagination Technologies. “The combination of GLOBALFOUNDRIES’ new 22FDX technology with Imagination’s broad portfolio of advanced IP – including PowerVR multimedia, MIPS CPUs and Ensigma communications – will enable more innovation by our mutual customers as they bring differentiated new products to the market.”

“FD-SOI technology can provide a multi-node, low-cost roadmap for wearable, consumer, multimedia, automotive, and other applications,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ 22FDX offering brings together the best in low-power FD-SOI technology in a low-cost platform that is expected to experience very strong demand.”

“FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie-Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES’ 22FDX for connected technologies.”

“GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology.”

Engineered SOI substrates are now a mainstream option for the semiconductor industry.

BY MARIAM SADAKA and CHRISTOPHE MALEVILLE, Soitec, Austin, TX and Grenoble, France

The number of mobile subscribers worldwide reached 95.5% of the world’s population in 2014 and is expected to reach 9.3B by 2019 (1). This fast growing trend is driving end markets towards satisfying stringent demands of mobile connected users. Whether it is a smartphone or a wearable device, the key requirements include low cost, extended battery life, more functionalities, smaller form factor, and fast time to market. In an effort to bring more performance, more functionality or less power consumption, innovation starting at the substrate level has demonstrated significant achievements. This includes implementing planar Fully Depleted Silicon-On- Insulator (FD-SOI) devices with full back bias capability to extend Moore’s Law beyond 28nm and meet power/ performance/cost requirements for low power SoCs. In addition, using High Resistivity SOI for integrating the RF Front End Module (FEM) providing significant die cost advantage with increased performance and functionality. In this paper, engineered substrates for next generation ultra-low power integrated digital and RF devices and other emerging applications will be discussed.

Device scaling and device functional diversification

Device scaling has been following Moore’s law for the last five decades, doubling transistor density every two years, bringing higher performance, more functionality at lower cost. To maintain this trend, the industry implemented non-classical ways to continue on the scaling path. This started with innovation at the material level, then innovation at the device structure level demonstrating improved electrostatic control enabled by fully depleted (FD) devices (FIGURE 1). FD devices include planar FD-SOI, vertical FinFET or multi-gate device structures. FD-SOI is a great example of device scaling in the substrate era, where the engineered substrate provides the fully depleted structure that solves the variability challenge and enables body bias capabilities to meet the power/performance and cost requirements for low power consumer SoCs.

FIGURE 1. Technology migration history [2].

FIGURE 1. Technology migration history [2].

The semiconductor industry also has another key focus called More-Than-Moore. This new trend provides added non-digital functional diversification without necessarily scaling according to Moore’s Law. More- than-Moore technologies cover a wide range of domains, and there are numerous examples where advantages brought by substrate engineering enable better perfor- mance and more functionality. With the increasing demand for wireless data bandwidth and the emergence of LTE Advanced, new RF devices with higher levels of integration and more stringent specifications need to be developed. RF-SOI substrates are a great example of how engineered substrates play a major role in achieving the needed level of performance and integration. Two generations of High Resistivity SOI (HR-SOI) substrates compatible with standard CMOS processing were developed [3]. While Gen 1 HR-SOI is well suited for 2G and 3G requirements, Gen 2 HR-SOI enables much higher linearity and isolation meeting most stringent LTE Advanced requirements and thus is paving the way for higher levels of integration with better performance at an improved cost (FIGURE 2).

FIGURE 2. Soitec’s RF-SOI leadership from ideas to high volume manufacturing.

FIGURE 2. Soitec’s RF-SOI leadership from ideas to high volume manufacturing.

UTBB FD-SOI substrates

FD-SOI with ultra-thin Box, known as Ultra-Thin-Body and Box (UTBB) substrates, are an attractive candidate for extending Moore’s Law at 28nm and beyond while keeping the cost benefit from shrinking. UTBB FD-SOI devices represent an extension of the planar device archi- tecture demonstrating several advantages essential to low power SoCs.

FD-SOI devices have excellent immunity to Short Channel Effects (SCE) leading to improved sub-threshold swing and Drain-Induced Barrier Lowering (DIBL), and minimum Random Dopant Fluctuation (RDF), thanks to the undoped channel. This ensures lowest Vt variation [4,5], improves performance at lower Vdd as well as improves SRAM and analog mismatch and analog gain, allowing superior digital/analog co-integration [6].

UTBB FD-SOI devices combine the advantage of tuning the front gate and back gate work function [4] as well as enabling effective back bias capabilities for multi-Vt options (FIGURE 3). The back bias capability is a unique feature that enables Vt modulation for better trade-off of power and performance and can be effectively applied in a static or dynamic mode. Moreover, UTBB FD-SOI back bias capabilities show no degradation with scaling and offer a wider range of biasing versus bulk at no area penalty [5].

FIGURE 3. UTBB FD-SOI with Back Bias (Courtesy of ST Microlectronics).

FIGURE 3. UTBB FD-SOI with Back Bias (Courtesy of ST Microlectronics).

UTBB FD-SOI is a scalable technology supporting at least three nodes; 28nm, 14nm and 10nm (FIGURE 4A). The technology satisfies density/area, performance and power saving requirements without a disruptive change in device architecture and integration. Today, available foundry offerings demonstrate competitive performance at 28 & 22nm [1,7] and the technology is proven down to 10nm [8]. Scaling requires thinner SOI and BOX. In order to alleviate the constraints on SOI film thickness reduction, a scaling sequence based on different BOX layer thickness was proposed, FIGURE 4B [9]. SOI substrates with 25nm BOX are already in production and 10 nm BOX has been demon- strated. Furthermore, the substrate roadmap beyond 14nm includes substrate strain engineering providing the advantage of enhancing the carrier mobility independent of device pitch. This includes strained silicon directly on insulator (SSOI) or strained SiGe- On-Insulator (SGOI) [10].

FIGURE 4. (a) UTBB FD-SOI Device integration supporting three nodes (11) (b) SOI/BOX thickness scaling ensuring a DIBL of 100 mV/V or below down to 7 nm node [9].

FIGURE 4. (a) UTBB FD-SOI Device integration supporting three nodes (11) (b) SOI/BOX thickness scaling ensuring a DIBL of 100 mV/V or below down to 7 nm node [9].

FD-SOI devices are planar devices that are fully compatible with mainstream CMOS processing, designs and EDA tools, providing a faster time to market solution. In addition to fully leveraging conventional CMOS processes, FD-SOI process integration is simpler than bulk (FIGURE 5) [1, 12]. FD-SOI process saves several masks and process steps typically included for Vt tuning and for the integration of uniaxial stressors needed to boost performance in planar and FinFET bulk [13, 14]. Even with the drastically increasing lithography cost, such process simplifications more than compensate for the SOI substrate cost, resulting in a lower overall processed wafer cost [11].

FIGURE 5. 28nm FD-SOI vs. 28LP process (courtesy of ST Microelectronics).

FIGURE 5. 28nm FD-SOI vs. 28LP process (courtesy of ST Microelectronics).

While the vertical FinFET device features excellent gate control and high density/performance per area, it also requires a disruptive change in process and design resulting in higher cost and longer time to market. For applications that require the ultimate performance/ digital integration and large die size, vertical FinFETs are a good solution. For other applications that cannot afford the FinFET solution, such as cost sensitive low-mid end mobile consumer applications, FD-SOI is a great candidate for providing low power/high performance and more analog integration capabilities with the least process and design disruption for low cost and fast time to market. Furthermore, FD-SOI devices with back bias can operate at voltages as low as 0.35V [15,16] without area and costly design penalties making them excellent candidates for Ultra-Low Power (ULP) applications. FD-SOI devices consume less energy than bulk at the MEP (Minimum Energy Point) and maintain the smallest energy per cycle with higher operating frequency across the whole Vdd range [17, 18]. This makes UTBB FD-SOI technology a very attractive option for enabling ULP cost sensitive IoT applications.

Smart Cut enabling uniformity for Vt variability control

FIGURE 6: The Smart Cut process.

FIGURE 6: The Smart Cut process.

Optimization of the conventional Smart Cut process is essential for delivering ultra-thin SOI and BOX with well controlled wafer-to-wafer and within-wafer uniformity (FIGURE 6). The Smart Cut unique uniformity control relies on several key aspects of the process [19]: (a) A highly uniform thermal oxidation of a donor wafer to form the BOX (b) A conformal hydrogen implant through the oxide to define the separation plane in the Silicon (c) A high temperature anneal to eliminate the SOI roughness while keeping excellent on-wafer SOI uniformity (20). Developing an efficient smoothing process to eliminate the Si roughness is critical for ensuring low transistor Vt variability. This requires Si thickness monitoring across the entire range of the spatial frequency. As existing ellipsometry and AFM characterizations are necessary but not sufficient, Soitec developed Differential Reflective Microscopy (DRM) to address the 100um scale SOI roughness. Consequently, bridging the gap between ellipsometry and AFM and providing a complete picture of surface roughness crucial for controlling Vt variations at the transistors level (FIGURE 7).

FIGURE 7. SOI layer thickness control.

FIGURE 7. SOI layer thickness control.

As the FD-SOI substrate plays a key role in defining the device structure, substrate local and global thickness control is very important. This is especially true for UTBB FD-SOI devices, where the BOX thickness affects the efficiency of Vt tuning through back biasing, and the channel thickness uniformity and roughness influence the electrostatics of the device and Vt variation respectively. Today, Soitec guarantees volume production of SOI 12nm ±5Å and BOX 25nm ±10Å (6 sigma value, all sites, all wafers). When benchmarking variability; planar FD-SOI exhibits the best performance compared to Bulk technologies [4, 5]. Global variability is also reduced and maximum TSi dispersion (TSi,max) obtained on 300mm wafers is already satisfying the objective for Vt variability for advanced technology nodes [4].

High resistivity SOI substrates

The rapid adoption of new wireless standards and the increasing demand for data bandwidth requires RF IC designers to develop devices with higher levels of integration, meeting more and more stringent specification levels. The engineered substrates on which those devices are manufactured play a major role in achieving that level of performance. The improved high frequency performance of CMOS with process shrinks, and the availability of CMOS foundry technol- ogies on 200 or 300mm substrates has made it possible to have high volume fabrication of integrated Si based RF systems, including high quality passive devices [21,22] and RF switches and power amplifiers on SOI substrates [23]. Historically, switches and power amplifiers were built on gallium arsenide (GaAs) substrates. Since 2008, RF-SOI has progressively displaced GaAs and silicon-on- sapphire technologies by offering the best cost, area and performance for RF switches, and thus becoming the mainstream technology solution adopted by the majority of RF foundries [24].

Gen 2 HR-SOI engineered substrates

FIGURE 8. Silicon uniformity requirements to meet ITRS variability roadmap [4].

FIGURE 8. Silicon uniformity requirements to meet ITRS variability roadmap [4].

Typical SOI substrates do not have thick enough BOX to prevent the electrical field from diffusing into the substrate, inducing high-frequency signal losses, non-linearity and crosstalk which are detrimental to RF performance. To improve the insertion loss, harmonic distortion and isolation performance required for switches, the bulk base substrate of an SOI substrate was replaced by a high-resistivity base substrate known as Gen 1 HR-SOI. The adoption of Gen 1 HR-SOI wafers for RF applications has allowed monolithic integration of RF FEM, leading to smaller size, better reliability, improved performance and lower system cost [25, 26]. While first generation substrates are well suited for 2G and 3G applications, they suffer from the a parasitic surface conduction (PSC) layer induced under the BOX due to fixed oxide charges which attract free carriers near the Si/SiO2 interface. This drastically reduces the substrate effective resistivity by more than one order of magnitude, limiting the substrate capability in meeting the next step in performance for LTE advanced standards (FIGURE 9).

FIGURE 9. Gen 2 HR-SOI Substrate.

FIGURE 9. Gen 2 HR-SOI Substrate.

To address this intrinsic limitation, Soitec and Université Catholique de Louvain (UCL) developed a second gener- ation (Gen 2) HR-SOI substrate with improved effective resistivity as high as 10KOhm.cm (FIGURE 10). This was achieved by adding a trap-rich layer underneath the buried oxide to freeze the PSC. These traps originate from the grain boundaries of a thin polysilicon layer added between the BOX and high resistivity substrate [27]. The high resistivity characteristics of Gen 2 HR-SOI substrates are conserved after CMOS processing, enabling very low RF insertion loss (< 0.15 dB/mm at 1 GHz), low harmonic distortion (-40dB) along coplanar waveguide (CPW) transmission lines, and purely capacitive crosstalk close to quartz substrates (FIGURE 11). It was further demon- strated that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors [28]. With second generation HR-SOI products, RF IC performance is further advanced meeting more stringent losses, coupling and non-linearity specifications (FIGURE 12) [25].

FIGURE 10. Measured effective resistivity of Gen 1 HR- SOI and trap-rich Gen 2 HR-SOI (TRSOI). Both use 10 kOhm.cm nominal resistivity handle Si substrate [25].

FIGURE 10. Measured effective resistivity of Gen 1 HR- SOI and trap-rich Gen 2 HR-SOI (TRSOI). Both use 10 kOhm.cm nominal resistivity handle Si substrate [25].

FIGURE 11. (a) Measured crosstalk comparing Gen 2 HR-SOI (TR SOI), Gen 1 HR-SOI and quartz [25] . (b) Measured harmonic distortion along a CPW line, on standard SOI (~ 10ohm.cm) and Gen 1 HR-SOI (~ 1 kOhm.cm) and Gen 2 HR-SOI (TR-SOI) (~ 10 kOhm.cm).

FIGURE 11. (a) Measured crosstalk comparing Gen
2 HR-SOI (TR SOI), Gen 1 HR-SOI and quartz [25] . (b) Measured harmonic distortion along a CPW line, on standard SOI (~ 10ohm.cm) and Gen 1 HR-SOI (~ 1 kOhm.cm) and Gen 2 HR-SOI (TR-SOI) (~ 10 kOhm.cm).

FIGURE 12. Harmonic two and three measured on CPW on commercially available versions of Gen 2 HR- SOI (eSi) substrates.

FIGURE 12. Harmonic two and three measured on CPW on commercially available versions of Gen 2 HR- SOI (eSi) substrates.

Because the trap-rich layer in Gen 2 HR-SOI substrates is integrated at the substrate level, additional process steps and consequently more conservative design rules are no longer needed, leading to a more cost effective process and a possible smaller die area per function. Gen 2 HR-SOI substrates now enable RF designers to add diverse on-chip functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity at lower cost than traditional technologies (FIGURE 13). It also brings clear benefits for the integration of passive elements, such as high quality factor spiral inductors [29], tunable MEMS capacitors [30], as well as reducing the substrate noise between devices integrated on the same chip. Beyond performance, RF-SOI offers a unique advantage to further reduce board area by integrating all FEM devices on the same die [3].

FIGURE 13. Gen 2 HR-SOI (eSi) substrates, advantages vs Gen 1 HR-SOI substrate.

FIGURE 13. Gen 2 HR-SOI (eSi) substrates, advantages vs Gen 1 HR-SOI substrate.

In addition to innovation at the substrate level, Soitec developed the characterization needed to predict the RF Harmonic Quality Factor (HQF) at the substrate level and before device/circuit manufacturing. The characterization method is based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide (FIGURE 14). This essential metrology step is used today throughout the Soitec product line to ensure Gen 2 HR-SOI SOI substrates provide the expected RF performance at the device level.

FIGURE 14. Harmonic Quality Factor (HQF) methodology.

FIGURE 14. Harmonic Quality Factor (HQF) methodology.

New substrates for new collaborations

As demonstrated, UTBB FDSOI and Gen 2 HR-SOI substrates are well positioned to address ULP IoT and mobile connectivity applications that will respectively require drastic power reduction and higher frequency bands at very low cost. Combining advanced CMOSprocess capabilities with the demonstrated benefit of engineered SOI substrates is paving the way for digital and RF integration for next generation cost sensitive integrated ULP mobile connected devices.

Furthermore, there are multiple examples where innovative substrate engineering can address roadmap challenges, enable further integration; provide differ- entiation in final product at a more efficient cost and footprint. Some examples of different application segments include: Photonics, Imaging sensors, advanced FinFET (TABLE 1).

Substrate Table 1

Looking beyond a wafer and an application, entering the substrate era requires critical partnerships across the entire ecosystem. This includes having an augmented collaboration along the value and supply chain, covering collaborations with material, equipment and substrate suppliers as well as collaborations with foundries, IDMs and fabless companies. Soitec greatly supports this model and believes in establishing strong collaborations to seed future critical innovations.

Conclusion

Engineered SOI substrates are now a mainstream option for the semiconductor industry adopted by several foundries. UTBB FD-SOI substrates enable planar fully depleted devices with full back bias capability to extend Moore’s Law at 28nm and beyond providing excellent power/performance/cost benefits. Gen 2 HR-SOI substrates enable FEM integration and higher linearity and isolation meeting stringent performance requirements for advanced standards at an improved cost. Combining advanced CMOS process capabilities with the demonstrated benefit of engineered SOI substrates is paving the way for digital and RF integration for next generation cost sensitive integrated ULP mobile connected devices. As such, engineered SOI substrates are well positioned to serve future integrated IoT applications.

Acknowledgement

The authors would like to thank Bich-Yen Nguyen and Eric Desbonnets for their valuable contribution and constructive discussions.

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MARIAM SADAKA is a Soitec fellow based in Austin, TX and CHRISTOPHE MALEVILLE is Senior Vice President, Digital Electronics Business Unit for Soitec, Grenoble, France.