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Leti_Jean-Eric_MichalletBy Jean-Eric Michallet, Leti Vice President of Sales and Marketing

Smart devices for the Internet of Things are among the top three growth drivers for the semiconductor industry, but the IoT is a highly fragmented market where multiple applications have varying energy requirements.

Speaking at a session on “Consumer & Energy Efficiency” at the LetiDays annual event in Grenoble, France, Edith Beigné, a senior scientist in the Architecture, ID Design, and Embedded Software Department at CEA-Leti, said the fragmentation presents challenges for technology providers, because it is difficult and expensive to design a single chip for one application or to provide a software or hardware platform to cover each archetype.

Leti’s new Internet of Things platform, L-IoT, is designed to overcome the challenges of fragmentation by providing a complete, flexible ultra-low power solution with adaptable analog and digital building blocks globally optimized for high energy efficiency and that “sleep” when energy-supply is low. All functionality, except the sensors, is integrated on a single chip.

L-IoT: a Flexible Platform

LetiDays 2-1

Adaptive Always-Responsive/On-Demand, according to energy levels

Known as “Elliot”, the platform includes both an “always-on” subsystem and “on-demand” subsystem. For applications such as video surveillance, secure communications, data fusion and tracking and monitoring, for example, the “on-demand” system can be woken up to provide additional data, as needed.

The application may have a variety of power sources for the “on-demand” tasks, but energy harvesting is the preferred choice, Beigné said.

Silicon Impulse

Leti also recently introduced Silicon Impulse, a comprehensive IC technology platform offering IC design, advanced intellectual property, emulator and test services and industrial multi-project wafer (MPW) shuttles. The eight-member consortium supporting the platform offers leading-edge, hardware-and-software solutions, including embedded software dedicated to geo-location and people location, for instance; subsystems such as 3D multi-core and low-power CPU modules, and a wide range of ICs: FD-SOI, RF, sensors, mixed-signal, MEMS and NEMS and 3D devices.

Caroline Arnaud, head of the Platform and Design Center Department at Leti, said the platform supports 28nm FD-SOI now, and Leti is in discussions with GLOBALFOUNDRIES for access to 22nm technology next year.

From sensor fusion to context awareness

Vivian Cattin, Leti project Manager, outlined future consumer applications that context-awareness technology can provide. She summarized Leti’s ongoing work with InvenSense, the world’s leading provider of MotionTracking sensor system-on-chip (SoC) and sound solutions for consumer electronic devices. In 2014, the company acquired the Leti spinout Movea, which was widely recognized for its advanced software for ultra-low-power location, activity tracking and context sensing.

The continuing collaboration is focused on improving context awareness by combining data from a variety of sensors, including accelerators and gyrometers, with other sources, such as WiFi beacons and the GPS systems from a person’s mobile device, to not only locate the person but estimate his or her direction or trajectory. The application also can estimate the travel time to the destination.

Cattin said a next step, called “user-adaptive processing”, would combine additional sensors, including wearable devices, software that supports machine learning, and the user’s own cloud-based information to support new uses such as personal wellness tips.

Less energy, more powerful applications for consumers

Jean-Michel Goiran, IoT business-development manager at Leti, highlighted Leti programs and projects that provide more powerful applications for consumers in the Internet of Things era, while using less power.

Connected sensor nodes typically reserve two-thirds of available power in standby mode for the microprocessor, while 13 percent is used by the sensor, 11 percent by the radio, and 10 percent by the active microprocessor. “We need an ultra-low standby-power solution for sustainable and long-living IoT devices deployment,” he said.

Non-volatile memory will be a big part of the solution for better standby-power management, because its content doesn’t require periodic refreshing. Super directivity, which refers to very small antennas directing their signals in only one direction, are another energy saver for IoT applications. Mutualizing functions on a single sensor, such as C02 detection, ventilation, presence detection and fire alarms, also can significantly lower power demand. “You need energy for sensors, so the fewer sensors the better,” Goiran said.

Wired houses for energy efficiency and security

Joël Mercelat, chief technical officer at Delta Dore, described a fully connected house that provides enhanced security and maintains residents’ preferred heating/cooling and lighting preferences, while cutting energy use. These functions are automated, but also can be controlled be hand-held devices.

Read more from CEA-Leti: 

What chipmakers will need to address growing complexity, cost of IC design and yield ramps

 

IBM Research today announced that working with alliance partners at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) it has produced the semiconductor industry’s first 7nm (nanometer) node test chips with functional transistors. The breakthrough underscores IBM’s continued leadership and long-term commitment to semiconductor technology research.

The accomplishment, made possible through IBM’s unique public-private partnership with New York State and joint development alliance with GLOBALFOUNDRIES, Samsung and equipment suppliers, is driven by the company’s $3 billion, five-year investment in chip R&D announced in 2014. Under that program, IBM researchers based at SUNY Poly’s NanoTech Complex in Albany are pushing the limits of chip technology to 7nm node and beyond to meet the demands of cloud computing and Big Data systems, cognitive computing and mobile products.

Developing a viable 7nm node technology has been one of the grand challenges of the semiconductor industry. Pursuing such small dimensions through conventional processes has degraded chip performance and negated the expected benefits of scaling — higher performance, less cost and lower power requirements. Microprocessors utilizing 22nm and 14nm technology power today’s servers, cloud data centers and mobile devices, and 10nm technology is well on the way to becoming a mature technology, but 7nm node has remained out of reach due to a number of fundamental technology barriers. In fact, many have questioned whether the traditional benefits of such small chip dimensions could ever be achieved.

The IBM 7nm node test chip with functioning transistors was achieved using new semiconductor processes and techniques pioneered by IBM Research. Developing it required a number of first-in-the-industry innovations, most notably silicon germanium (SiGe) channel transistors and extreme ultraviolet (EUV) lithography integration at multiple levels.

By introducing SiGe channel material for transistor performance enhancement at 7nm node geometries, process innovations to stack them below 30nm pitch and full integration of EUV lithography at multiple levels, IBM was able to achieve close to 50 percent area scaling improvements over today’s most advanced 10nm technology. These efforts could result in at least a 50 percent power/performance improvement for the next generation of systems that will power the Big Data, cloud and mobile era.

The 7nm node milestone continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

IBM and SUNY Poly have built a highly successful, globally recognized partnership at the multi-billion dollar Albany NanoTech Complex, highlighted by the institution’s Center for Semiconductor Research (CSR), a $500 million program that also includes the world’s leading nanoelectronics companies. The CSR is a long-term, multi-phase, joint R&D cooperative program on future computer chip technology. It continues to provide student scholarships and fellowships at the university to help prepare the next generation of nanotechnology scientists, researchers and engineers.

Related news: 

IBM announces $3B research initiative

GLOBALFOUNDRIES completes acquisition of IBM Microelectronics business

By David W. Price and Douglas G. Sutherland

Author’s Note: This is the eighth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

Moving to the next design rule can be stressful for the inspection and metrology engineer. Like everything else in the fab, process control generally doesn’t get any easier as design rules shrink and new processes are introduced.

The eighth fundamental truth of process control for the semiconductor IC industry is:

Process Control Requirements Increase with Each Design Rule

This statement has proven to be historically accurate, as evidenced by the increase in process control spending as a percentage of wafer front-end (WFE) total costs. This article, however, will focus on a few of the forward-looking observations that we believe will further accelerate the adoption of process control.

The historical increase in process control with shrinking design rules has been driven largely by the introduction of key technical inflections. Recent examples for logic/foundry include immersion lithography, high-k metal gates, gate-last integration, and FinFET transistor structures. These high profile process changes required enormous engineering focus and led to the implementation of new inspection and metrology steps to characterize the associated defectivity and drive yield learning.

While the industry will continue to face significant technical challenges (next-generation lithography being the most obvious example), there is another factor emerging which will play an equally large role in setting the inspection and metrology strategy for the 16/14nm design node and beyond.

Figure 1 shows the number of process steps as a function of design rule for a generic logic/foundry process. Up to the 20nm node, there has been a very modest increase in process steps with design rule shrinks due to, for example, more metal levels and the addition of hard mask steps. But starting at 16/14nm, there will be an unprecedented increase in the number of process steps. This jump in process steps will be driven by:

  • The shift from 2D to 3D transistor structures in both logic and memory
  • More complicated integration in both the front end and back end
  • The push-out of EUV lithography, leading to massive numbers of multi-patterning steps

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Process Tool Defectivity

Because of this increase in process steps—and the accumulative nature of yield loss—fabs must reduce the defectivity at each individual step in order to achieve the same final yield. Figure 2 shows the total yield as a function of the number of process steps where the average per-step yield is held constant. Prior to 16/14nm, this effect was scarcely noticeable since the total increase in process steps was minimal.

Moving forward, fab defect reduction teams must continue to resolve the challenging new technical inflections. But they must also place more focus on driving down defectivity at all process steps:

  1. Line Yield: To maintain the same line yield (wafers out / wafers in), there must be fewer excursions and less scrap at each step
  2. Die Yield: Every operation in the fab must be held to a tighter specification for defect density (D0) and variation (Cpk)

To make matters worse, defect inspection and metrology operations will continue to become more difficult. The defect count must go down even as the number of yield-relevant defects increases and the detection task becomes harder. Similarly, the variability in metrology measurements must be reduced even as those measurements become more difficult to make.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Impact on Cycle Time

The increase in process steps has another downside: increased cycle time. If cycle time increases in proportion to the number of process steps then it follows from Figure 1 that the cycle time will roughly double from the 20nm to the 10nm node. One publication has even suggested that the cycle time may double from 20nm to an advanced 16nm process [2].

The fab’s ability to do yield learning via feedback from electrical test and physical failure analysis (PFA) is directly tied to the “hot lot” cycle time. Longer hot-lot cycle times mean fewer opportunities for these long-loop learning cycles as device manufacturers try to ramp yield and deliver products to market. More emphasis must therefore be placed on in-line yield learning methodologies.

Sampling Pressure

Finally, more process steps will increase the manufacturing cost per wafer. In the second article in this series, Sampling Matters, we showed that the ideal sampling rate (that which provides the lowest total cost to the fab) goes with the square root of the device manufacturing cost. In other words, if the manufacturing cost increases by 30 percent then the corresponding process control sampling rate needs to increase by 14 percent (everything else being constant) to stay at the lowest total cost. This sampling increase will put further pressure on the fab’s inspection and metrology teams.

Summary

In summary, each new design rule will introduce:

  • Technical inflections that require engineering focus and innovation, as well as the implementation of new process control methodologies
  • More process steps that must be directly monitored
  • Tighter controls and lower defect density at each individual step due to the compounding nature of yield loss
  • Longer cycle times, resulting in more reliance on in-line (vs. end-of-line) techniques for yield learning
  • Higher stakes (greater economic impact to the fab) in the event of an excursion due to the higher wafer manufacturing costs, which will put pressure on the fab to increase inspection and metrology sampling

The cascade of challenges that flows from the increase in process steps is sometimes referred to as the “Tyranny of Numbers.” For further exploration of how fabs are adapting their process control strategy for new design rules, please contact the authors of this article.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Lipsky, “TSMC Outlines 16nm, 10nm Plans.” EE Times, 4/8/2015.
  2. Jones, Strategic Cost Model, IC Knowledge, LLC. http://www.icknowledge.com/

Read more Process Watch: 

Time is the enemy of profitability

Know your enemy

The most expensive defect

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

GLOBALFOUNDRIES today announced that it has completed its acquisition of IBM’s Microelectronics business.

With the acquisition, GLOBALFOUNDRIES gains differentiated technologies to enhance its product offerings in key growth markets, from mobility and Internet of Things (IoT) to Big Data and high-performance computing. The deal strengthens the company’s workforce, adding decades of experience and expertise in semiconductor development, device expertise, design, and manufacturing. And the addition of more than 16,000 patents and applications makes GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.

“Today we have significantly enhanced our technology development capabilities and reinforce our long-term commitment to investing in R&D for technology leadership,” said Sanjay Jha, chief executive officer of GLOBALFOUNDRIES. “We have added world-class technologists and differentiated technologies, such as RF and ASIC, to meet our customers’ needs and accelerate our progress toward becoming a foundry powerhouse.”

Through the addition of some of the brightest and most innovative scientists and engineers in the semiconductor industry, GLOBALFOUNDRIES solidifies its path to advanced process technologies at 10nm, 7nm, and beyond.

In RF, GLOBALFOUNDRIES now has technology leadership in wireless front-end module solutions. IBM has developed world-class capabilities in both RF silicon-on-insulator (RFSOI) and high-performance silicon-germanium (SiGe) technologies, which are highly complementary to GLOBALFOUNDRIES’ existing mainstream technology offerings. The company will continue to invest to deliver the next generation of its RFSOI roadmap and looks to capture opportunities in the automotive and home markets.

In ASICs, GLOBALFOUNDRIES now has technology leadership in wired communications. This enables the company to provide the design capabilities and IP necessary to develop these high-performance customized products and solutions. With increased investments, the company plans to develop additional ASIC solutions in areas of storage, printers and networking. The most recent ASIC family, announced in January and built on GLOBALFOUNDRIES’ 14nm-LPP technology, has been well accepted in the marketplace with several design wins.

GLOBALFOUNDRIES increases its manufacturing scale with fabs in East Fishkill, NY and Essex Junction, VT. These facilities will operate as part of the company’s growing global operations, adding capacity and top-notch engineers to better meet the needs of its existing and new customers.

Moreover, the transaction builds on significant investments in the burgeoning Northeast Technology Corridor, which includes GLOBALFOUNDRIES’ leading-edge Fab 8 facility in Saratoga County, NY and joint R&D activities at SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering in Albany, NY. The company’s presence in the northeast now exceeds 8,000 direct employees.

The acquisition includes an exclusive commitment to supply IBM with advanced semiconductor processor solutions for the next 10 years. GLOBALFOUNDRIES also gets direct access to IBM’s continued investment in semiconductor research, solidifying its path to advanced process geometries at 10nm and beyond.

Related news: 

IBM announces $3B research initiative

Research led by Michigan State University could someday lead to the development of new and improved semiconductors.

In a paper published in the journal Science Advances, the scientists detailed how they developed a method to change the electronic properties of materials in a way that will more easily allow an electrical current to pass through.

The electrical properties of semiconductors depend on the nature of trace impurities, known as dopants, which when added appropriately to the material will allow for the designing of more efficient solid-state electronics.

The MSU researchers found that by shooting an ultrafast laser pulse into the material, its properties would change as if it had been chemically “doped.” This process is known as “photo-doping.”

“The material we studied is an unconventional semiconductor made of alternating atomically thin layers of metals and insulators,” said Chong-Yu Ruan, an associate professor of physics and astronomy who led the research effort at MSU. “This combination allows many unusual properties, including highly resistive and also superconducting behaviors to emerge, especially when ‘doped.'”

An ultrafast electron-based imaging technique developed by Ruan and his team at MSU allowed the group to observe the changes in the materials. By varying the wavelengths and intensities of the laser pulses, the researchers were able to observe phases with different properties that are captured on the femtosecond timescale. A femtosecond is 1 quadrillionth, or 1 millionth of 1 billionth, of a second.

“The laser pulses act like dopants that temporarily weaken the glue that binds charges and ions together in the materials at a speed that is ultrafast and allow new electronic phases to spontaneously form to engineer new properties,” Ruan said. “Capturing these processes in the act allows us to understand the physical nature of transformations at the most fundamental level.”

Philip Duxbury, a team member and chairperson of the department of physics and astronomy, said ultrafast photo-doping “has potential applications that could lead to the development of next-generation electronic materials and possibly optically controlled switching devices employing undoped semiconductor materials.”

A semiconductor is a substance that conducts electricity under some conditions but not others, making it a good medium for the control of electrical current. They are used in any number of electronics, including computers.

Bruno Mourey, chef du Département intégration hétérogène sur siliciumBy Bruno Mourey, Chief Technology Officer, CEA-Leti

As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Chief among them for designers and chipmakers are the increased complexity and cost of IC design and yield ramp-ups, and wafer costs, said Carlo Reita, strategic marketing manager at CEA-Leti.

“Disruptive architecture and integration technologies are required,” Reita told participants at the 17th annual LetiDays in Grenoble, France, June 24-25. In his talk, “Technologies and architectures for low-power data processing,” Reita noted the spikes in both complexity and cost that accompany the industry’s progression to smaller technology nodes. The spikes are driven primarily by costly new tools and increases in both design manpower and the number of expensive licenses for software-design tools that accompany increasing device complexity.

Reita cited projections from IBS that industry-wide, non-recurring engineering (NRE) costs will total $38 million for IC designs at the 28nm node, $132 million at the 16nm node and $1.34 billion at the 5nm node.

Adding yield ramp-up costs to IC design costs, which include both new designs and specializations, the projected NREs skyrocket from $59 million at 28nm to $176 million at 16nm and $2.24 billion at 5nm. Meanwhile, the average selling price of 300mm wafers grow from $9,885 at 16nm to $19,620 at 5nm.

Reita noted that such projections underscore the pressure that the industry will face to develop new design-implementation approaches that change the cost metrics for advanced-features, so that initial products can generate revenues that justify the design and yield ramp-up costs.

He said that managing data traffic that is increasing exponentially, while maintaining data-center server performance and lowering the centers’ energy consumption, is among the top challenges for the computing industry in the years ahead. Meanwhile, mobile computing and the Internet of Things are adding a different set of challenges that will feed the design-cost escalation, ranging from the requirement for mandatory long battery life to supporting heterogeneous and power-hungry applications and the capability to adjust to process, voltage and temperature variations.

Reita also outlined Leti’s plans and vision for technologies that address these challenges in the short, medium and longer terms.

Like other speakers during the two-day event, he noted FD-SOI’s advantages compared to FinFET as a proven low-power, cost-effective solution that will meet current and mid-term needs for devices down to the 10nm node. In addition, transistor-stacking options, such as Leti’s low-temperature CoolCube technology, support denser and higher-performing CMOS devices. CoolCube also makes it easier for designers to use heterogeneous integration of material and/or functions and provides a greater degree of freedom for design partitioning, Reita said.

Other avenues of exploration include adaptive fine-grain architecture that mitigates local and dynamic PVT variations, and permits either better use of the chip surface or smaller chips

Leti also is working on resistive RAM that can reduce power consumption at the storage level by putting high-density, non-volatile memory closer to logic chips.

On Leti’s roadmap for the medium term, neuromorphic architectures may enable full transfer of successful algorithms into a specific physical system that will achieve power-efficient computation. Deep recurrent networks with spike coding are a likely candidate to best match physical implementation characteristics.

In Leti’s view, this architecture also allows co-localization of memory and computation similar to a biological system, where a synaptic element performs storage, interconnect and non-linear operations. In addition, the architecture takes full advantage of Leti’s advanced RRAM, 3D and low-power CMOS techniques to break memory-bottleneck and synaptic-density issues, while maintaining ultra low power.

Reita also spoke briefly about quantum computing, “a very long-term” technology possibility, whose appeal includes superposition of the quantum bits (qubits) states in an ultimate parallel system and reversible operators that keep power use at a minimum. This architecture, which is probably 20 years down the road, is expected to massively accelerate computation. It will be best suited for tackling complex optimization problems, Reita said.

Leti collaborates with CEA’s fundamental research departments on topics including SiGe nanowire devices, in which electronics states can act as qubits and use Pauli spin blockade for spin-charge conversion and interaction with CMOS and the external world.

Related news:

Leti workshop covers major trends in FD-SOI technologies

ASCENT project offers unparalleled access to European nanoelectronics infrastructure

Leti launches new Silicon Impulse FD-SOI Development Program

Power transistor sales are forecast to grow 6 percent in 2015 and set a new record high of $14.0 billion following a strong recovery in 2014, which drove up dollar volumes by 14 percent after two consecutive years of decline, according to IC Insights’ 2015 O S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.  In the last six years, power transistor sales have swung wildly, overshooting and undershooting end-use demand as equipment makers struggled to balance inventories in the midst of economic uncertainty since the 2008-2009 recession.

IC Insights believes the power transistor business is finally stabilizing and returning to more normal growth patterns in the 2014-2019 forecast period of the 2015 O-S-D Report.  Driven by steady increases in automotive, consumer electronics, portable systems, industrial, and wireless communications markets, power transistor sales are expected to rise by a compound annual growth rate (CAGR) of 5.3 percent between 2014 and 2019, when worldwide revenues are forecast to reach $17.1 billion (Figure 1).  Worldwide power transistor sales grew by a CAGR of 6.2 percent between 1994 and 2014.

For more than three decades, power transistors have been the growth engine in the commodity-filled discrete semiconductor market, which grew 11 percent in 2014 to a record-high $23.0 billion after falling 7 percent in 2012 and dropping 5 percent in 2013.  The new O-S-D Report shows power transistors accounted for 58 percent of total discretes sales in 2014 versus 51 percent in 2004 and 36 percent in 1994.  A number of power transistor technologies are needed to control, convert, and condition currents and voltages in an ever-expanding range of electronics—including battery-operated portable products, new energy-saving equipment, hybrid and electric vehicles,  “smart” electric-grid applications, and renewable power systems.

Despite the spread of system applications, power transistors have struggled to maintain steady sales growth since the 2009 semiconductor downturn, when revenues fell by 16 percent.  Power transistor sales sharply rebounded in the 2010 recovery year with a record-high 44 percent increase followed by 12 percent growth in 2011 to reach the current annual peak of $13.5 billion.  Power transistors then posted the first back-to-back annual sales declines in more than 30 years (-8 percent in 2012 and -6 percent in 2013) due to inventory corrections, price erosion, and delays in purchases by cautious equipment makers responding to economic uncertainty.   Power transistors ended the two-year losing streak in 2014 with sales and unit shipments both growing by 14 percent.

Figure 1

Figure 1

The 2015 O-S-D Report’s forecast shows power transistor sales returning to a more normal 6% increase in 2015 with power FET revenues growing 6 percent to $7.4 billion, insulated-gate bipolar transistor (IGBT) modules climbing 8 percent to $3.1 billion, IGBT transistors rising 6 percent to $1.1 billion, and bipolar junction transistors being up 4 percent to $893 million this year.

Fan-in WLP is experiencing continuous growth and attracting new applications, according to Yole Développement’s (Yole) latest report “Fan-in Wafer Level Packaging: Market & Technology Trends.” Indeed fan-in WLP technology confirms its presence on the semiconductor market with indisputable benefits linked to cost and form factor. Technology innovation continues and widens the sphere of possibilities of fan-in WLP solutions.
“Fan-in Wafer Level Packaging: Market & Technology Trends” report proposes a deep analysis of the fan-in WLP technology trends with a dedicated roadmap and an overview of latest technical innovations. Under this report, the “More than Moore” market research and strategy consulting company, Yole, also reviews the potential disruptions including new market drivers, infrastructure, expanding business models, new entries, competing packaging solutions, and analyzes the impact on the supply chain.

Although seemingly out of the spotlight, fan-in Wafer Level Packages (WLP) remain a highly important and constant presence with unmatchable advantages in cost and form factor. Fan-in WLP holds 16 percent of the total number of packages, while serving 4.4 percent of the wafer market at only 1.5 percent of the total semiconductor revenue.

“Fan-in WLP is forecasted to continue a stable growth, with a market of $5.3B in 2014 and a CAGR between 2014 and 2020 of 7 percent,” explained Andrej Ivankovic, Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at Yole. And he added: “The total wafer count in 300mm equivalent wafers is reaching 4 million with a projected CAGR of 8 percent while the unit number is found at 36 billion with a projected CAGR of 9 percent.”

Throughout the past few years, MEMS and CMOS image sensors have been increasing their share compared to analog, mixed signal and digital ICs and are now accounting for more than 50 percent of the total revenue.

The leading applications by wafer demand in the analog/mixed signal/digital domain are BT+WiFi+FM combos and RF transceivers followed by PMU, audio/video codecs, DC/DC converters, ESD/EMI IPD. MEMS devices are led by digital compasses, RF filters, accelerometers and gyroscopes. CMOS image sensors are strongly positioned in 2nd place by overall fan-in application rankings. In total 41 applications and their evolution are analyzed in more depth within Yole’s report. Yole’s data include breakdowns of MEMS, CMOS image sensors and analog, mixed signal and digital devices.

From a technology viewpoint, innovation continues in order to extend fan-in WLP capability, as summarized in Yole’s figure below.

fan in wlp fig 1

Click to view full size.

“Current bump pitch in high volume is mostly at 0.4mm with 0.35mm already present as well. Particular effort is being made to increase the die size and I/O count” says Santosh Kumar, Senior Technology & Market research analyst, Advanced Packaging and Semiconductor Manufacturing at Yole. Max I/O count in high volume is heading above 200 and announcements have been made for high volume production up to 800 I/Os. The die size sweet spot ranges up to 7mm x 7mm with 8mm x 8mm and 9mm x 9mm qualified and ready.

Yole’s technology & market analysis contains an in-depth analysis on the outlook for bump pitch, die size, I/O count, minimum line width/space, package thickness, RDL dielectric materials, who is developing which technology and the main challenges to be overcome for the evolution of fan-in technology. Fan-in WLP is still on track of technology innovation.

Related news:

Three trends driving optoelectronics market growth through 2019

Optoelectronics, sensors/actuators, and discretes growth accelerates

From connectivity to globalization and sustainability, the “Law” created by Gordon Moore’s prediction for the pace of semiconductor technology advances has set the stage for global technology innovation and contribution for 50 years. The exponential advances predicted by Moore’s Law have transformed the world we live in. The ongoing innovation, invention and investment in technology and the effects that arise from it are likely to enable continued advances along this same path in the future, according to a new report from IHS Inc. Titled “Celebrating the 50th Anniversary of Moore’s Law,” the report describes how the activity predicted by Moore’s Law not only drives technological change, but has also created huge economic value and driven social advancement.

In April of 1965, Fairchild Semiconductor’s Research and Development Director, Gordon Moore, who later founded Intel, penned an article that led with the observation that transistors would decrease in cost and increase in performance at an exponential rate. More specifically, Moore posited that the quantity of transistors that can be incorporated into a single chip would approximately double every 18 to 24 months. This seminal observation was later dubbed “Moore’s Law.”

“Fifty years ago today, Moore defined the trajectory of the semiconductor industry, with profound consequences that continue to touch every aspect of our day-to-day lives,” said Dale Ford, vice president and chief analyst for IHS Technology. “In fact, Moore’s Law forecast a period of explosive growth in innovation that has transformed life as we know it.”

The IHS Technology report, which is available as a free download, finds that an estimated $3 trillion of additional value has been added to the global gross domestic product (GDP), plus another $9 trillion of indirect value in the last 20 years, due to the pace of innovation predicted by Moore’s Law. The total value is more than the combined GDP of France, Germany, Italy and the United Kingdom.

If the cadence of Moore’s Law had slowed to every three years, rather than two years, technology would have only advanced to 1998 levels: smart phones would be nine years away, the commercial Internet in its infancy (five years old) and social media would not yet have skyrocketed.

“Moore’s Law has proven to be the most effective predictive tool of the last half-century of technological innovation, economic advancement, and by association, social and cultural change,” Ford said. “It has implications for connectivity and the way we interact, as evidenced by the way social relationships now span the globe. It also provides insight into globalization and economic growth, as technology continues to transform entire industries and economies. Finally it reveals the importance of how sustainability affects life on Earth, as we continue to transform our physical world in both positive and negative ways.”

Moores Law full

The Moore’s Law Era: Explosive Economic and Societal Change

The consequences of Moore’s Law has fueled multifactor productivity growth. The activity forecast by the law has contributed a full percentage point to real GDP growth, including both direct and indirect impact, every year between 1995 and 2011, representing 37 percent of global economic impact.

“Not even Gordon Moore himself predicted the blistering pace of change for the modern world,” Ford said. “While it is true most people have never seen a microprocessor, every day we benefit from experiences that are all made possible by the exponential growth in technologies that underpin modern life.”

According to the “Moore’s Law Impact Report,” the repercussions of Moore’s Law have contributed to an improved quality of life, because of the advances made possible in healthcare, sustainability and other industries. The results of advanced digital technology include the following:

  • Forty percent of the world’s households now have high-speed connections, compared to less than 0.1 percent in 1991
  • Up to 150 billion incremental barrels of oil could potentially be extracted from discovered global oil fields
  • Researchers can perform 1.5 million high-speed screening tests per week (up from 180 in 1997), allowing for the development of new material, such as bio-fuels and feedstock’s for plant-based chemicals

Moore’s Law: Reflecting the Pace of Change

Moore’s Law is not a law but an unspoken agreement between the electronics industry and the world economy that inspires engineers, inventors and entrepreneurs to think about what may be possible.

“Whatever has been done, can be outdone,” said Gordon Moore. “The industry has been phenomenally creative in continuing to increase the complexity of chips. It’s hard to believe – at least it’s hard for me to believe – that now we talk in terms of billions of transistors on a chip rather than tens, hundreds or thousands.”

Moore’s observation has transformed computing from a rare, expensive capability into an affordable, pervasive and powerful force – the foundation for Internet, social media, modern data analytics and more. “Moore’s Law has helped inspire invention, giving the world more powerful computers and devices that enable us to connect to each other, to be creative, to be productive, to learn and stay informed, to manage health and finances, and to be entertained,” Ford said.

Millennials: The Stewards of Moore’s Law

From the changing shape and feel of how humans communicate to the delivery of healthcare, changing modes of transportation, cities of the future, harvesting energy resources, classroom learning and more – technology innovations that spring from Moore’s Law likely will remain a foundational force for growth into the next decade.

From data sharing, self-driving cars and drones to smart cities, smart homes and smart agriculture, Moore’s Law will enable people to continuously shrink technology and make it more power efficient, allowing creators, engineers and makers to rethink where – and in what situations – computing is possible and desirable.

Computing may disappear into the objects and spaces that we interact with – even the fabric of our clothes or ingestible tracking devices in our bodies. New devices may be created with powerful, inexpensive technology and combining this with the ability to pool and share more information, new experiences become possible.

Since the global economic recession of 2008-2009, the IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers.  From 2009-2014, semiconductor manufacturers have closed or repurposed 83 wafer fabs, according to data compiled, updated, and now available in IC Insights’ Global Wafer Capacity 2015-2019 report.

Figure 1 shows that 41 percent of fab closures since 2009 have been 150mm fabs and 27 percent have been 200mm wafer fabs.  Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.  More recently, ProMOS and Powerchip closed their respective 300mm wafer fabs in 2013.

IC fabs Fig 1

 

Semiconductor suppliers in Japan have closed 34 wafer fabs since 2009, more than any other country/region over the past six years.   In the 2009-2014 timeframe, 25 fabs were closed in North America and 17 were shuttered in Europe (Figure 2).

IC fabs Fig 2

 

Worldwide fab closures surged in 2009 and 2010 partly as a result of the severe economic recession at the end of the previous decade.  A total of 25 fabs were closed in 2009, followed by 24 being shut down in 2010.  Ten fabs closed in 2012 and 12 were removed from service in 2013.  Six fabs were closed in both 2011 and in 2014, the fewest number of closures per year during the 2009-2014 time span.

Given the flurry of merger and acquisition activity seen in the semiconductor industry recently, the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects the number of fab closures to accelerate in the coming years—a prediction that will likely please foundry suppliers but make semiconductor equipment and material suppliers a little bit nervous.