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Texas Instruments was again the leading supplier of analog devices in 2014 with $8.1 billion in sales, and increased its analog marketshare to 18 percent, according to rankings of top suppliers of major IC product categories found in IC Insights’ April Update to The McClean Report 2015.  The top 10 analog IC suppliers accounted for 57 percent of total analog sales in 2014, up slightly from 56 percent in 2013.  Among the top suppliers, six companies on the list had sales in excess of $2.0 billion and three others exceeded $1.0 billion in analog sales last year. (Renesas again fell short of the $1.0 billion mark.) Among the top suppliers, Skyworks Solutions (42 percent), NXP (21 percent), and Texas Instruments (13 percent) showed the strongest growth and outperformed the total analog market (9 percent) by the widest margins.

Figure 1

Figure 1

TI’s analog sales represented 62 percent of its total corporate revenue in 2014.  Since the 1990s, TI has focused on increasing its presence in the analog market.  In 2009, TI purchased 300mm manufacturing tools from defunct Qimonda and put them to use to build analog ICs, becoming the first company to manufacture analog devices on 300mm equipment.  In 2010, TI acquired two wafer fabs operated by Spansion in Aizu-Wakamatsu, Japan, and it acquired a fully equipped 200mm fab in China from Cension Semiconductor Manufacturing in Chengdu.  Both facilities were immediately put to use making analog ICs.  In April 2011, TI acquired National Semiconductor—its rival in many analog markets—for $6.5 billion.

TI is boosting its analog position by transferring more manufacturing to 300mm wafers in its newer RFAB and its older DMOS 6 fab.  TI says the 300mm fabs will together help reduce its total production costs by up to 40 percent, increase its available manufacturing capacity substantially, and give it added flexibility to respond to customer demands.

TI’s 2014 analog revenue was nearly 3x larger than second place ST, whose sales grew 2 percent in 2014. ST accounted for 6 percent marketshare. ST attributed its lower analog sales to softer equipment sales (computer, consumer, automotive, industrial) among its primary customers.  Third-ranked Infineon and seventh-ranked NXP were two other European-headquartered companies ranked among the top 10 analog suppliers in 2014.  Collectively, these three European suppliers accounted for 16 percent analog marketshare last year.

Skyworks enjoyed a stellar year in which its analog sales increased 42 percent mostly due to strong worldwide smartphone sales. Skyworks Solutions makes analog and mixed signal semiconductors for Apple, Samsung, and other suppliers of mobile devices.  Multiple power amplifier components from Skyworks are found in Apple’s iPhone 6 models.  It has been estimated that Skyworks supplies $4 worth of content from every new iPhone 6 handset.

While Skyworks is heavily focused in mobile, CEO David Aldrich has said the company’s technology is “a conduit into the Internet of Things.”  In 2015, the company said it would look to the automotive, home, and wearable markets to expand its presence in applications linked to the Internet of Things.

Analog ICs like audio amplifiers, op amps, are analog switches are key components and building blocks for creating innovative wearable applications.  Skyworks’ wireless technology is used in some General Electric healthcare equipment, and the company recently sealed a deal to supply high-performance filter solutions to Panasonic devices.

Analog Devices purchased smaller rival Hittite Microwave in mid-2014, a company that specialized in devices for RF and signal-conversion applications.  ADI’s analog sales grew 9% last year.  ADI is expected to provide devices that enable the 3D/Force Touch feature—currently available on the Apple Watch—to the iPhone 6s that is due out in the second half of 2015 and new generations of the iPad. The Force Touch feature uses tiny electrodes to distinguish between a light tap and a deep press to trigger contextually specific controls.

Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

BY BILL CHEN, ASE US, Sunnyvale, CA; BILL BOTTOMS, 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG, Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI, Toshiba Kangawa, Japan.

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that in the aggregate provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub‐system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level cost-of-ownership.

The mission of the ITRS Heterogeneous Integration Focus Team is to provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the require- ments for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

Background

The environment is rapidly changing and will require revolutionary changes after 50 years where the change was largely evolutionary. The major factors driving the need for change are:

  • We are approaching the end of Moore’s Law scaling.
  • The emergence of 2.5D and 3D integration techniques
  • The emerging world of Internet of Everything will cause explosive growth in the need for connectivity.
  • Mobile devices such as smartphones and tablets are growing rapidly in number and in data communications requirements, driving explosive growth in capacity of the global communications network.
  • Migration of data, logic and applications to the cloud drives demand for reduction in latency while accommodating this network capacity growth.

Satisfying these emerging demands cannot be accomplished with the current electronics technology and these demands are driving a new and different integration approach. The requirements for power, latency, bandwidth/bandwidth density and cost can only be accomplished by a revolutionary change in the global communications network, with all the components in that network and everything attached to it. Ensuring the reliability of this “future network” in an environment where transistors wear out, will also require innovation in how we design and test the network and its components.

The transistors ‘power consumption in today’s network account for less than 10 percent of total power, total latency and total cost. It is the interconnection of these transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, where the future limitations in performance, power, latency and cost reside. Overcoming these limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.

Difficult challenges

The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS. Packaging and test have found it difficult to scale their performance or cost per function to keep pace with transistors and many difficult challenges must be met to maintain the historical pace of progress.

In order to identify the difficult challenges we have selected seven application areas that will drive critical future requirements to focus our work. These areas are:

  • Mobile products
  • Big data systems and interconnect
  • The cloud
  • Biomedical products
  • Green technology
  • Internet of Things
  • Automotive components and systems

An initial list of difficult challenges for Heterogeneous Integration for these application areas is presented in three categories; (1) on‐chip interconnect, (2) assembly and packaging and (3) test. These are analyzed in line with the roadmapping process and will be used to define the top 10 challenges that have the potential to be “show stoppers” for the seven application areas identified above.

On-chip interconnect difficult challenges

The continued decrease in feature size, increase in transistor count and expansion into 3D structures are presenting many difficult challenges. While challenges in continuous scaling are discussed in the “More Moore” section, the difficult challenges of interconnect technology in devices with 3D structures are listed here. Note that this assumes a 3D structure with TSV, optical interconnects and passive devices in interposer substrates.

ESD (Electrostatic Discharge): Plasma damage on transistors by TSV etching especially on via last scheme. Low damage TSV etch process and the layout of protection diodes are the key factors.

CPI (Chip Package Interaction) Reliability [Process]: Low fracture toughness of ULK (Ultra Low‐k) dielectrics cause failures such as delamination. Material development of ULK with higher modulus and hardness are the key factors.

CPI (Chip Package Interaction) Reliability [Design]: A layout optimization is a key for the device using Cu/ULK structure.

Stress management in TSV [Via Last]: Yield and reliability in Mx layers where TSV land is a concern.

Stress management in TSV [Via Middle]: Stress deformation by copper extrusion in TSV and a KOZ (Keep Out Zone) in transistor layout are the issues.

Thermal management [Hot Spot]: Heat dissipation in TSV is an issue. An effective homogenization of hot spot heat either by material or layout optimization are the key factors.

Thermal management [Warpage]: Thermal expansion management of each interconnect layer is necessary in thinner Si substrate with TSV.

Passive Device Integration [Performance]: Higher Q, in other words, thicker metal lines and lower tan dielectrics is a key for achieving lower power and lower noise circuits.

Passive Device Integration [Cost]: Higher film and higher are required for higher density and lower footprint layout.

Implementation of Optical Interconnects: Optical interconnects for signaling, clock distribution, and I/O requires development of a number of optical components such as light sources, photo detectors, modulators, filters and waveguides. On‐chip optical interconnects replacing global inter- connects requires the breakthrough to overcome the cost issue.

Assembly and packaging difficult challenges

Today assembly and packaging are often the limiting factors in performance, size, latency, power and cost. Although much progress has been made with the introduction of new packaging architectures and processes, with innovations in wafer level packaging and system in package for example, a significantly higher rate of progress is required. The complexity of the challenge is increasing due to unique demands of heterogeneous integration. This includes integration of diverse materials and diverse circuit fabric types into a single SiP architecture and the use of the 3rd dimension.

Difficult packaging challenges by circuit fabric

  • Logic: Unpredictable hot spot locations, high thermal density, high frequency, unpredictable work load, limited by data bandwidth and data bottle‐necks. High bandwidth data access will require new solutions to physical density of bandwidth.
  • Memory: Thermal density depends on memory type and thermal density differences drive changes in package architecture and materials, thinned device fault models, test & redundancy repair techniques. Packaging must support low latency, high bandwidth large (>1Tb) memory in a hierar- chical architecture in a single package and/or SiP).
  • MEMS: There is a virtually unlimited set of requirements. Issues to be addressed include hermetic vs. non‐hermetic, variable functional density, plumbing, stress control, and cost effective test solutions.
  • Photonics: Extreme sensitivity to thermal changes, O to E and E to O, optical signal connections, new materials, new assembly techniques, new alignment and test techniques.
  • Plasmonics: Requirements are yet to be determined, but they will be different from other circuit type. Issues to be addressed include acousto‐ magneto effects and nonlinear plasmonics.
  • Microfluidics: Sealing, thermal management and flow control must be incorporated into the package.

Most if not all of these will require new materials and new equipment for assembly and test to meet the 15 year Roadmap requirements.

Difficult packaging challenges by material

Semiconductors: Today the vast majority of semiconductor components are silicon based. In the future both organic and compound semiconductors will be used with a variety of thermal, mechanical and electrical properties; each with unique mechanical, thermal and electrical requirements.

Conductors: Cu has replaced Au and Al in many applications but this is not good enough for future needs. Metal matrix composites and ballistic conductors will be required. Inserting some of these new materials will require new assembly, contacting and joining techniques.

Dielectrics: New high k dielectrics and low k dielectrics will be required. Fracture toughness and interfacial adhesion will be the key parameters. Packaging must provide protection for these fragile materials.

Molding compound: Improved thermal conductivity, thinner layers and lower CTE are key requirements.

Adhesives: Die attach materials, flexible conductors, residue free materials needed o not exist today.

Biocompatible materials: For applications in the healthcare and medical domain (e.g. body patches, implants, smart catheters, electroceuticals), semiconductor‐based devices have to be biocompatible. This involves the integration of new (flexible) materials to comply with specific packaging (form factor) requirements.

Difficult challenges for the testing of heterogeneous devices

The difficulties in testing heterogeneous devices can be broadly separated into three categories: Test Quality Assurance, Test Infrastructure, and Test Design Collaboration.

Test quality assurance needs to comprehend and place achievable quality and reliability metrics for each individual component prior to integration, in order to meet the heterogeneous system quality and reliability targets. Assembly and test flows will become inter- twined and interdependent. They need to be constructed in a manner that maintains a cost effective yield loss versus component cost balance and proper component fault isolation and quantification. The industry will be required to integrate components that cannot guarantee KGD without insurmountable cost penalties and this will require integrator visible and accessible repair mechanisms.

Test infrastructure hardware needs to comprehend multiple configurations of the same device to enable test point insertion at partially assembled and fully assembled states. This includes but is not limited to different component heights, asymmetric component locations, and exposed metal contacts (including ESD challenges). Test infrastructure software needs to enable storing and using volume test data for multiple components that may or may not have been generated within the final integrators data domains but are critical for the final heterogeneous system functionality and quality. It also needs to enable methods for highly granular component tracking for subsequent joint supplier and integrator failure analysis and debug.

Test design collaboration is one of the biggest challenges that the industry will need to overcome. It will be a requirement for heterogeneous highly integrated highly functional systems to have test features co‐designed across component boundaries that have more test coverage and debug capability than simple boundary scans. The challenge
of breaking up what was once the responsibility of a wholly contained design for test team across multiple independent entities each trying to protect IP, is only magnified by the additional requirement that the jointly developed test solutions will need to be standardized across multiple competing heterogeneous integrators. Industry wide collaboration on and adherence to test standards will be required in order to maintain cost and time effective design cycles for highly desired components that traditionally has only been required for cross component boundary communication protocols.

The roadmapping process

The objective of ITRS 2.0 for heterogeneous integration is to focus on a limited number of key challenges (10) that have the greatest potential to be “show stoppers,” while leaving other challenges identified and listed but without focus on detailed technical challenges and potential solutions. In this process collaboration with other Focus Teams and Technical Working Groups will be a critical resource. While we will need collaboration with other groups both inside and outside the ITRS some of the collaborations are critical for HI to address its mission. FIGURE 1 shows the major internal collaborations in three categories.

FIGURE 1. Collaboration priorities.

FIGURE 1. Collaboration priorities.

We expect to review these key challenges and our list of other challenges on a yearly basis and make changes so that our focus keeps up with changes in the key challenges. This will ensure that our efforts remain focused on the pre‐competitive technologies that have the greatest future value to our audience. There are four phases in the process detailed below.

1. Identify challenges for application areas: The process would involve collaboration with other focus teams, technical TWGs and other roadmapping groups casting a wide net to identify all gaps and challenges associated with the seven selected application areas as modified from time to time. This list of challenges will be large (perhaps hundreds) and they will be scored by the HI team by difficulty and criticality.

2. Define potential solutions: Using the scoring in phase (1) a number (30‐40) will be selected to identify potential solutions. The remainder will be archived for the next cycle of this process. This work will be coordinated with the same collabo- ration process defined above. These potential solutions will be scored by probable success and cost.

3. Down select to only the 10 most critical challenges: The potential solutions with the lowest probability of success and highest cost will have the potential to be “show stopping” roadblocks. These will be selected using the scoring above and the focus issues for the HI roadmap. The results of this selection process will be commu- nicated to the relevant collaboration partners for their comments.

4. Develop a roadmap of potential solutions for “show stoppers”: The roadmap developed for the “show stopping” roadblocks shall include analysis of the blocking issue and identification of a number of potential solutions. The collaboration shall include detail work with other units of the ITRS, other roadmapping activity such as the Jisso Roadmap, iNEMI Roadmap, Communications Technology Roadmap from MIT. We are continuing to work with the global technical community: industry, research institutes and academia, including the IEEE CPMT Society.

The blocking issues will be specifically investigated by the leading experts within the ITRS structure, academia, industry, government and research organizations to ensure a broad based understanding. Potential solutions will be identified through a similar collaboration process and evaluated through a series of focused workshops similar to the process used by the ERD iTWG. This process is a workshop where there is one proponents and one critic presenting to the group. This is followed by a discussion and a voting process which may have several iterations to reach a consensus.

The cross Focus Team/TWG collaboration will use a procedure of iteration to converge on an understanding of the challenges and potential solutions that is self‐ consistent across the ITRS structure. An example is illustrated in FIGURE 2.

FIGURE 2. Iterative collaboration process

FIGURE 2. Iterative collaboration process

It is critically important that our time horizon include the full 15 years of the ITRS. The work to anticipate the true roadblocks for heterogeneous integration, define potential solutions and implement a successful solution may require the full 15 years. Among the tables we will include 5 year check points of the major challenges for the key issues of cost, power, latency and bandwidth. In order for this table to be useful we will face the challenge of identifying the specific metric or metrics to be used for each application driver as we prepare the Heterogeneous Integration roadmap chapter for 2015 and beyond.

BILL CHEN is a senior technical advisor for ASE US, Sunnyvale, CA; BILL BOTTOMS is President and CEO of 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG is director of business development at Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI works in the Toshiba’s Center for Semiconductor Research & Development, Kangawa, Japan.

IHS Technology’s final market share results for 2014 reveal that worldwide semiconductor revenues grew by 9.2 percent in 2014 coming in just slightly below the growth projection of 9.4 percent based on preliminary market share data IHS published in December 2014. The year ended on a strong note with the fourth quarter showing 9.7 percent year-over-year growth.  IHS semiconductor market tracking and forecasts mark the fourth quarter of 2014 as the peak of the annualized growth cycle for the semiconductor industry.

Global revenue in 2014 totaled $354.5 billion, up from $324.7 billion in 2013, according to a final annual semiconductor market shares published by IHS Technology). The nearly double-digit percentage increase follows solid growth of 6.6 percent in 2013, a decline of 2.6 percent in 2012 and a marginal increase of 1.3 percent in 2011. The performance in 2014 represents the highest rate of annual growth since the 33 percent boom of 2010.

“While 2014 marked a peak year for semiconductor revenue growth, the health of both the semiconductor supply base and end-market demand, position the industry for another year of strong growth in 2015,” said Dale Ford, vice president and chief analyst at IHS Technology. “Overall semiconductor revenue growth will exceed 5 percent in 2015, and many component categories and markets will see improved growth over 2014.  The more moderate 2015 growth is due primarily to more modest increases in the memory and microcomponent categories.  The dominant share of semiconductor markets will continue to see vibrant growth in 2015.”

More information on this topic can be found in the latest release of the Competitive Landscaping Tool from the Semiconductors & Components service at IHS.

Top ten maneuvers

Intel maintained its strong position as the largest semiconductor supplier in the world followed by Samsung Electronics and Qualcomm at a strong number two and three position in the rankings.  On the strength of its acquisition of MStar, MediaTek jumped into the top 10 replacing Renesas Electronics at number 10.  The other big mover among the top 20, Avago Technologies, also was boosted by an acquisition, moving up nine places to number 14 with its acquisition of LSI in 2014.

Strategic acquisitions continue to play a major role in shaping both the overall semiconductor market rankings and establishing strong leaders in key semiconductor segments.  NXP and Infineon will be competing for positions among the top 10 semiconductor suppliers in 2015 with the boost from their mergers/acquisitions of Freescale Semiconductor and International Rectifier, respectively.

Among the top 25 semiconductor suppliers, 21 companies achieved growth in 2014.  Out of the four companies suffering declines, three are headquartered in Japan as the Japanese semiconductor market and suppliers continue to struggle.

Broad-based growth

As noted in the preliminary market share results, 2014 was one of the healthiest years in many years for the semiconductor industry.  Five of the seven major component segments achieved improved growth compared to 2013 growth. All of the major component markets saw positive growth in 2014.  Out of 128 categories and subcategories tracked by IHS, 73 percent achieved growth in 2014.  The combined total of the categories that did not grow in 2014 accounted for only 8.1 percent of the total semiconductor market.

Out of more than 300 companies included in IHS semiconductor research, nearly 64 percent achieved positive revenue growth in 2014.  The total combined revenues of all companies experiencing revenue declines accounted for only roughly 15 percent of total semiconductor revenues in 2014.

Semiconductor strength

Memory still delivered a strong performance driven by continued strength in DRAM ICs. However, memory market growth declined by a little more than 10 percent compared to the boom year of 2013 with over 28 percent growth in that year.  Growth in sensors & actuators came in only slightly lower than 2013.

Microcomponents achieved the strongest turn around in growth moving from a -1.6 percent decline in 2013 to 8.9 percent growth in 2014.  It also delivered the best growth among the major segments following memory ICs.  Even Digital Signal Processors (DSPs) achieved positive growth in 2014 following strong, double-digit declines in six of the last seven years.  MPUs lead the category with 10.7 percent growth followed by MCUs with 5.4 percent growth.

Every application market delivered strong growth in 2014 with the exception of Consumer Electronics.  Industrial Electronics lead all segments with 17.8 percent growth.  Data Processing accomplished the strongest improvement in growth as it grew 13.7 percent, up nearly 10 percent from 2014.  Of course, MPUs and DRAM played a key role in the strength of semiconductor growth in Data Processing.  The third-strongest segment was Automotive Electronics which was the third segment with double-digit growth at 10 percent.  Only Wireless Communications saw weaker growth in 2014 compared to 2013 as its growth fell by roughly half its 2013 level to 7.8 percent in 2014.

IC Insights will release its April Update to the 2015 McClean Report later this month. The Update includes the final 2014 company sales rankings for the top 50 semiconductor and top 50 IC companies, and the leading IC foundries. Also included are 2014 IC company sales rankings for various IC product segments (e.g., DRAM, MPU, etc.).

In 2014, there were only two Japanese companies—Toshiba and Renesas—that were among the top 10 semiconductor suppliers (Figure 1). Assuming the NXP/Freescale merger is completed later this year, IC Insights forecasts that Toshiba will be the lone Japanese company left in the top 10 ranking. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor sales presence in the global market.

Fig 1

Fig 1

Figure 1 traces the top 10 semiconductor companies dating back to 1990, when Japanese semiconductor manufacturers wielded their greatest influence on the global stage and held six of the top 10 positions.  The six Japanese companies that were counted among the top 10 semiconductor suppliers in 1990 is a number that has not been matched by any country or region since (although the U.S. had five suppliers in the top 10 in 2014). The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, fell to three companies in 2000 and 2006, and then to only two companies in 2014.

Figure 1 also shows that, in total, the top 10 semiconductor sales leaders are making a marketshare comeback. After reaching a marketshare low of 45 percent in 2006, the top 10 semiconductor sales leaders held a 53 percent share of the total semiconductor market in 2014.  Although the top 10 share in 2014 was eight points higher than in 2006, it was still six points below the 59 percent share they held in 1990.  As fewer suppliers are able to achieve the economies of scale needed to successfully invest and compete in the semiconductor industry, it is expected that the top 10 share of the worldwide semiconductor market will continue to slowly increase over the next few years.

April 2015 marks the 50th anniversary of one of the business world’’s most profound drivers, now commonly referred to as Moore’s Law.  In April 1965, Gordon Moore, later co-founder of Intel, observed that the number of transistors per square inch on integrated circuits would continue to double every year.  This “observation” has set the exponential tempo for five decades of innovation and investment resulting in today’s $336 billion USD integrated circuits industry enabled by the $82 billion USD semiconductor equipment and materials industry (SEMI and SIA 2014 annual totals).

SEMI, the global industry association serving the nano- and micro-electronic manufacturing supply chains, today recognizes the enabling contributions made by the over 1,900 SEMI Member companies in developing semiconductor equipment and materials that produce over 219 billion integrated circuit devices and 766 billion semiconductor units per year (WSTS, 2014).

50 years of Moore’’s Law has led to one of the most technically sophisticated, constantly evolving manufacturing industries operating today.  Every day, integrated circuit (IC) production now does what was unthinkable 50 years ago.  SEMI Member companies now routinely produce materials such as process gases, for example, to levels of 99.994 percent quality for bulk Silane (SiH4) in compliance with the SEMI C3.55 Standard.  Semiconductor equipment manufacturers develop the hundreds of processing machines necessary for each IC factory (fab) that are at work all day, every day, processing more than 100 silicon wafers per hour with fully automated delivery and control – all with standardized interoperability. SEMI Member companies provide the equipment to inspect wafer process results automatically, and find and identify defects at sizes only fractions of the 14nm circuit line elements in today’s chips, ensuring process integrity throughout the manufacturing process.

“”It was SEMI Member companies who enabled Moore’’s Law’’s incredible exponential growth over the last 50 years,”” said Denny McGuirk, president and CEO of SEMI.  “”Whereas hundreds of transistors on an IC was noteworthy in the 1960s, today over 1.3 billion transistors are on a single IC.  SEMI Member companies provide the capital equipment and materials for today’s mega-fabs, with each one processing hundreds or thousands of ICs on each wafer with more than 100,000 wafers processed per month.””

To celebrate SEMI Member companies’ contribution to the 50 years of Moore’s Law, SEMI has produced a series of Infographics that show the progression of the industry.

1971

2015

Price per chip

$351

$393

Price per 1,000 transistors

$150

$0.0003

Number of transistors per chip

2,300

1,300,000,000

Minimum feature size on chip

10,000nm

14nm

From SEMI infographic “Why Moore Matters”: www.semi.org/node/55026

Consider these eight issues where the packaging team should be closely involved with the circuit design team.

BY JOHN T. MACKAY, Semi-Pac, Inc., Sunnyvale, CA

Today’s integrated circuit designs are driven by size, performance, cost, reliability, and time- to-market. In order to optimize these design drivers, the requirements of the entire system should be considered at the beginning of the design cycle—from the end system product down to the chips and their packages. Failure to include packaging in this holistic view can result in missing market windows or getting to market with a product that is more costly and problematic to build than an optimized product.

Chip design

As a starting consideration, chip packaging strategies should be developed prior to chip design completion. System timing budgets, power management, and thermal behavior can be defined at the beginning of the design cycle, eliminating the sometimes impossible constraints that are given to the package engineering team at the end of the design. In many instances chip designs end up being unnecessarily difficult to manufacture, have higher than necessary assembly costs and have reduced manufacturing yields because the chip design team used minimum design rules when looser rules could have been used.

Examples of these are using minimum pad-to-pad spacing when the pads could have been spread out or using unnecessary minimum metal to pad clearance (FIGURE 1). These hard taught lessons are well understood by the large chip manufacturers, yet often resurface with newer companies and design teams that have not experienced these lessons. Using design rule minimums puts unnecessary pressure on the manufacturing process resulting in lower overall manufacturing yields.

Packaging 1

FIGURE 1. In this image, the bonding pads are grouped in tight clusters rather than evenly distributed across the edge of the chip. This makes it harder to bond to the pads and requires more-precise equipment to do the bonding, thus unnecessarily increasing the assembly cost and potentially impacting device reliability.

Packaging

Semiconductor packaging has often been seen as a necessary evil, with most chip designers relying on existing packages rather than package customization for optimal performance. Wafer level and chipscale packaging methods have further perpetuated the belief that the package is less important and can be eliminated, saving cost and improving performance. The real fact is that the semiconductor package provides six essential functions: power in, heat out, signal I/O, environmental protection, fan-out/compatibility to surface mounting (SMD), and managing reliability. These functions do not disappear with the implementation of chipscale packaging, they only transfer over to the printed circuit board (PCB) designer. Passing the buck does not solve the problem since the PCB designers and their tools are not usually expected to provide optimal consideration to the essential semiconductor die requirements.

Packages

Packaging technology has considerably evolved over the past 40 years. The evolution has kept pace with Moore’s Law increasing density while at the same time reducing cost and size. Hermetic pin grid arrays (PGAs) and side-brazed packages have mostly been replaced by the lead-frame-based plastic quad flat packs (QFP). Following those developments, laminate based ball grid arrays (BGA), quad flat pack no leads (QFN), chip scale and flip-chip direct attach became the dominate choice for packages.

The next generation of packages will employ through-silicon vias to allow 3D packaging with chip-on-chip or chip-on-interposer stacking. Such approaches promise to solve many of the packaging problems and usher in a new era. The reality is that each package type has its benefits and drawbacks and no package type ever seems to be completely extinct. The designer needs to have an in-depth understand of all of the packaging options to determine how each die design might benefit or suffer drawbacks from the use of any particular package type. If the designer does not have this expertise, it is wise to call in a packaging team that possesses this expertise.

Miniaturization

The push to put more and more electronics into a smaller space can inadvertently lead to unnec- essary packaging complications. The ever increasing push to produce thinner packages is a compromise against reliability and manufacturability. Putting unpackaged die on the board definitely saves space and can produce thinner assemblies such as smart card applications. This chip-on-board (COB) approach often has problems since the die are difficult to bond because of their tight proximity to other components or have unnecessarily long bond wires or wires at acute angles that can cause shorts as PCB designers attempt to accommodate both board manufacturing line and space realities with wire bond requirements.

Additionally, the use of minimum PCB design rules can complicate the assembly process since the PCB etch-process variations must be accommodated. Picking the right PCB manufacturer is important too as laminate substrate manufacturers and standard PCB shops are most often seen as equals by many users. Often, designers will use material selections and metal systems that were designed for surface mounting but turn out to be difficult to wire bond. Picking a supplier that makes the right metallization tradeoffs and process disciplines is important in order to maximize manufacturing yields

Power

Power distribution, including decoupling capaci- tance and copper ground and power planes have been mostly a job for the PCB designer. This is a wonder to most users as to why decoupling is rarely embedded into the package as a complete unit. Cost or package size limitations are typically the reasons cited as to why this isn’t done. The reality is that semiconductor component suppliers usually don’t know the system requirements, power fluctuation tolerance and switching noise mitigation in any particular installation. Therefore power management is left to the system designer at the board level.

Thermal Management

Miniaturization results in less volume and heat spreading to dissipate heat. Often, there is no room or project funds available for heat sinks. Managing junction temperature has always been the job of the packaging engineer who must balance operating and ambient temperatures and packaging heat flow.

Once again, it is important to develop a thermal strategy early in the design cycle that includes die specifics, die attachment material specification, heat spreading die attachment pad, thermal balls on BGA and direct thermal pad attachment during surface mount.

Signal input/output

Managing signal integrity has always been the primary concern of the packaging engineer. Minimizing parasitics, crosstalk, impedance mismatch, transmission line effects and signal atten- uation are all challenges that must be addressed. The package must handle the input/output signal requirements at the desired operating frequencies without a significant decrease in signal integrity. All packages have signal characteristics specific to the materials and package designs.

Performance

There are a number of factors that impact perfor- mance including: on-chip drivers, impedance matching, crosstalk, power supply shielding, noise and PCB materials to name a few. The performance goals must be defined at the beginning of the design cycle and tradeoffs made throughout the design process.

Environmental protection

The designer must also be aware that packaging choices have an impact on protecting the die from environmental contamination and/or damage. Next- generation chip-scale packaging (CSP) and flip chip technologies can expose the die to contami- nation. While the fab, packaging and manufacturing engineers are responsible for coming up with solutions that protect the die, the design engineer needs to understand the impact that these packaging technologies have on manufacturing yields and long-term reliability.

Involve your packaging team

Hopefully, these points have provided some insights on how packaging impacts many aspects of design and should not be relegated to just picking the right package at the end of the chip design. It is important that your packaging team be involved in the design process from initial specification through the final design review.

In today’s fast moving markets, market windows are shrinking so time to market is often the important differentiator between success and failure. Not involving your packaging team early in the design cycle can result in costly rework cycles at the end of the project, having manufacturing issues that delay the product introduction or, even worse, having impossible problems to solve that could have been eliminated had packaging been considered at the beginning of the design cycle.

System design incorporates many different design disciplines. Most designers are proficient in their domain specialty and not all domains. An important byproduct of these cross-functional teams is the spreading of design knowledge throughout the teams, resulting in more robust and cost effective designs.

Packages are changing. Acoustic methods provide a way to image and analyze them.

BY TOM ADAMS, SONOSCAN, INC., Elk Grove Village, IL

By the year 2020, the design, dimensions and materials of various electronic component packages will have changed in varying degrees from their current forms. PEMs (plastic-encap-sulated microcircuits) will still be in production, but likely with shrinking sizes and better (or less expensive) encapsulants. Stacking of die connected by non-wire methods such as through-silicon vias (TSVs) will be in production. These and other package types, along with components such as ceramic chip capacitors, will need to be inspected for internal anomalies, typically by non-destructive acoustic micro imaging. This article takes a forward look at some of the challenges and changes that may take place in various packages and the possible advances in acoustic methods for imaging and analyzing them.

In electronic components, the business of acoustic micro imaging is to make visible and and analyze internal structural features. Acoustic micro imaging tools such as Sonoscan’s C-SAM series are used to image anomalies and defects, or to verify their absence. The defects are typically gaps – delaminations, voids, cracks, non-bonds and the like – but an acoustic micro imaging tool will also reveal surprises such as the out-of-place or missing die sometimes noted in counterfeit components.

New acoustic imaging methods

Today, the prevalent imaging mode for acoustic micro imaging tools is what is commonly called the Time Domain Amplitude Mode. The scanning transducer sends a pulse of VHF (5 to 100 MHz) or UHF (above 100 MHz) ultrasound into an x-y location. A few micro-seconds later, the transducer receives a number of echoes from the depth of interest. The amplitude of the highest-amplitude echo within a gate (time window) is used to assign a pixel value to that x-y location. The other echoes are ignored.

At the moment, there are about a dozen other imaging modes which collect data in different ways and which yield different information and images about a sample. One example: it is important in imaging IGBT modules to measure and map the thickness of the solder bonding the heat sink to the ceramic raft above. Irregular solder thickness often means that the raft is tilted or warped (and thus may restrict heat dissipation). The Time Difference mode will map the interface. This mode ignores echo amplitude altogether and uses the arrival time of the echoes to measure and map the thickness of the solder. Irregular solder thickness means that the raft is tilted or warped (and thus may restrict heat dissipation). Other acoustic imaging modes use other techniques to detect thickness variations.

The Frequency Domain mode produces multiple images of the target depth in a sample. Each image is made using echoes within a very narrow frequency range (e.g., 102.0-103.5 MHz). This mode is useful in samples having subtle anomalies or defects that may be hard to discern with, say, Amplitude Mode.

A new mode is typically developed when the user of an acoustic micro imaging tool expresses the need to push acoustic imaging beyond its current capabilities in order to solve a specific inspection problem. In some instances an existing mode that was previously developed for research purposes is found to be useful for emerging sample types. It is very likely that new acoustic imaging modes will developed as electronic components and assemblies continue to evolve.

A recently developed mode is the Echo Integral Mode. It gives a view similar to, but more informative than, the Amplitude Mode. While Amplitude Mode picks the highest single amplitude to assign a pixel value, The Echo Integral Mode uses the sum of the amplitude of all the echoes at a given x-y coordinate to determine the pixel color for that coordinate. This approach makes it easier to see subtle local differences in, say, the quality of a bond between two materials.

FIGURE 1 is the Thru-Scan mode image of a plastic BGA package. Thru-Scan pulses ultrasound into the top of the package and uses a sensor beneath the package to read the amplitude of the arriving ultrasound at each x-y location. Gap-type defects block ultrasound and thus appear in a Thru-Scan image as black acoustic shadows.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

In Figure 1, the black features within the die at center are surely significant anomalies, but an engineer cannot tell from this Thru-Scan image what depth they lie at: are they in the die attach material or in the substrate below?

At left in FIGURE 2 is the Amplitude Mode image of the die area. This image is gated on (reads echoes only from) the die attach depth, and ignores echoes from other depths. The black dots are not features in the gated depth, but are the acoustic shadows of voids in the mold compound above the die. The die area itself is rather uniformly pale gray, with no features of note. The image at right used the Echo Integral Mode, also gated on the die attach material. Using the average amplitude of all the echoes at of millions of x-y coordinates gave a different result: there are significant differences in brightness. The large bright area marked by arrows is a gap-type defect in the die attach, and there are other, smaller defects of the same type. The defects imaged as black shadows by Thru-Scan are imaged here as near-white defects by the Echo Integral Mode. They are clearly in the die attach, and not in the substrate. The roughly spherical feature in the upper right of the Thru-Scan image, however, is the shadow of the void in the mold compound above the die.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

Components will continue to shrink

Sonoscan’s laboratories have for some time been imaging PEMs that are only 200 microns thick and 3mm x 3mm in area. The die is typically less than 100 microns thick. In some ways, the small dimensions are an advantage in acoustic imaging: the plastic encapsulant scatters and absorbs ultrasound, so the less encapsulant the pulse and the resulting echo need to travel through, the better the resolution in the acoustic image. Such a component may be imaged with the very high frequency of 230 MHz, rather than the 15 MHz to 100 MHz of larger plastic packages. Higher frequency means better spatial resolution in the acoustic image.

One of the most commonly imaged non-PEM components is the ceramic chip capacitor, where the goal is to image delaminations and cracks that can lead to leakage between electrode layers. The very smallest ceramic chip capacitors currently being manufactured measure 0.010 inch by 0.005 inch. They can be imaged acoustically, but extremely small dimensions make imaging time-consuming.

Mid-end components

So named because they involve both front-end and back-end processes, mid-end components are typically assembled by mounting flip chips onto a wafer and then encapsulating the flip chips with plastic before dicing the wafer. They have been described as non-wired QFNs.

What has evolved is that some mid-end components can be imaged well enough to see details of the solder bump bonds, while others cannot. Sonoscan has developed transducers having an acoustic frequency that is low enough to get through the plastic encapsulant, and high enough to give good details about the bump bonds.

But many mid-end components have an encap- sulant that is only partly transparent to ultrasound. Gross features and defects will be visible, but not the details of the bump bonds, which will probably become even smaller in the future. The alternative is to use the Thru-Scan imaging mode. Any gap in between, such as a break in a solder bump, will block the arriving ultrasound and be visible as a black feature. These acoustic shadows contain no information about the depth of a feature, but the relatively simple design along with experience with a given mid-end component are helpful.

The evolution of package design may in time alleviate the encapsulant problem. The trend is toward more chip-on-wafer type designs, and toward ever-smaller dimensions. The encapsulants may perhaps become unnecessary; their departure would enhance acoustic inspection.

Stacked die

Individual components typically have industry standards that can be used to judge the risk posed by a void in the die attach material or a delamination along a lead finger. Stacked die have no industry standards; presumably each maker of stacked die uses their own guidelines to reduce field failures.

Die stacks can be imaged acoustically before encapsulation, and in the future some may be imaged after encapsulation, particularly if ultrasound-friendly encapsulants are used. In both situations, the same problem occurs: each pulse encountering a material interface is partly reflected and partly transmitted across the interface. Unencapsulated stacks are typically imaged during development in order to refine assembly processes. Even a four-die stack (that has at least eight interfaces) can generate so many echoes that it becomes very difficult to identify the echo being sent by the delamination of the adhesive on the top of die #3.

For unencapsulated stacks, this problem has largely been solved by software developed jointly by Sonoscan and the Technical University of Dresden. The software uses material properties and dimensions to create a virtual stack as much like the physical stack as possible, and works out the imaging techniques, which are then further refined on the physical stack. The goal is to identify the echoes that were returned from specific depths of interest – e.g., the interface between the bottom surface of die #6 and the adhesive beneath it. By repeatedly moving between the virtual sample and the physical sample, the imaging parameters are defined that will show the echoes at this depth.

Nearly all memory devices are stacked, and the die are wire-bonded to each other. But there are stacks have many different configurations; one common configuration puts a small memory chip on top of a larger processing chip.

It’s hard to tell where the architecture of die stacks may go from here. In some stacks, through-silicon vias (TSVs) will replace wires. Defects such as delamina- tions will be visible acoustically, but whether the TSVs will be visible acoustically is difficult to judge at this point. What manufacturers want to see is that each TSV is filled. Their diameters are already extremely small. Whether acoustic methods will be devised to make them nondestructively visible is not known yet.

A long-standing problem in imaging typical PEMs is that a delamination on the back side of the die paddle cannot be imaged when scanning the top side of the PEM. Before the PEM is surface-mounted, it can simply be flipped over and imaged from the back side. After mounting, only the top surface is available for scanning. The problem is that there are too many interfaces: the pulsed ultrasound must cross the top surface of the plastic, the plastic-to-die interface, the die-to-die attach interface, and the die attach-to-die paddle interface. This is essentially the same problem encountered in the imaging of stacked die. In theory, a delamination between the die paddle and the plastic below it can be located and imaged by the software developed for die stacks.

Package-on-package

Package-on-package assemblies, such as a package containing one or more memory die on top of a package containing one or more logic die, are beginning to appear in Sonoscan’s testing laboratories. These package designs have some advantages over the stacking of die; for example, if one of the two packages is found to be defective before assembly, it can be replaced, while the logic package is retained. It seems likely that the popularity of these assemblies will increase in the next few years.

After the two packages are bonded together, the chief structural reliability concern is the adhesive between the two packages. This is where gap-type defects, primarily voids, may be found. If present, voids put stress on the solder joints for the BGA balls.

How acoustic imaging is performed depends on the structure of the assembly. Normal reflection-mode pulse-echo imaging can sometimes be used, but the assembly is likely to have numerous material interfaces that could limit the effectiveness of this method. Because internal structural defects in this assembly are largely limited to voids at a specific known depth, it often makes more sense to use the Thru-Scan mode to reveal the voids.

Interposers

The term “interposer” is used rather loosely to describe a redistribution layer between a top die and a lower die or printed circuit board. chip and the solder balls that make connection with a substrate. In terms of acoustic imaging, interposers behave much like flip chips, in that the depth of interest is between two structures.

The common defects are delaminations, signif- icant because they are capable of attracting contaminants (and thus causing corrosion) and of expanding through thermal cycling. The growth of chips having advanced processing capabilities will likely make the acoustic imaging of interposers more frequent.

Summary

The advantage of acoustic micro imaging tools is their ability to image nondestructively gap-type anomalies and certain other anomalies (tilting, warping) in electronic materials. In recent years, the original Amplitude Mode has been joined by roughly a dozen other modes that push imaging capabilities into new areas.

It can be expected that electronic components will continue to add their own capabilities and to reduce their physical dimensions. Some components will become more difficult to image; others, particularly those that become thinner or that use acoustically friendly materials, may permit the use of higher frequencies to image smaller features. Since there is no good non-destructive substitute for acoustic modes, engineers who demand reliability may want to apply acoustic micro imaging to new device configurations and keep track of new acoustic imaging modes.

Supplier Hub answers the needs of a changing semiconductor industry. 

BY LUC VAN DEN HOVE, imec, Leuven, Belgium

Supplier HubOur semiconductor industry is a cyclical business, with regular ups and downs. But we have always successfully rebounded, with new technologies that have brought on the next generation of electronic products. Now however, the industry stands at an inflection point. Some of the challenges to introduce next generation technologies are larger than ever before. Overcoming this point will require, in our opinion, a tighter collaboration than ever. To accommodate that collaboration, we have set up a new Supplier Hub, a neutral platform where researchers, IC producers, and suppliers work on solutions for technical challenges. This collaboration will allow the industry to overcome the inflection point and to move on to the next cycle of success, driven by the many exciting application domains that appear on the horizon.

Call for a new collaboration model

The formulas for the industry’s success have changed. Device structures are pushing the limits of physics, making it challenging to continue progressing according to Moore’s Law. Intricate manufacturing requirements make process control ever more difficult. Also chip design is more complex than ever before, requiring more scrutiny, analysis and testing before manufacturing can even begin. And the cost of manufacturing equipment and setting up a fab has risen exponentially, shutting out many smaller companies and forcing equipment and material suppliers to merge.

In that context, more and more innovation is coming from the supplier community, both from equipment and material suppliers. But as processes are approaching some fundamental limits, such as material limits, chemical, physical limits, it is also for suppliers becoming more difficult to operate and develop next-generation process steps in an isolated way. An earlier and stronger interaction among suppliers is needed.

All this makes a central and neutral platform more important than ever. That insight and the requests we got from partners set imec on the path to organizing a supplier hub. A hub that is structured as a neutral, open innovation R&D platform, a platform for which we make a substantial part of our 300mm cleanroom floor space available, even extending our facilities. It is a platform where suppliers and manufacturers collaborate side-to- side with the researchers developing next-generation technology nodes.

Organizing the supplier hub is a logical evolution in the way we have always set up collaborations with and between companies that are involved in semiconductor manufacturing. Collaborations that have proven very successful in the previous decade and that have resulted in a number of key innovations.

Supplier Hub off to a promising start

Today, both in logic and in memory, we are developing solutions to enable 7nm and 5nm technology nodes. These will involve new materials, new transistor architectures, and ever shrinking dimensions of structures and layers. At imec, the bulk of scaling efforts like these used to be done in collaborative programs involving IDMs and foundries, but also the fabless and fablite companies. All of these programs were strongly supported by our partnerships with the supplier community.

But today, to work out the various innovations in process steps needed for future nodes, we simply need this stronger and more strategic engagement from the supplier community, involving experimenting on the latest tools, even if they are still under development. And vice-versa, the tool and material suppliers can no longer only develop tools based on specs documents. To fabricate their products successfully and on time, they need to develop and test in a real process flow, and be involved in the development of new device concepts, to be able to fabricate tools and design process steps that match the requirements of the new devices.

A case in point: it is no longer possible now to develop and asses the latest generation of advanced litho without matching materials and etch processes. And reversely, the other tool suppliers need the result of the latest litho developments. So today, all process steps have to be optimized concurrently with other process steps, integrating material innovations at the same time. And this is absolutely necessary for success.

So that’s where the Supplier Hub enters.

In 2013, imec announced an extended collaboration with ASML, involving the set up an advanced patterning center, which will grow to 100 engineers. In 2014, the new center was started as the cornerstone of the supplier hub. Mid 2014, Lam Research agreed to partake in the hub. And since then a growing number of suppliers has been joining, among them the big names in the industry. Some of more recent collaborations that we announced e.g. were Hitachi (CD-SEM metrology equipment) and SCREEN Semiconductor Solutions (cleaning and surface preparation tools).

End of 2014, ASML started installing its latest EUV-tool, the NXE:3300. In the meantime, we have initiated building a new cleanroom next to our existing 300mm infrastructure. The extra floor space will be needed to accommodate all the additional equipment that will come in in the frame of the tighter collaboration among suppliers. Finally, during our October 2014 Internal Partner Conference, we organized a first Supplier Collaboration Forum where the suppliers discussed and evaluated their projects with all partners, representing a large share of the semiconductor community.

We have also been expanding the supplier hub concept through a deeper involvement of material suppliers. These will prove a cornerstone of the hub, as many advances we need for scaling to the next nodes will be based on material innovations.

Enabling the Internet-Of-Everything

I hold great optimism for the industry. The last years, the success of mobile devices has fueled the demand for semiconductor-based products. These mobile applications will continue to stimulate data consumption, going from 4G to 5G as consumers clamor for greater data availability, immediacy, and access. Beyond the traditional computing and communications applications loom new markets, collectively called the ‘Internet of Everything.’

In addition, nanoelectronics will enable disruptive innovations in healthcare to monitor, measure, analyze, predict and prevent illnesses. Wearable devices have already proven themselves in encouraging healthier lifestyles. The industry’s challenge is now to ensure that the data delivered via personal devices meet medical quality standards. In that frame, our R&D efforts will continue to focus on ultra-low-power multi-sensor platforms.

While there are many facets to the inflection point puzzle, the answers of the industry begin to take shape. The cost of finding new solutions will keep on rising. Individual companies carry ever larger risks if their choices prove wrong. But through closer collabo- ration, companies can share that risk while developing solutions, exploring and creating new technologies, shorten times to market, and be ready to bring a new generation of products to a waiting world. The industry may indeed stand at an inflection point, but the future is bright. Innovation cannot be stifled. And collaboration remains the consensus of an industry focused on the next new thing. Today, IC does not just stand for Integrated Circuit, it indeed calls for Innovation and Collaboration.

The recent acquisition of Freescale Semiconductor by NXP Semiconductors would catapult the merged entity into the world’s eighth-largest chipmaker, positioning the newly minted giant for an even more formidable presence in key industrial sectors, according to IHS, a global source of critical information and insight.

Prior to the merger, NXP ranked 15th in revenue and Freescale 18th. With combined revenue last year of approximately $10 billion, the resulting new company would have surpassed Broadcom. Only Intel, Samsung Electronics, Qualcomm, SK Hynix, Micron Technology, Texas Instruments and Toshiba would have been bigger, as shown in the table below.

Global Top 10 Semiconductor Makers’ Revenue Share

2014 Company  Revenue Share
Rank
1 Intel 14.14%
2 Samsung Electronics 10.77%
3 Qualcomm 5.46%
4 SK Hynix 4.56%
5 Micron Technology 4.56%
6 Texas Instruments 3.46%
7 Toshiba 2.90%
8 NXP-Freescale (Merged) 2.83%
9 Broadcom 2.38%
10 STMicroelectronics 2.10%

 

“The merged company’s strength will be especially apparent in automotive-specific analog applications,” said Dale Ford, vice president and chief analyst at IHS. “Automotive products clearly will be the biggest convergence resulting from a merged product portfolio of the Dutch-based NXP and its smaller U.S. rival.”

The amalgamated NXP-Freescale would place the company in second place in the area of microcontroller units (MCUs), which are integrated circuits for embedded and automatically controlled applications, including automotive engine-control systems.  The merged company could also affect the digital signal processing (DSP) market, where Texas Instruments reigns supreme. DSPs are an important component in the audio and video handling of digital signals used in myriad applications, including mobile-phone speech transmission, computer graphics and MP3 compression.

“While both NXP and Freescale boast diverse portfolios with complementary products, the high-performance lines of the two chipmakers have very different target solutions,” said Tom Hackenberg, senior analyst for MCUs and microprocessors at IHS.

Freescale has been a key strategic provider of high-reliability automotive, telecomm infrastructure and industrial solutions, including both application-specific and general-purpose products that go after high-performance applications. NXP’s broad portfolio, by comparison, has strategically targeted precision analog and low-power portable-device applications, most of which are directed at portable wireless, automotive infotainment, consumer components and a complementary base of industrial components, including secure MCUs for smart cards. Even in the auto industry, where the two companies both focus on infotainment, their technologies harmonize: NXP dominates the radio market, while Freescale fills a large demand for low- to midrange center-stack processors and instrument cluster controllers.

“The most significant processor competition will likely occur in low-power connectivity solutions, where both chipmakers offer competitive connectivity MCUs,” said Hackenberg. “In particular, the newly merged company will be well-positioned to make groundbreaking advances in the human-machine interface market.”

Freescale recently began developing its portfolio of vision-related intellectual property with Canadian maker CogniVue, used in advanced driver assistance systems (ADAS). For its part, NXP has solid voice-processing expertise. Both companies overall have strong sensor fusion intellectual property, with each maker tending toward different applications. “The resulting combination could offer strategic symmetry in combined vision-, voice- and motion-controlled systems,” Hackenberg added.

Another important aspect of the merger is that Freescale is a near-exclusive source for power architecture processors and processor intellectual property. Although its market share overall is small compared to x86 and ARM, Freescale plays a significant role in the military aerospace industry, where many high-reliability equipment controls rely on power architecture. “While the acquisition of Freescale by a foreign owner is unlikely to be a deal breaker, the development could have some bearing on the approval process in the military, as it will now involve a non-U.S. company possessing ownership of its primary source of military aerospace specific Power Architecture,” Hackenberg noted.

Cypress Semiconductor Corp. and Spansion, Inc. yesterday announced that they have closed the merger of the two companies in an all-stock, tax-free transaction valued at approximately $5 billion. In a special meeting earlier today, Cypress shareholders approved the issuance of 2.457 shares of Cypress stock to Spansion shareholders for each Spansion share they own. Spansion shareholders approved the merger in a separate special meeting. The merger is expected to achieve more than $135 million in cost synergies on an annualized basis within three years and to be accretive to non-GAAP earnings within the first full year after the transaction closes. The combined company will continue to pay $0.11 per share in quarterly dividends to shareholders.

Cypress President and CEO T.J. Rodgers is scheduled to talk about the merger live on the Fox Business News program, “Opening Bell,” hosted by Maria Bartiromo, Friday morning at 7:30 a.m. PDT. A four-minute video of Rodgers and Spansion CEOJohn Kispert, describing the synergies of the merger and benefits for Cypress and Spansion customers, is available on the Cypress website atwww.cypress.com/NewCypress.

“We closed this merger even more quickly than originally anticipated, accelerating our strategic and financial roadmap,” Rodgers said. “From Day One, the new Cypress will capitalize on its expanded product portfolio and leadership positions in embedded processing and specialized memories to significantly extend its penetration of global markets such as automotive, industrial, consumer, wearable electronics and the Internet of Things.”

“Consider the automotive market, where Cypress has a dominant position in capacitive touch-sensing controllers and SRAMs for infotainment systems, and Spansion is the leading supplier of flash memory and microcontrollers for infotainment, body and climate control systems, instrument clusters and advanced driver assistance systems,” Rodgers said. “The new Cypress will be the No. 3 chip supplier worldwide of memories and microcontrollers to this business. You can think of the post-merger company truly in terms of the well-known equation: 1 + 1 = 3: No. 1 in SRAMs, No. 1 in NOR flash and No. 3 overall.”

“Spansion’s exceptional team and technology leadership in high-performance memory and MCUs will complement Cypress’s strong capabilities. This merger was an important step forward in Spansion’s transformation into a global embedded systems leader,” said Kispert, CEO of Spansion and a member of the Cypress board of directors. “Together, we can significantly enhance our value to our customers and deliver a more robust and broader product line to meet their embedded requirements.”