Tag Archives: letter-ap-top

By DAVE HEMKER, Senior Vice President and Chief Technology Officer, Lam Research Corp.

Given the current buzz around the Internet of Things (IoT), it is easy to lose sight of the challenges
– both economic and technical. On the economic side is the need to cost-effectively manufacture up to a trillion sensors used to gather data, while on the technical side, the challenge involves building out the infrastructure. This includes enabling the transmission, storage, and analysis of volumes of data far exceeding anything we see today. These divergent needs will drive the semiconductor equipment industry to provide very different types of manufacturing solutions to support the IoT.

In order to fulfill the promise of the IoT, sensor technology will need to become nearly ubiquitous in our businesses, homes, electronic products, cars, and even our clothing. Per-unit costs for sensors will need to be kept very low to ensure the technology is economically viable. To support this need, trailing-edge semiconductor manufacturing capabilities provide a viable option since fully depreciated wafer processing equipment can produce chips cost efficiently. For semiconductor equipment suppliers, this translates into additional sales of refurbished and productivity-focused equipment and upgrades that improve yield, throughput, and running costs. In addition to being produced inexpensively, sensors intended for use in the IoT will need to meet several criteria. First, they need to operate on very low amounts of power. In fact, some may even be self-powered via MEMS (microelectromechanical systems)-based oscillators or the collection of environmental radio frequency energy, also known as energy harvesting/scavenging. Second, they will involve specialized functions, for example, the ability to monitor pH or humidity. Third, to enable the transmission of data collected to the supporting infrastructure, good wireless communications capabilities will be important. Finally, sensors will need to be small, easily integrated into other structures – such as a pane of glass, and available in new form factors – like flexible substrates for clothing. Together, these new requirements will drive innovation in chip technology across the semiconductor industry’s ecosystem.

The infrastructure needed to support the IoT, in contrast, will require semiconductor performance to continue its historical advancement of doubling every 18-24 months. Here, the challenges are a result of the need for vast amounts of networking, storage in the Cloud, and big data analysis. Additionally, many uses for the IoT will involve risks far greater than those that exist in today’s internet. With potential medical and transportation applications, for example, the results of data analysis performed in real time can literally be a matter of life or death. Likewise, managing the security and privacy of the data being generated will be paramount. The real-world nature of things also adds an enormous level of complexity in terms of predictive analysis.

Implementing these capabilities and infrastructure on the scale imagined in the IoT will require far more powerful memory and logic devices than are currently available. This need will drive the continued extension of Moore’s Law and demand for advanced semiconductor manufacturing capability, such as atomic-scale wafer processing. Controlling manufacturing process variability will also become increasingly important to ensure that every device in the new, interconnected world operates as expected.

With development of the IoT, semiconductor equipment companies can look forward to opportunities beyond communications and computing, though the timing of its emergence is uncertain. For wafer processing equipment suppliers in particular, new markets for leading-edge systems used in the IoT infrastructure and productivity-focused upgrades for sensor manufacturing are expected to develop.

The most expensive defect


December 18, 2014

Defects that aren’t detected inline cost fabs the most. 

By DAVID W. PRICE and DOUGLAS G. SUTHERLAND, KLA-Tencor, Milpitas, CA

Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis). Here, we are referring to the term defect in a general sense—the same concepts also apply to metrology measurements.

The third fundamental truth of process control for the semiconductor IC industry is:

The most expensive defect is the one that wasn’t detected inline.

FIGURE 1A (top) shows an imaginary SPC chart for a factory experiencing a baseline shift in defectivity (an excursion) beginning at Lot #300. FIGURE 1B (bottom) shows the same scenario except the fab has an effective inline monitor at the point of the excursion. In this case, the excursion is quickly identified and the offending process tool is taken offline for process tuning or maintenance. The excursion is contained and relatively few lots are impacted by the resulting yield loss.

Defects 1a

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

The difference between these two scenarios is that in the top chart, the fab is unable to detect the excursion inline so the baseline shift continues unabated until the first affected lots hit end of line test. For a foundry process with a 60-day cycle time, this delay could easily exceed 20 days.

In our experience working with IC manufacturers, the majority of financial impact does not come from large excursions that cause significant yield loss to every affected wafer—those problems are usually identified and rectified very early on. Rather, the largest losses usually come from small excursions that are difficult to detect. They cause relatively low levels of yield loss but persist for prolonged periods of time. It is not uncommon to see thousands or even tens of thousands of wafers exposed to these low level excursions.

The culprit is nearly always a process control capability issue that can be traced back to one or more possible problems. The following list is not meant to be exhaustive, but is instead, representative of the most common causes:

Defects 2

FIGURE 2. Cost vs. mean time to detection (MTTD) of finding a defect inline. The curves are drawn for 4 different wafer costs in a fab with 100k WSPM. It is assumed that the excursion takes place at a single step in the process and happens once per year to each of the process tools at that step. The yield loss is assumed to be 20% during the excursion.

  • Insufficient number of inspection points to allow effective isolation of the defect source.
  • Failing to use a sensitive enough inspection tool or recipe (pixel size is too large, wrong wavelength,
  • etc.)
  • Inspection area of wafer is too low.
  • Review sample size is too small.

Often, the original inspection strategy was carefully designed, but as time passed, changes were made to reduce costs. As new sources of noise are introduced in the SPC chart, the fab becomes less sensitive to small excursions.

FIGURE 2 shows the economic impact to the fab for the two scenarios shown by the SPC chart in FIGURE 1. Imagine an excursion which results in a net 25 percent yield loss (e.g., one out of four wafers must be scrapped). Finding that excursion at end-of-line (+30 days) versus inline (greater than one day) would amount to a staggering $21 million loss per occurrence for an average size run rate of 25k wafer starts per month. Given that this value only repre- sents the cost of re-manufacturing the scrapped wafers it could actually be a conservative estimate. The true cost could easily be double that amount for a fab that is running at the limit of their capacity since it would directly impact revenue.

Even if the situation requires the use of a relatively expensive inspection tool to find, monitor and resolve the problem, it is nearly always in the factory’s best interest to do so. One of the implications of this truth is that if an important defect type can only be detected by a certain inspection tool, then that inspection tool is almost always the most cost-effective solution for that layer. Rather than modifying process control strategies to save costs, it is nearly always in the factory’s best interest to maintain capable, inline process control strategies that prevent the financial impact of ‘the most expensive defect.’

Author’s Note: This is the third in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

Read more Process Watch:

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

 

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the fourth in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Nobody likes surprises—especially the managers of $10 billion factories. In a dynamic field like advanced semiconductor IC fabrication, there will always be unknowns. However, it is critical to know what you know and know what you don’t know. Every measurement has error. The quality of the decision you make is highly dependent on the uncertainty in the data used to make that decision.

Process control spending is discretionary. Fabs will invest to the point that they believe the return on investment is favorable. It may make financial sense to sample less, skip certain measurements, or use a less capable inspection/metrology tool. However, the fab must always face facts and quantify the level of risk associated with these decisions. The stakes—missing an excursion resulting in costly yield loss—are too high to live in denial.

The fourth fundamental truth of process control for the semiconductor IC industry is: 

Always quantify your lots at risk when making changes to your process control strategy

Quantifying your lots at risk equates to understanding the uncertainty in your measurement. This is a basic concept that most factory engineers learned at some point during their education, however, it is also one of the most tedious of tasks. As a result, this portion of the analysis is skipped more often than we care to admit.

Within process control there are really only two types of risk: Alpha risk and Beta risk. Alpha risk is a false alarm; it is when your inspection tells you that the wafer measured is out of control when really there is nothing wrong with the larger process. Beta risk is the opposite of this; it is when your inspection tells you that the wafer you measured was in control but really there is a serious problem. Figure 1 summarizes the difference.

KLAT_FIGURES-1

Figure 1. Definition of Alpha risk and Beta Risk

Alpha and Beta risk arise as a result of the inability to consistently make an inspection that accurately represents the process at that point in time. The best way to reduce both types of risk is to make the process itself less variable. There are few, if any, activities in semiconductor manufacturing that are more value-added than driving variability out of the process. It is much easier to spot real changes in the process when the native lot-to-lot variation is low. However, this cannot always be easily achieved and the Alpha risk (the number of false alarms) can sometimes only be reduced by moving the control limits further from the target (raising the upper control limit and / or lowering the lower control limit). Increasing the spread between the control limits will reduce the Alpha risk but it comes at the expense of increasing the Beta risk—it makes the inspection process less sensitive to real excursions.

Just as changing the native variability in the process usually warrants reassessing where to place the control limits, any time the characteristics of the measurement itself are changed (changing the sensitivity of the recipe, changing the area of the wafer that is inspected, changing the size of the review sample, etc.) the position of the control limits also needs to be re-evaluated.

As an example, consider a defect inspection step where 100 percent of the wafer area is inspected. For a particular defect of interest (DOI) the inspection finds between 40 and 60 DOI on each wafer under normal conditions and the upper control limit (UCL) is placed at 61. If the inspection strategy is changed such that further inspections will only sample 50 percent of the wafer area, the range of normal values will change from between 40 and 60 to between 12 and 42 for 50 percent area (or 24 and 84 when normalized back to the full wafer count). The increase in range is a result of the Binomial Probability Theory that quantifies the effect that sometimes there will be a disproportionate number of DOI in the area that was inspected and sometimes there will be a disproportionate number of DOI in the area that was not inspected.

With the stroke of a pen, the decision to reduce the wafer area to 50 percent has tripled the variability in this particular part of the process from a range of 20 to a range of 60 DOI per wafer. In doing so, they have undone months of hard work by a team of engineers who worked diligently to drive the variability out of the process in the first place. The fab manager must now choose to keep the UCL at 61 and suffer many more false alarms or raise the UCL to 85 where they will have approximately the same number of false alarms but be much less sensitive to real excursions.

The impact of changing the inspected wafer area depends on several factors including the average DOI, the native variation and the size of the excursion that one is trying to detect. Figure 2 shows how the percent error changes as a function of wafer area for three different DOI counts.

KLAT_FIGURES-2

Figure 2.  Percent Error versus Wafer Area for three different DOI counts.  At 100 percent area there is no error introduced into the measurement. As the area decreases, the error increases. The error is largest for low DOI counts and is bounded by -100% on the low side and unbounded on the high side.

We have chosen the example of wafer area to illustrate the point because it is such a common practice but the same principles apply to all aspects of process control. The measurement is part of the process― when you degrade the quality of the measurement you degrade the quality of the process.

There are many ways in which process control risk manifests itself in the fab. One simple approach is to get in the habit of asking the questions: “how many lots are at risk if I do this?” and, “what are the error bars on this analysis?”

For example, how many lots are at risk if the fab:

  • Skips an inspection step?
  • Uses a less sensitive inspector or pixel size?
  • Reduces the sampling rate?
  • Use a less precise metrology tool?
  • Measure fewer features per wafer?

Changing process control strategy to reduce costs may seem like a short term solution but it is seldom if ever sustainable for one very simple reason: fab managers don’t like surprises!

References:

1)     You Can’t Fix What You Can’t Find, Solid State Technology, July 2014

2)     Sampling Matters, Semiconductor Manufacturing and Design, September 2014

3)     The Most Expensive Defect, Solid State Technology, December 2014

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Process Watch blog series: 

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The semiconductor equipment and materials industry is currently enjoying a double-digit annual growth rate and good prospects looking forward to 2015.  However, there are huge challenges around the corner with the move from planar to FinFET transistors, with 193nm immersion lithography being pushed well below 14nm, and with an explosion of new materials to integrate, among others.

The SEMI International Technology Partners Conference (ITPC 2014) convened on 9-12 November on the bright and crystalline Kohala Coast of the Big Island of Hawaii.  Like our industry, all looked calm and peaceful – yet just around the corner, the Kilauea Volcano was violently reshaping the landscape with rivers of molten lava in the town of Pahoa.

Living in the shadow of an active volcano and the sometimes spectacularly disruptive process of building an island – or the nano-electronics manufacturing industry in our case – was picked up in this year’s ITPC theme:  New Structures for Innovation.  Wholly new concepts for collaboration and partnerships to address the challenges and to enable innovation were discussed formally in the conference, as well as informally in the many networking opportunities.

The program included keynote presentations by driving IC manufacturers:  Intel, SMIC, SK Hynix, TSMC, and Micron to set the stage for the rest of the program by hitting the key issues:

  • Delivering density scaling benefits in an era of increased capital intensity and materials complexity (Intel and SMIC)
  • Trends in semiconductor development following changes in the mobile market (SK Hynix)
  • Limits of lithography beyond the 10nm node (TSMC)
  • Collaboration for innovation (Micron)

Each of these keynote presentations neatly distilled the related challenges and opportunities and provided richly provocative observations on what is needed to keep innovation as the fundamental enabler.

Beyond the exceptional insights and depth of these presentations, a few “fun facts” were captured below.

  • Intel’s pursuit of 450mmm has had a positive impact on 300mm productivity (Bob Bruck, Intel)
  • China’s overall two highest revenue imports are oil and ICs  (Tzu-Yin Chiu, SMIC)
  • To succeed in today’s IC manufacturing world there needs to be system-level and process-level partnership and collaboration across the extended supply chain  (Sungwook Park, SK Hynix)
  • Of the Fortune 500 companies from 30 years ago, only 15% remain today.  Large companies are often too slow to react to change (Mark Adams, Micron)
  • Facebook and Google are now among the top six server manufacturers in the world (Mark Adams, Micron)

The conference continued with an industry and market outlook segment with special attention to IoT, electric vehicles, and nanoelectronics “connecting lives to improving lives.”  This included some amazing video clips of Nissan’s autonomous driving electric vehicles in Japan traffic, and imec’s intense visualizations of next generation nano-bio applications.

Among the best appreciated sections, was the segment on new industry structure that featured speakers and panelists from Google (David Peterson), Robert Metcalfe (University of Texas), Dan Solomon (Solomon Consulting), and AlixPartners (Dan Fisher). David Peterson brought a perspective from outside of our industry which is useful to test ideas and refresh approaches. He asked the audience to start with the most difficult ideas: make the tough choices, ask the questions that no one else will, and nurture a vibrant, distinctive culture. On making the tough choice, he was specific – and it is indeed tough, “sub-optimize current performance to invest in future performance:  innovations, R&D, learning, leadership development, building an adaptable organization, experimenting with ideas and projects that may not succeed. This segment was capped by Shozo Saito (Toshiba) providing an overview on the connections of new market and industry structure by device platform development.

The final segment focused on technology with Frits van Hout of ASML presenting the EUVL transition from R&D to industrialization. Following this a panel, moderated by Dan Hutcheson of VLSI Research, focused on frontiers of technology with panelists Paul Boudre of Soitec, David Hemker of Lam Research, Michael Liehr of CNSE, and Omkaram Nalamasu of Applied Materials.

It was a fascinating conference that both discussed the need and models for new collaboration and partnerships – and brought our industry’s thought leaders together to have opportunities to find these connections during the conference.

A few more interesting “fun facts” “fun bits” from the conference:

  • China plans to spend $100B to build a China-local IC industry that will supply up to 40% of China’s IC consumption.
  • The era of planar technology is coming to an end – and this precipitates great changes.
  • There is virtually no viable small company R&D engine model remaining in ICs and semiconductor equipment.  The model for innovation in our industry has significantly changed in the last five years.
  • Collaborations and partnerships are more essential now than ever before for developing innovation.
  • To build trust in developing partnerships, potential partners should work together and take many small risks together quickly.
  • Among the top innovations in our industry is Moore’s law and inventing SEMI – this is one of the big successes in collaboration and co-opetition.
  • A twelve week cycle from tape-out to finished wafer is too long.  This must change to keep pace with product development innovation.
  • The semiconductor industry should quickly work to define standards/platforms for IOT to ensure the pace of growth and chip consumption
  • A favorite slide was from Google that reminded the audience that to win, we have to view any customer problem as our problem:

ITPC

To participate in other strategic events, consider the SEMI Industry Strategy Symposium U.S. 2015 in January or SEMI Industry Strategy Symposium Europe 2015 in February.

3D TSV begins


December 10, 2014

3D TSV integration has already been adopted in MEMS and CMOS Image Sensors for consumer applications (Source: 3DIC & 2.5D TSV Interconnect for Advanced Packaging Business Update report). Device makers such as Sony, Toshiba, Omnivision, Samsung, Bosch Sensortec, STMicroelectronics and mCube … have all brought devices to the market that integrate 3D TSV technology.

“TSV’s added- value is important: increased performance and functionality, more compact devices, more efficient utilization of the silicon space,” explained Yole Développement (Yole). Moreover, even if 3D TSV process steps are adding cost at the device manufacturing level, these technologies enable cost- saving in other parts of the supply chain.

tsv

“No more doubts about adoption of 3D TSV platform across a wider range of applications: all key players added 3D TSV into their roadmaps, engineering samples have already started to ship and preparation is on-going for entering volume manufacturing,” said Rozalia Beica, CTO & Business Director, Advanced Packaging and Semiconductor Manufacturing at Yole. This year, the industry witnessed several memory product announcements for high-end applications, with transfer to volume production planned in the near future.

“Driven by the demand to further increase in performance, 2015 will be the year for the implementation of 3D TSV technology in high volume production,” explains Rozalia.

The market research and strategy consulting company, Yole and its advanced packaging team, are closely studying and monitoring the industry’s activities in this field. The latest results can be found in Yole’s new 3DIC & 2.5D Business Update Report published this year.

Yole’s vision on further 3D TSV technology adoption will be presented during the European 3D TSV Summit 2015 in Grenoble. The company is partnering with SEMI to support the European TSV Summit, which will take place in Grenoble, France on January 19 to 21, 2015. The European 3D TSV Summit is organized by SEMI Europe. To meet Yole’s experts, discover the detailed program and register, click European 3D TSV Summit 2015.

Also, at the European 3D TSV Summit, Jean-Christophe Eloy, President & CEO, Yole will moderate the panel discussion, “From TSV Technology to Final Products – What is the Business for 3D Smart Systems?” taking place on Tuesday 20, at 5:20 PM. Jean-Christophe will highlight 3D TSV market trends and technology challenges, especially its integration for 3D smart systems application. He will welcome the following panelists: Ron Huemoeller, Senior VP Advanced Product / Platform Development, AMKOR – Martin Schrems, VP of R&D, ams AG – Bryan Black, Senior Fellow, AMD – Mustafa Badaroglu, Senior Program Manager, Qualcomm.

In parallel, Rozalia Beica will be part of the Market Briefing Symposium, on Monday 19. Her presentation is entitled: “From Development to Manufacturing: An Overview of Industry’s 3D Packaging Activities”.

“We are excited to have a group of highly qualified market experts, such as Yole Développement, joining us this year for the European 3D TSV Summit,” stated Anne-Marie Dutron, Director of SEMI Europe’s Grenoble office. “To highlight the adoption of 3D TSV technology in several market applications and to answer the demand from our members, we have given the business aspects of the 3D TSV industry more importance in this 2015 edition.”

The European 3D TSV Summit final program is now available.

The Semiconductor Industry Association (SIA) today announced that worldwide sales of semiconductors reached $29.7 billion for the month of October 2014, an increase of 9.6 percent from the October 2013 total of $27.1 billion and an uptick of 1.5 percent compared to last month’s total of $29.2 billion.

Sales in the Americas increased 12.2 percent year-over-year in October, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects substantial growth for 2014 and moderate growth for 2015 and 2016.

“Year-over-year global semiconductor sales increased for the eighteenth straight month in October, and the industry is well-positioned for a strong close to 2014,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Sales continue to be strong across the board, with nearly all regions and product categories exhibiting increases. We expect nearly double-digit growth in 2014, followed by moderate growth in 2015 and 2016.”

Regionally, sequential monthly sales increased in the Americas (5.8 percent) and remained roughly flat in Asia Pacific (up 0.7 percent), Europe (down 0.1 percent), and Japan (down 0.6 percent). Compared to October 2013, sales increased in the Americas (12.2 percent) as noted above, Asia Pacific (12.1 percent), and Europe(5.2 percent), but decreased in Japan (-3 percent).

Additionally, SIA today endorsed the WSTS Autumn 2014 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $333.2 billion in 2014, a 9 percent increase from the 2013 sales total. WSTS predicts year-over-year increases for 2014 in Asia Pacific (11.4 percent), Europe (8.7 percent), the Americas (6.9 percent), and Japan (1.3 percent).

Beyond 2014, the industry is expected to grow steadily and moderately across all regions, according to the WSTS forecast. WSTS predicts 3.4 percent growth globally for 2015 ($344.5 billion in total sales) and 3.1 percent growth for 2016 ($355.3 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

October 2014
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.06 6.41 5.8%
Europe 3.21 3.21 -0.1%
Japan 3.03 3.01 -0.6%
Asia Pacific 16.93 17.05 0.7%
Total 29.23 29.69 1.5%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.71 6.41 12.2%
Europe 3.05 3.21 5.2%
Japan 3.11 3.01 -3.0%
Asia Pacific 15.22 17.05 12.1%
Total 27.09 29.69 9.6%
Three-Month-Moving Average Sales
Market May/Jun/Jul Aug/Sep/Oct % Change
Americas 5.47 6.41 17.2%
Europe 3.24 3.21 -1.1%
Japan 3.04 3.01 -0.9%
Asia Pacific 16.38 17.05 4.1%
Total 28.13 29.69 5.5%

WSTS Autumn 2014 Forecast

Autumn 2014 Amounts in US$M Year on Year Growth in %
2013 2014 2015 2016 2013 2014 2015 2016
Americas 61,496 65,763 69,274 71,432 13.1 6.9 5.3 3.1
Europe 34,883 37,923 38,491 39,732 5.2 8.7 1.5 3.2
Japan 34,795 35,239 35,133 35,452 15.2 1.3 -0.3 0.9
Asia Pacific 174,410 194,226 201,648 208,656 7.0 11.4 3.8 3.5
Total World – $M 305,584 333,151 344,547 355,272 4.8 9.0 3.4 3.1
Discrete Semiconductors 18,201 20,441 21,347 21,980 -4.9 12.3 4.4 3.0
Optoelectronics 27,571 29,498 30,958 31,983 5.3 7.0 4.9 3.3
Sensors 8,036 8,627 9,151 9,624 0.3 7.4 6.1 5.2
Integrated Circuits 251,776 274,586 283,090 291,685 5.7 9.1 3.1 3.0
Analog 40,117 44,217 47,429 49,175 2.1 10.2 7.3 3.7
Micro 58,688 62,211 63,144 64,240 -2.6 6.0 1.5 1.7
Logic 85,928 89,547 91,488 93,927 5.2 4.2 2.2 2.7
Memory 67,043 78,611 81,029 84,343 17.6 17.3 3.1 4.1
Total Products – $M 305,584 333,151 344,547 355,272 4.8 9.0 3.4 3.1

The semiconductor industry directly employs nearly a quarter of a million people in the United States. In 2013, U.S. semiconductor company sales totaled $155 billion, and semiconductors make the global trillion dollar electronics industry possible. Founded in 1977 by five microelectronics pioneers, SIA unites companies that account for 80 percent of America’s semiconductor production.

Cypress Semiconductor Corp. and Spansion, Inc. this week announced a definitive agreement to merge in an all-stock, tax-free transaction valued at approximately $4 billion. The post-merger company will generate more than $2 billion in revenue annually.

“This merger represents the combination of two smart, profitable, passionately entrepreneurial companies that are No. 1 in their respective memory markets and have successfully diversified into embedded processing,” said Rodgers, Cypress’s founding president and CEO. “Our combined company will be a leading provider of embedded MCUs and specialized memories. We will also have extraordinary opportunities for EPS accretion due to the synergy in virtually every area of our enterprises.”

Under the terms of the agreement, Spansion shareholders will receive 2.457 Cypress shares for each Spansion share they own. The shareholders of each company will own approximately 50 percent of the post-merger company. The company will have an eight-person board of directors consisting of four Cypress directors, including T.J. Rodgers and Eric Benhamou, and four Spansion directors, including John Kispert and Ray Bingham, the Spansion chairman, who will serve as the non-executive chairman of the combined company, which will be headquartered in San Jose, California and called Cypress Semiconductor Corporation.

The merger is expected to achieve more than $135 million in cost synergies on an annualized basis within three years and to be accretive to non-GAAP earnings within the first full year after the transaction closes. The combined company will continue to pay $0.11per share in quarterly dividends to shareholders.

“Bringing together these high-performing organizations creates operating efficiencies and economies of scale, and will deliver maximum value for our shareholders, new opportunities for employees and an improved experience for our customers,” said John Kispert, CEO of Spansion. “With unparalleled expertise, global reach in markets like Japan and market-leading products for automotive, IoT, industrial and communications markets, the new company is well positioned to deliver best-of-breed solutions and execute on our long-term vision of adding value through embedded system-on-chip solutions.”

The closing of the transaction is subject to customary conditions, including approval by Cypress and Spansion stockholders and review by regulators in the U.S., Germany and China. The transaction has been unanimously approved by the boards of directors of both companies. Cypress and Spansion expect the deal to close in the first half of 2015.

Jefferies LLC and Morgan Stanley & Co. LLC served as financial advisors and Fenwick & West and Latham & Watkins acted as legal counsel to Spansion. Qatalyst Partners acted as financial advisor and Wilson Sonsini Goodrich & Rosati acted as legal counsel to Cypress.

With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.

The challenges for DRAM are to reduce power consumption, satisfy required bandwidth and satisfy density (miniaturization) requirements all the while maintaining low cost.

Many expect current DDR, both the compute variety (DDR3 / DDR4) and the mobile variety (LPDDR3/LPDDR4) to reach the end of their road soon, as the DDR interface reportedly cannot run at data rates higher than 3.2 Gbps in a traditional computer main memory environment. Thus several new DRAM memory architectures based on 3D layer stacking and TSV have evolved to carry memory technology forward.

The challenges for DRAM are to reduce power consumption, satisfy required bandwidth and satisfy density (miniaturization) requirements all the while maintaining low cost. Applications are evolving with different demands on these basic requirements. For example, graphics in a smartphone may require bandwidth of 15GB/sec while a networking router may require 300GB/sec.

memory_3dicbusiness_1_384x288

Memory is also known to be the biggest user of power in server farms, thus there is a requirement in both portable devices and networking and server applications for low power memory solutions.

Hynix has announced the release of multiple memory solutions over the next 2 years.
Emerging DRAM technologies such as wide IO, HMC and HBM are being optimized for different applications and present different approaches to address bandwidth, power, and area challenges. The common element to HMC, HBM and Wide IO are 3D technologies.

Wide I/O 2: supporting 3D-IC packaging for PC and server applications

Wide I/O increases the bandwidth between memory and its driver IC logic by increasing the IO data bus between the two circuits. Wide I/O typically uses TSVs, interposers and 3D stacking technologies.

The 2014 Wide I/O 2 standard JESD229-2 from JEDEC, is designed for high-end mobile applications that require high bandwidth at the lowest possible power. Wide I/O 2 provides up to 68GBps bandwidth, at lower power consumption (better bandwidth/Watt) with 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint. This standard trades a significantly larger I/O pin count for a lower operating frequency. Stacking reduces interconnect length and capacitance. The overall effect is to reduce I/O power while enabling higher bandwidth.

In the 2.5D-stacked configuration, cooling solutions can be placed on top of the two dies. With the 3D-stacked form of Wide I/O 2, heat dissipation can be an issue since there is no standard way to cool stacked die. The Hybrid Memory Cube is a specialized form of the wide I/O architecture.
The Hybrid Memory Cube (HMC) developed by Micron and IBM is expected to be in mass production in 2014. This architecture consists of 3D stacked DRAM layers on top of a controller logic layer. For example, 4 DRAM die are divided into 16 “cores” and then stacked. The logic base is at the bottom has 16 different logic segments, each controlling the four DRAMs cores that sit directly on top of it . This type of memory architecture supports a very large number of I/O pins between the logic and DRAM cores, which deliver bandwidths as high as 400GB/s. According to the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15x the performance of a DDR3 module and consume 70 per cent less energy per bit than DDR3.

In addition to Micron and IBM, the HMC architecture developer members include Samsung, Hynix, ARM, Open Silicon, Altera, and Xilinx (HMC specs).

High bandwidth memory (HBM)
The 2013 JEDEC HBM memory standard, JESD235 was developed for high end graphics and gaming applications. HBM consisting of stacked DRAM die, built with Wide I/O and TSV, supports 128GB/s to 256GB/s bandwidths. TSMC has recently compared these different memory architectures in terms of bandwidth, power and price.

Architecture choice depends on application
Different applications will have different requirements in terms of bandwidth, power consumption, and footprint.
• Because thermal characteristics are critical in high end smartphones, the industry consensus is that Wide I/O 2 is probably the best choice. Wide I/O 2 meets heat dissipation, power, bandwidth, and density requirements. However, it is more costly than LPDDR4.
• Given its lower silicon cost, LPDDR4 is probably better suited for tablets and low end smart phones, less cost-sensitive mobile markets.
• For high-end computer graphics processing, which are less constrained by cost then mobile devices, HBM memory may be the best choice.
• High performance computing (HPC) or a networking router requiring 300GBps BW is probably best matched to the HMC.
The properties of these standardized memory architectures and the applications they appear best suited for are compared below.
As we move into 2015 several industry segments have announced applications using the new memory stacks.
• Intel recently announced that their Xenon Phi processor “Knights Landing” which will debut in 2015 will use 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth for high performance computing applications.
• AMD and Nvidia have also announced the use of HBM in their next generation graphics modules like the Nvidia Pascal due out in 2016.

Yole Développement has been studying 2.5/3DIC technology and commercial adoption for nearly a decade.

The above described advances and all the rest of the latest 3DIC happenings can be found in Yole Développement’s new report “3DIC & 2.5D TSV Interconnect for Advanced Packaging – 2014 Business Update”. More information on www.i-micronews.com, advanced packaging reports section.

Slideshow: IEDM 2014 Preview


November 26, 2014

This year, the IEEE International Electron Devices Meeting (IEDM) celebrates 60 years of reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. In 2014 there is an increased emphasis on circuit and process technology interaction, energy harvesting, bio-snesors and bioMEMS, power devices, magnetics and spintronics, two dimensional electronics and devices for non-Boolean computing.

Solid State Technology will be reporting insights from bloggers and industry partners during the conference, and this slideshow provides an advance look at some of the most newsworthy topics and papers to be presented at the annual meeting, to be held at the Hilton San Francisco Union Square Hotel from December 15-17, 2014.

Click here to launch slideshow. 

Bay Bridge, San Francisco at dusk

 

Related news and blogs: 

Intel and IBM to lay out 14nm FinFET strategies on competing substrates at IEDM 2014

Slideshow: IEDM 2013 Highlights

“The long term growth of the equipment & materials business will be supported by the expansion of 3D TSV stack platforms,” says Yole (Yole Développement) in its latest report, “Equipment & Materials for 3DIC & WLP Applications“. The market research and strategy consulting company, Yole proposes a deep analysis of the equipment & materials market for 3DIC & WLP applications. Under this new report, analysts announce a market multiplied by 2.5 in the next 5 years.

“Mainly supported today by flip-chip wafer bumping, the equipment market generated revenue of more than $930M in 2013,” said Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing, Yole. “It is expected that this equipment market revenue will peak at almost $2.5B”, she added.

Equipment & Materials for 3DIC & WLP Applications report presents an overview of the main equipment and materials used in the 3D & WLP applications. Under this technology & market analysis, Yole’s analysts describe insights on a number of equipment tools, breakdown by wafer size & revenue, by type of equipment & materials and advanced packaging applications. Moreover, they also provide a detailed analysis dedicated to key suppliers, market shares and technological highlights that impact the 3D & WLP industry. Equipment & materials market forecasts are calculated from 2013 to 2019.

This market is fueled by the 3D IC technology with TSV interconnects, an area offering opportunities for new developments in equipment modification— equipment that is much more expensive than the tools used for established Advanced Packaging platforms :3D WLP, WLCSP and flip-chip wafer bumping. Indeed, according to Yole, 2015 will be the key turning point for the adoption of 3D TSV Stacks since the memory manufacturers, such as Samsung, SK Hynix, Micron, have already started to ship prototypes this year and might be ready to enter in high-volume manufacturing next year.

In its latest announcement (Source: Song Jung-a, Financial Times), Samsung Electronics reveals its $14.7 billion investment, to build a new semiconductor plant in South Korea. This investment becomes the biggest single expenditure on a memory chip factory.

“The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%”

According to the Korean company, construction of the world’s biggest plant will begin in the first half of next year and complete in the second half of 2017. In addition, logic manufacturers will diversify investments from System-on-Chip to Package-on-Package and will benefit from Advanced Packaging platforms such as 2.5D interposer and FOWLP to stimulate their high-volume production.

From the materials side, Yole confirmed: “The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.”

Growth will mainly be driven by the expansion of the next generation Wafer-Level-Packaging platforms: 3D TSV stacked memories, multi-layer RDL for FOWLP & WLCSP. Such platforms are becoming more complex and requiring additional and various thin layers, as well as advanced materials, to achieve better performance.