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The Semiconductor Industry Association (SIA) today announced that the SIA board of directors has elected Brian Krzanich, CEO of Intel, as its 2015 chairman and Dr. Necip Sayiner, president, CEO and director of Intersil, as its 2015 vice chairman.

“We are excited to welcome Brian Krzanich as SIA’s 2015 chairman,” said Brian Toohey, SIA president and CEO. “His exceptional understanding of semiconductor issues and extensive industry experience make him uniquely qualified to help tackle our industry’s challenges and lead us into the future. We appreciate his many achievements and look forward to his leadership in 2015 as SIA chairman.”

Krzanich became the CEO of Intel in May 2013. He has progressed through a series of technical and leadership roles at Intel, most recently serving as the COO since January 2012. As COO, his responsibilities included leading an organization of more than 50,000 employees spanning Intel’s Technology and Manufacturing Group, Intel Custom Foundry, supply chain operations, the NAND Solutions group, human resources, information technology and Intel’s China strategy. Prior to becoming COO, Krzanich held senior leadership positions within Intel’s manufacturing organization. Krzanich began his career at Intel in 1982 in New Mexico as a process engineer.

“On the cusp of innovations such as the Internet of Things, wearable devices and smart cities, the U.S. semiconductor industry is poised for growth,” said Krzanich. “I look forward to collaborating with colleagues and policymakers to ensure that our industry reaches its full potential, continues to create jobs and keeps America at the forefront of technological advancement.”

Dr. Sayiner joined Intersil as president, CEO and director in March 2013. Prior to joining Intersil, he served as president, CEO and director of Silicon Laboratories from September 2005 to April 2012. Previously, Sayiner held various leadership positions at Agere Systems Inc., which included Executive Vice President and General Manager, Enterprise and Networking Division from August 2004 to September 2005; and Vice President and General Manager, Networking ICs Division from March 2002 to August 2004.

“Necip Sayiner has extensive industry experience and a strong technical background,” Toohey said. “His skills and leadership will be a tremendous asset to our association as we work to enact pro-innovation policies and build a stronger semiconductor industry in the U.S. We welcome him as 2015 SIA vice chairman.”

“I’m pleased to be supporting the SIA as vice chairman and helping to drive awareness of the importance of the semiconductor industry to our nation’s economic health,” said Sayiner. “Now more than ever, it is vital that we fight for government policies that promote growth and competitiveness.”

Nine of the Top 20 Semiconductor Suppliers are Forecast to Register Double-Digit Growth in 2014

Later this month, IC Insights’ November Update to The 2014 McClean Report will show a forecast ranking of the 2014 top 25 semiconductor suppliers with the companies’ sales broken down on a quarterly basis.  A preview of the forecast for the top 20 companies’ total 2014 sales results is presented in Figure 1.  The top 20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 2014 includes eight suppliers headquartered in the U.S., three in Japan, three in Europe, three in Taiwan, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

This year’s top-20 ranking includes two pure-play foundries (TSMC and UMC) and six fabless companies.  Pure-play IC foundry GlobalFoundries is forecast to be replaced in this year’s top 20 ranking by fabless IC supplier Nvidia.  It is interesting to note that the top four semiconductor suppliers all have different business models.  Intel is essentially a pure-play IDM, Samsung a vertically integrated IC supplier, TSMC a pure-play foundry, and Qualcomm a fabless company.

IC foundries are included in the top 20 ranking because IC Insights has always viewed the ranking as a top supplier list, not as a marketshare ranking, and realizes that in some cases semiconductor sales are double counted.  With many of IC Insights’ clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  Foundries and fabless companies are clearly identified in Figure 1.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

As shown, it is expected to require total semiconductor sales of over $4.2 billion to make the 2014 top 20 ranking. In total, the top 20 semiconductor companies’ sales are forecast to increase by 9 percent this year as compared to 2013. However, when excluding the two pure-play foundries (TSMC and UMC) from the ranking, the top “18” semiconductor companies’ sales are forecast to increase by 8 percent this year, the same rate as IC Insights’ current forecast for total 2014 worldwide semiconductor market growth.

 

Fig. 1

Outside of the top six spots, there are numerous changes expected within the 2014 top-20 semiconductor supplier ranking.  In fact, of the 14 companies ranked 7th through 20th, 10 of them are forecast to change positions in 2014 as compared with 2013 (with NXP expected to jump up two spots).

More details on the forecasted 2014 top 25 semiconductor suppliers will be provided in the November Update to The McClean Report.

Texas Instruments Incorporated (TI) today announced it will expand its manufacturing capacity in Chengdu, China, with a 300mm wafer bumping facility. The addition of this manufacturing process in Chengdu further increases TI’s 300mm analog capacity and its ability to support customer demand.

TI announced the new operation today in concert with an event celebrating the grand opening of its seventh assembly/test (A/T) facility. The 358,000 square-foot A/T facility was purchased from UTAC Chengdu Ltd. in December 2013 and is now qualified and in production using advanced quad-flat no-leads (QFN) packaging technology.

TI’s manufacturing investment in China began in 2010 with the opening of the company’s first wafer fabrication plant in Chengdu. TI extended its investment with the adjacent A/T facility, opening today. TI will now further extend its operations in Chengdu with a 300mm wafer bumping facility on its Chengdu High-tech Zone (CDHT) campus.

“The CDHT has been a dynamic area of economic development in West China, offering a strong environment for investment and government service,” said Kevin Ritchie, senior vice president of TI’s Technology & Manufacturing Group. “We’re pleased to extend our 300mm manufacturing capabilities at our world-class Chengdu facility to further ensure continuity of supply to our customers and support their growth.”

Wafer bumping is a manufacturing process for advanced packaging technologies, which is completed prior to assembly. The process replaces wire bonding as the interconnection by applying solder, in the form of bumps, or balls, to a device at the wafer level. Nearly 40 percent of TI’s wafer production is manufactured using bump techniques.

This investment plan does not change TI’s capital spending forecast. The company continues to expect its capital spending levels to remain about 4 percent of revenue.

TI has served a broad array of customers in China for more than 27 years. In addition to its manufacturing footprint in Chengdu, TI has established 18 offices providing sales and applications support, four R&D centers and a product distribution center in Shanghai.

TI has manufacturing operations throughout the world, including the United States, Mexico, Germany, Scotland, China, Malaysia, Japan, Taiwan and the Philippines. Its 300mm operations include the industry’s first 300mm Analog wafer fab in Richardson, Texas as well as its DMOS6 wafer fab in Dallas and bump operations in the Philippines and Dallas.

Capped by last week’s announcement that Qualcomm Inc. would buy CSR PLC, the automotive semiconductor industry recently has been undergoing a wave of merger and acquisition (M&A) activity that has shaken up the competitive order of the market, according to IHS Technology.

In two major deals announced in August, Germany’s Infineon Technologies AG said it would acquire U.S.-based International Rectifier Corp., while ON Semiconductor Corp. sealed a deal to acquire fellow American firm Aptina Imaging Corp.

With the International Rectifier deal, Infineon bolstered its No. 2 rank in the global automotive semiconductor business and helped it to close the gap on the market leader, Renesas of Japan. Following the acquisition, Infineon trails Renesas by just $288 million, down from nearly $500 before Infineon bought International Rectifier, based on ranking data from 2013.

Meanwhile, the Aptina acquisition expanded ON’s automotive semiconductor revenue by $183 million, allowing ON to move up one position to eighth place in the market, also based on 2013 ranking data.

The purchase of the U.K.’s CSR will allow California-based Qualcomm to enhance its market share. Qualcomm ranked No. 43 in 2013, while CSR came in at 23. The two companies combined would have ranked at No. 19 in 2013.

“While these three M&A deals differ in their specific goals and benefits, all have the same strategic objective: expanding market share in the lucrative business for semiconductors used in automobiles,” said Ahad Buksh, analyst for automotive semiconductors at IHS. “The automotive supply is adding new infotainment, communications and driver-assist functionality at a rapid pace, causing related semiconductor revenue to rise 5 percent to reach $26 billion in 2013. Suppliers are buying up competitors to gain scale in the market, to add key capabilities and to capitalize on established customer relationships.”

Clash of the top 10 titans

The figure below presents the IHS ranking of the world’s top 10 suppliers of automotive semiconductors in 2013, showing the impact from the recent acquisitions.

Auto_Semi_in_Cars

All of these 10 companies increasingly are investing in automotive, having identified the area as a strategic field of expansion. At the same time, most of these companies are divesting from other markets, such as wireless and consumer electronics.

The strong positions held by the top 10 suppliers are the result of decades of investment to meet the specific requirements of leading customers. These requirements include high product quality and strong service support. IHS believes that automotive manufacturers will tend to maintain long-term relationship with these established semiconductor suppliers.

To Infineon and beyond

Infineon’s acquisition of International Rectifier not only will diversify the former’s product portfolio but also will make it a bigger threat to Renesas.

Last year was great for both Infineon and International Rectifier, with automotive-related revenue at the two companies rising by 11.7 percent and 15.6 percent, respectively. In contrast, the declining exchange rate of Japanese yen vs. the U.S. dollar meant that Renesas suffered a 14.2 percent drop in automotive revenue in 2013. What used to be a lead of more than $1.2 billion for Renesas over Infineon in 2012 eroded by 60 percent.

Once the International Rectifier acquisition is complete, Renesas’ lead will shrink further.

International Rectifier’s strong presence in low-power insulated-gate bipolar transistor (IGBT), power modules and power metal–oxide–semiconductor field-effect transistor (MOSFET) will boost Infineon into the top spot in the discrete integrated circuit (IC) category. This particularly reinforces Infineon’s position in the fast growing hybrid and electric vehicle segment. Intelligent power switches, data converters and application-specific integrated circuits (ASIC) from International Rectifier also will complement Infineon’s portfolio and will generate economies of scale. Even though Infineon’s second position in analog ICs won’t change, the acquisition will help it close in on the top player in the segment, STMicroelectronics.

On the acquisition hunt

Aside from bringing ON Semiconductor closer to the $1 billion mark in automotive semiconductors, Aptina’s sensor business is of strategic importance, as it was a weak spot in On’s portfolio. Now, ON Semiconductor can count itself the leading supplier of complementary-metal-oxide semiconductor (CMOS) imaging sensors, which serve as the eyes of advanced driver assistance systems (ADAS) in vehicles. The rapid adoption of ADAS will drive markets for automotive image sensors to attain 10 percent growth per year from 2013 to 2020, making it a good investment for On.

Qualcomm boosts automotive market share with CSR acquisition

Qualcomm’s acquisition of CSR is more about buying—and as a result, enlarging—market share in automotive than about complementing Qualcomm’s product portfolio.

With the purchase, Qualcomm will become the world’s fourth-largest supplier of ASICs for automotive infotainment, with a 10 percent market share. In 2013, the company ranked 11th with a market share of 2.7 percent, unchanged from 2012 and 2011.

IBM and GLOBALFOUNDRIES today announced that GLOBALFOUNDRIES will acquire IBM’s global commercial semiconductor technology business, including IBM’s intellectual property, technologists and technologies.

IBM will pay GLOBALFOUNDRIES $1.5 billion in cash over the next three years to take the chip operations off its hands. The cash consideration will be adjusted by the amount of working capital which is estimated to be $200 million.

Workers prep Global Foundries' newest semiconductor factory, "Fab 8" in Saratoga County, New York State Source: IBM

Workers prep Global Foundries’ newest semiconductor factory, “Fab 8” in Saratoga County, New York State. Source: IBM

GLOBALFOUNDRIES will also become IBM’s exclusive server processor semiconductor technology provider for 22nm, 14nm and 10nm semiconductors for the next 10 years.

It its official statement, IBM said the agreement will enable the company to further focus on fundamental semiconductor research and the development of future cloud, mobile, big data analytics, and secure transaction-optimized systems. IBM will continue its previously announced $3 billion investment over five years for semiconductor technology research to lead in the next generation of computing. GLOBALFOUNDRIES will have primary access to the research that results from this investment through joint collaboration at the Colleges of Nanoscale Science and Engineering (CNSE), SUNY Polytechnic Institute, in Albany, N.Y.

Through the acquisition, GLOBALFOUNDRIES will gain substantial intellectual property including thousands of patents, making GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.

GLOBALFOUNDRIES will acquire and operate existing IBM semiconductor manufacturing operations and facilities in East Fishkill, New York and Essex Junction, Vermont, adding capacity to serve its customers and thousands of jobs to GLOBALFOUNDRIES’ workforce. GLOBALFOUNDRIES plans to provide employment opportunities for substantially all IBM employees at the two facilities who are part of the transferred businesses, except for a team of semiconductor server group employees who will remain with IBM. After the close of this transaction, GLOBALFOUNDRIES will be the largest semiconductor technology manufacturing employer in the Northeast.

GLOBALFOUNDRIES will also acquire IBM’s commercial microelectronics business, which includes ASIC and specialty foundry, manufacturing and related operations and sales. GLOBALFOUNDRIES plans to invest to grow these businesses.

IBM took a related pre-tax charge of $4.7 billion in its third quarter. It also reported a 4 percent drop in revenue on Monday.

What the analysts are saying

In terms of its 14nm FinFET collaboration with Samsung, the acquisition and the sudden influx of top talent from IBM will certainly help get GLOBALFOUNDRIES up to speed, Robert Maire of Semiconductor Advisors LLC reported.

“Even though Samsung still holds the keys and most of the cards in their relationship, the addition of the IBM horsepower does help even things a little bit even though IBM hasn’t been a serious player in the semiconductor business for quite a while it still has a deep well of expertise,” said Mr. Maire.

Currently, analysts at Summit Research Partners are not concerned about the long-term financial impact of the acquisition.

“We think that at present, when the transfer of IBM’s chip manufacturing assets to GLOBALFOUNDRIES is done, this is a non-event to the semiconductor industry for the most part,”  said Srini Sundararajan, Semiconductor, Semi-cap Equipment Analyst at Summit Research Partners. “That is sad considering that there were times in the 90s that IBM and Intel competed with one another over bragging rights for technological advancements.”

“In terms of potential impact to semiconductor equipment companies, there would likely be minimal to no impact as potential capex spend would be absorbed within the capex spend of Global Foundries,” Mr. Sundararajan concluded.

By Bettina Weiss, VP, Business Development, SEMI

The 2nd annual SEMI Vietnam Semiconductor Strategy Summit, co-organized with the Saigon Hi-Tech Park and with FabMax as the premier sponsor, was held September 16-17, 2014 in Ho Chi Minh City. This year’s conference drew over 160 attendees from Vietnam, Europe, U.S. and other Southeast Asian countries for a full day of presentations, panel discussions, networking opportunities and interactions with government, the Ho Chi Minh City Semiconductor Industry Association (HSIA) and the Saigon Hi-Tech Park (SHTP).

Fig 1

 

Building on the success of the inaugural Summit in September of 2013, attendees and speakers commented on the sense of progress and growing vitality of the emerging semiconductor manufacturing ecosystem in Vietnam. In his welcome remarks, Kai Fai Ng, president, SEMI Southeast Asia spoke to the importance of Vietnam in Southeast Asia, and SEMI’s plans to facilitate business interactions between Vietnamese and Southeast Asian companies, support efforts in workforce development and education, and continue to strengthen the relationship with key stakeholders in the country.

Of particular interest to the audience was the keynote presentation by Dr. Pham Ba Tuan, senior expert at CNS, the company tasked with executing the 200mm fab project in Saigon Hi-Tech Park that was announced last year. Tuan stressed the importance of domestically manufactured devices to satisfy a rapidly growing need in Vietnam thanks to the country’s young population and high university graduation rates. Tuan indicated that, depending on the product choice and the cost structure of the new wafer fab, at least 5,000 wafer starts per months would be needed. Fab capacity would be a function of product mix, so wafer starts need to be adjustable from 5,000 to 10,000 wafer starts per month. This would necessitate an investment of “a few million USD” to enable equipment purchases, fab construction and infrastructure readiness.

Source: Saigon Industry Corporation (CNS)

Source: Saigon Industry Corporation (CNS)

Tuan emphasized the fact that the choice of technology was a crucial factor for the wafer fab, since it influences investment volume, product portfolio, as well as the ability to develop a skilled workforce throughout the manufacturing process. The choice for the wafer fab in Saigon Hi-Tech Park is 180nm on 200mm wafers, a node and substrate size choice that will enable the production of a wide variety of products. According to CNS, revenue from all products made in technologies down to 180nm already account for US$1 billion.

Fig 3

The project timeline presented at the SEMI conference shows construction to begin in Q3 2015 and equipment move-in starting in Q2 2016.

Fig 4

The CNS presentation was followed by a brief company introduction to NXP delivered by Mr. Frederic Vincentini.

Kicking of the second session on Semiconductor Manufacturing in Vietnam, Ms. Sherry Boger, general manager, Intel Vietnam, provided an update on Intel’s plans to extend the production of flagship products to Vietnam — such as the Haswell microprocessor, which was recently announced. Intel’s Vietnam facility is the largest assembly and test facility in the global Intel network, employing over 3,000 Vietnamese employees when fully ramped.

Fab-Finder’s Todd Curtis shared his company’s learning experiences when they started doing business in Vietnam. He stated that the Fab-Finder management team brought over 100 years of semiconductor experience to the table — but 0 years in this country, making it imperative to rapidly get up to speed with respect to laws and taxes, cultural differences and sensitivities and different business practices. Mr. Curtis made a point of thanking his Vietnamese business partners, legal and tax advisors, HSIA and the Saigon Hi-Tech Park for the education they provided.

Prof. Cor Claeys of Imec presented Imec’s Open Innovation Model. Given the ever shrinking features, the complexity of new devices and applications and the rising cost in R&D, Claeys stressed the need for collaborative efforts in the semiconductor industry in order to keep up with the increasing need and speed of innovation.

Open Innovation

Source: Samsung

Source: Samsung

Contrasting Imec’s Open Innovation model with the traditional R&D approach – where most of the R&D is done in-house, no IP is shared and projects occur in silos –Claeys emphasized the need to share risk, cost, talent and IP among R&D partners in order to jointly reap the benefits of an accelerated, cost-effective RD activity.

This discussion provided a nice introduction into two presentations in the afternoon addressing technology transfers, IP creation and protection. Ms. Radhika Snirivasan, Ph.D., from IBM talked about the process by which technology transfers occur, and how opportunities and risks can be managed. Snirivasan described technology transfers as “quintessential” to any technology installation and shared IBM’s methodology, from preparation and training through installation and debug, qualification and yield learning to product qualification and ramp. She pointed to the added value when IP transfers are managed in highly customizable and flexible scenarios, providing protection and safeguards against risks such as the transfer infrastructure, adequacy of documentation and lack of technology readiness/maturity.

Fig 6

Dr. John Schmitz of NXP elaborated on the subject by presenting NXP’s view on the growing importance of Intellectual Property Rights (IPRs) since knowledge has become a critical driver in the economy. “IPRs are the economical manifestation of technical and business knowledge,” said Schmitz, stressing that IPRs provide a mechanism of protection against misuse. Speaking to current and future patent portfolios, he stated the requirement for future patents to be aligned with the overall company strategy, but stressed the inherent risk of having to look at least 5 years ahead — a mandate he contrasted with the product lifecycle of mobile phones, which is currently about 6 months.

The last formal presentation of the day was M+W Group’s “Integrated Approach for Semiconductor Wafer Fab Implementation,” presented by Mr. Andreas Authenrieth, M+W Group. His presentation focused on the prerequisites for a sustainable and cost-effective fab design, with particular emphasis on energy efficiency, environmental technology and the use of renewable energy. Authenrieth also included the use of secondary equipment in his presentation, explaining the importance of correlating tool specifications with technology requirements, paying close attention to consumables and spares and managing equipment testing and documentation. These considerations could be of particular importance for the CNS wafer fab project.

The 2nd annual SEMI Vietnam Semiconductor Strategy Summit concluded with two panel discussions: The first panel – investing and operating in the technology sector in Vietnam – was moderated by Eduard Hoeberichts, FabMax and included two presentations which addressed both the side of the operator and the side of the government. Johnny Choo of ON Semiconductor shared the experience as an operator of two back-end facilities in Vietnam and highlighted the very positive experience over the last several years as well as some of the areas for potential improvement.

This perspective was consistent with the observations that Sherry Boger of Intel made in the morning presentation. Dr. Le Hoai Quoc as president of Saigon High Tech Park presented the capabilities of the High Tech Park as well as the general government support in various areas for operators and new investors in Vietnam. The “two sides of the coin” perspective led to a lively discussion at the end of the panel session.

Fig 7

 

The second panel – Education and Workforce Development – was moderated by Ms. Bettina Weiss, SEMI, and included: Ms. Sherry Boger, Intel Vietnam; Dr. Carel von der Poel, Technical University Delft; Dr. Pham Ba Tuan, CNS; and Cao Nguyen, ON Semiconductor. The importance of developing a skilled talent pool in Vietnam was also a prominent topic in SEMI’s 2013 Vietnam Semiconductor Strategy Summit. Panelists engaged in a lively debate about the need to do more for women in high tech, partnerships with international universities and special programs like HEEAP (Higher Engineering Education Alliance Program) which Intel is very actively supporting, as well as the Technical University Delft/DIMES Center, which has been engaged with Vietnam’s Hanoi University of Technology, Hanoi University of Civil Engineering and the Ministry of Science and Technology in various programs. According to Dr. van der Poel, it would be fairly easy to extend these programs to the semiconductor space, as Vietnam starts focusing on workforce readiness in this sector.

At the networking reception, attendees and speakers alike commented on the sense of progress and excitement over the last 12 months. Local attendees in particular appreciated the rich presentations and perspectives from the conference speakers, and international companies, including our sponsors, left with a lot of new contacts and business opportunities in country — and the sense that Vietnam is very serious about becoming a stakeholder in the global semiconductor market.

SEMI is grateful for the support of the sponsoring companies who helped make this year’s Summit possible:  FabMax, CNS, M+W Group, Advantest, Fab-Finder, GES, Lam Research, NXP, QAM, and Surplus Global.

Specifications of reed relays, which are used for current switching in ATE and other applications are explained, including carry current, lifetime, minimum switch capacity, hot switching, operating speed and thermoelectric switching.

BY KEVIN MALLETT, Pickering Electronics, Clacton-on-Sea, Essex, U.K.

Reed relays, which use an electromagnet to control one or more reed switches without requiring an armature, are used for instrumentation and automatic test equipment (ATE), high voltage switching, low thermal EMF, direct drive from CMOS, RF switching and other specialized applications.

Reed relays are deceptively simple devices in principle. They contain a reed switch, a coil for creating a magnetic field, an optional diode for handling back EMF from the coil, a package and a method of connecting to the reed switch and the coil to outside of the package. The reed switch is itself a simple device in principle and relatively low cost to manufacture thanks to modern manufacturing technology.

The reed switch has two shaped metal blades made of a ferromagnetic material (roughly 50:50 nickel iron) and glass envelope that serves to both hold the metal blades in place and to provide a hermetic seal that prevents any contaminants entering the critical contact areas inside the glass envelope. Most (but not all) reed switches have open contacts in their normal state.

If a magnetic field is applied along the axis of the reed blades the field is intensified in the reed blades because of their ferromagnetic nature, the open contacts of the reed blades are attracted to each other and the blades deflect to close the gap. With enough applied field the blades make contact and electrical contact is made.

The only movable part in the reed switch is the deflection of the blades, there are no pivot points or materials trying to slide past each other. The reed switch is considered to have no moving parts, and that means there are no parts that mechanically wear. The contact area is enclosed in a hermetically sealed envelope with inert gasses, or in the case of high voltage switches a vacuum, so the switch area is sealed against external contamination. This gives the reed switch an exceptionally long mechanical life

Inevitably in practice the issues are a little more complicated. The ferromagnetic material is not a good conductor and in particular the material does not make a good switch contact. So the reed blades have to have a precious metal cover in the contact area, the precious metal may not stick to the blade material very well so an underlying metal barrier may be required to ensure good adherence. Some types of reed relay use mercury wetted contacts, consequently reed relays that use plated contacts are often referred to as “dry” reed relays. The metals can be added by selective plating or by sputtering processes. Where the reed blade passes through the glass envelope any plating (in many cases there may be none) requires controlling to avoid adversely affecting the glass to metal hermetic seal. Outside the glass seal the reed blades have to be suitably finished to allow them to be soldered or welded into the reed relay package, usually requiring a different plating finish to that used inside the glass envelope.

The materials used for the precious metal contact areas inside the glass envelope have a significant impact on the reed switch (and therefore the relay) characteristics. Some materials have excellent contact resistance stability; others resist the mechanical erosion that occurs during hot switch events. Commonly used materials are ruthenium, rhodium and iridium– all of which are in the relatively rare platinum precious metal group. Tungsten is often used for high power or high voltage reed switches due to its high melting point. The material for the contact is chosen to best suit the target performance – bearing in mind the material chosen can also have a significant impact on manufacturing cost. Sealed in a long, narrow glass tube, the contacts are protected from corrosion, and are usually plated with silver, which has very low resistivity but is prone to corrosion when exposed, rather than corrosion-resistant but more resistive gold as used in the exposed contacts of high quality relays. The glass envelope may contain multiple reed switches or multiple reed switches can be inserted into a single bobbin and actuate simultaneously. As the moving parts are small and lightweight, reed relays can switch much faster than relays with armatures. They are mechanically simple, making for reliability and long life.

This article reviews and explains common specifications used for reed relays (FIGURE 1).

FIGURE 1. Reed relays are used for current switching in ATE and other applications.

FIGURE 1. Reed relays are used for current switching in ATE and other applications.

Carry current

Carry current is the current that the reed relay can support through its contact without long term damage. The life of the relay should be indefinite under this condition though some reed relays may also have a pulse current rating which can be applied to the relay without damage.

The carry current is determined primarily by the contact resistance of the relay and the heat sinking to the environment. As the current increases the temperature of the reed blades increases until it reaches a temperature where the material is no longer ferromagnetic (Curie Temperature). Once that temperature is reached the relay contacts may open since the blades no longer respond to the magnetic field. The blade temper- ature is clearly dependent upon the current and relay path resistance – the normal assumption is that this is a square law (with current) relationship. In reality, the temperature rise is significantly more than a square law since the metallic resistance also increases with temperature, the magnetic field drops with temperature because of coil resistance rise and the mechanical properties of the blade can change. Consequently like all relays, exceeding the rating can result in a type of thermal runaway.

The packaging of the reed switch has a significant impact on the temperature rise, a lead frame tends to conduct heat to the outside world while the plastic encapsulation materials insulate it. The packaged reed relay will always have a lower current rating than that of the reed switch because manufacturers quote the rating with the reed switch directly exposed (no coil, no plastic packaging). The coil power will also add to the heating effect. Consequently Pickering Electronics always de-rates the reed relay ratings to ensure that the relay switch remains within its design limits.

There is also another subtle effect that occurs as the carry current increases – the signal creates its own magnetic field that twists the blades and therefore can modulate the contact resistance. The blade twisting may start to see a contact resistance rise as the blade contact area reduces or changes.

Care must be taken not to exceed the relays ratings and pulse ratings should take account of the square law relationship between current and temperature.

It becomes difficult to manufacture reed relays with a carry current of greater than 2A because the contact area has to be increased and that tends to make the bladed stiffer and require a higher magnetic field strength to operate them.

Lifetime

The lifetime of reed relays is critically dependent on the load conditions the reed switch encounters. For reed relays which are instrument grade the mechanical lifetime is much greater than 1 billion operations – they are mechanically simple devices that rely purely on the deflection of a blade to operate and there are conse- quently fewer wear out mechanisms.

The blade contact area though stills wears as they are opened and closed. If the signal load when the blade closes or opens is low then the wear out is very slow, as the load increases and hot switching (interruption or closure of a signal live carrying significant current or voltage) occurs higher temperatures are generated at the contact interface and this makes the materials more prone to wear. DC signals can also result in the migration of metal from one contact to another and without regular polarity reversal eventually the underlying contact materials are exposed with their poorer conduction characteristics. Hot switching can also create a temporary plasma in the contact area with high local temperatures, rapid operation of a relay under load can start to raise the contacts temperature to an extent where premature wear out can occur. The life an instrument grade reed relay can vary by three orders of magnitude according to the load conditions, perhaps 5 billion operations under no or light load to 5 million operations at a heavy load.

Minimum switch capacity

Some types of relay have a minimum switch capacity, if the relay is closed on a very low level signal (current or voltage) oxide or debris on the relay contacts can remain at the interface and cause a higher than expected resistance, or even an open circuit. This tends not to be the case with reed relays because the precious metal contacts are sealed in a hermetic glass envelope containing inert gas. Minimum switch capacity tends to be a characteristic of higher power mechanical (EMR) relays.

Hot switching

Hot switching occurs whenever a relay contact is opened or closed with a signal (current and voltage) is present. As the contacts move apart or close an arc can be created which transfers material from one contact to another, or simply redistributing the material. As the contact plating is damaged the resistance will eventually start to rise until the relay is no longer fit for the intended application.

For reed relays hot switching tests are always conducted into resistive loads. The hot switch capacity of a reed relay is typically quoted at a current/voltage that results in the number of operations that the relay will support around 10million operations. The data sheet specifies a hot switch current (the limiting factor at low voltages), a hot switch voltage (limiting factor at low current) and a power (from the product of the open contact voltage and the closed contact current).

Operating speed

The operate time is the time from when the relay coil is energized or de-energized to when the contact reaches a stable position.

For a normally open contact when the coil is energized the current, and therefore the magnetic
field, in the coil rises until the blades start to move closer together until they make contact. The contacts may impact each other sufficiently rapidly that there is bounce where for a short duration the contact is inter- mittently closed then opened. The operate time should be the time from when the relay coil was energized until the contacts are stably closed.

If the coil is driven from a higher than specified coil voltage the closing speed of the relay will be faster, however once the contacts make there may be more contact bounce as they meet with greater force. Overdriving the coil can also increase the release time since the magnetic field takes longer to collapse to the point where the contacts start to open.

For a normally open Form A (SPST) contact the release time is the time from when the coil is de-energised to when the contact is open. This operate time can be dependent on how the reed relay is driven, the presence of a protection diode on the coil will increase the release time. Typically, the release time is around one half the operate time.

Soft and hard weld failures

Operation of reed relays (or EMRs) under high load conditions causes one of the most common failure mechanisms for relays – a failure where the contacts are welded together. By convention these welds are classified as being either soft or hard failures. In the event of hard failure the contacts tend to be welded together and nothing will separate them. This is an easy fault to identify. Soft failures occur where the contacts sick but eventually come apart without any additional assistance. The failure is caused by small areas on the contact welding together, but the weld area is sufficiently small that the reed blades will separate because of their sprung nature. They could spring apart very quickly, or it may take several seconds to spring apart depending on how hard the weld is.

In either case the impact on the user is that the switching function of the relay is impaired and this is likely to have an adverse impact on the user application. So in either case the relay will require replacing since the defect is unlikely to improve with time. The cause of the weld will also need to be investigated and corrected.

Thermoelectric EMF

The cause of thermoelectric voltages is often misunderstood by users, and often misrepresented in articles and on the internet. The effect of thermoelectric EMF’s is to generate a small voltage (measured in microvolts) across the relay terminals when the relay is closed (FIGURE 2).

FIGURE 2. Thermoelectric EMF’s are used to generate a small voltage (measured in microvolts) across the relay terminals when the relay is closed.

FIGURE 2. Thermoelectric EMF’s are used to generate a small voltage (measured in microvolts) across the relay terminals when the relay is closed.

The voltage arises whenever a metal wire has a temperature gradient across it (the Seebeck Effect), if one end of the wire is at a different temperature to the other then a voltage will appear which is dependent on the temperature difference and the materials that make up the wire. Reed relays use a mix of metals, and these can have different temperature drops across them which results in a voltage appearing at the relay connection terminals. The voltage is not created at a connection junction. Nickel iron has quite a strong thermoelectric EMF, so designing reed relays with low thermal EMF’s can be a challenge.

The number and type of materials varies according to FIGURE 2. Thermoelectric EMF’s are used to generate a small voltage (measured in microvolts) across the relay terminals when the relay is closed. to the way the reed switch is designed and how it is packaged. If the relay was perfectly symmetric in construction (so the materials used from each contact to the reed switch were the same and the reed itself was perfectly symmetric in all materials and dimensions) and all heat sources in the relay body (primarily due to the coil) then this would be the case. However in reality the symmetry is not perfect so a residual voltage will arise.

Users can also degrade the performance by how they use the relay. When mounted on a PCB if the PCB has a temperature profile across it then that will generate an additional thermal EMF. Relay manufacturers usually assume that the thermal EMF is zero when the relay is first closed since up to that point no heat source exists inside the relay body. However, a temperature profile across the PCB (caused by the presence of other heat sources or forced air cooling) will create a thermal EMF.

Reed relays that have excellent Thermal EMF performance are typically designed to be as symmetric in design as possible and to use highly efficient coils to avoid heating the reed switch. Typically though, this results in a physically larger relay.

Two pole designs often quote the Differential Thermal EMF, this is the voltage generated between the two switches (usually) in a single package.

Assuming the relay design is reasonably symmetrical to a first order the voltage in one switch is the same as the other, so the differential voltage can be much smaller for the relay. Differential and single ended Thermo Electric EMF numbers should not be directly compared or confused with each other.

India has a very large industry base of electronics items, but there is little manufacturing base for semiconductors. As of now India doesn’t have any operational wafer fabrication plants and depends extensively on the imports. Semiconductor industry is 100 percent import based with India importing semiconductors worth $10 billion in 2013. Since In 2013, India spent $169 billion on oil imports, $54 billion on gold imports and $31.5 billion on electronic imports.

Semiconductors are used extensively in various applications, which offer immense potential for the growth of this industry in India.  Semiconductors are used majorly in Mobile Devices, Telecommunications, Information Technology & Office Automation (IT & OA), Industrial, Automotive and other industries (Aerospace, Defense and Medical industries).

The latest research report by NOVONOUS finds that the semiconductor industry is estimated to grow from $10.02 billion in 2013 to $52.58 billion in 2020 at CAGR of 26.72 percent.

According to this research report, mobile devices are expected to grow at CAGR of 33.4 percent from 2013 to 2020. The contribution to semiconductor revenue is expected to grow from 35.4 percent in 2013 to 50.7 percent in 2020.

Telecommunication segment is expected to grow at CAGR of 26.8 percent from 2013 to 2020 and its contribution to total revenue will remain the same at 19.7 percent in 2020.

IT&OA contribution to the total semiconductor revenue will come down from 28.3 percent in 2013 to 17.4 percent in 2020 due to consolidation in this sector. This segment will grow at CAGR of 18.2 percent over the next seven years.

Consumer electronics segment is expected to grow at CAGR of 18.8 percent and the contribution to the total semiconductor revenue will come down from the current level of 5.6 percent in 2013 to 3.5 percent in 2020. Industrial electronics segment is expected to grow at CAGR of 19.6 percent and the contribution to the total semiconductor revenue will come down from current level of 4 percent to 2.7 percent.

Automotive electronics segment is expected to grow faster at CAGR of 30.5 percent from 2013 to 2020; its revenue contribution will increase from 3.2 percent in 2013 to 3.9 percent in 2020.

A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described. 

BY NAOMI YOSHIDA, KEPING HAN, MATTHEW BEACH, XINLIANG LU, RAYMOND HUNG, HAO CHEN, WEI TANG, YU LEI, JING ZHOU, MIAO JIN, KUN XU, ANUP PHATAK, SHIYU SUN, SAJJAD HASSAN, SRINIVAS GANDIKOTA, CHORNG-PING CHANG and ADAM BRAND, Applied Materials, Santa Clara, CA 

At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.

In this study, using WFM full fill and combining two techniques — the novel metal composition and ion implantation into the WFM process, we successfully realized three critical aspects for the metal gate for 10 nanometer and beyond. These are: 1) precise effective work function (eWF) control over a 600 millivolt (mV) tuning range to achieve multiple VT, 2) maintaining conductivity for a sub-15 nanometer gate trench, and 3) compatibility to the self-aligned contact (SAC).

A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal compo- sition and beam line ion implantation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage (HFCV) and current voltage (IV) measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability.

Work function modulation

FIGURE 1 shows eWF with three compositions of NMOS WF metals (nWFM) compared with RF-PVD titanium aluminum (TiAl) that was used as the nWFM reference metal. Results demon- strated that the difference between the highest and lowest WF was 550 mV and is attributed to the ALD TiAl composition. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps. This made possible a WF range from near the Si conduction band edge of 4.1 electron volts (eV) for NMOS low VT to above mid-gap 4.7 eV. The WF shift corresponded well to the different dose levels; therefore we demonstrated that ion implantation can be used to pinpoint the target WF. In addition, we found that ion implantation into ALD TiAl does not degrade the gate leakage current and effective oxide thickness (EOT) performance.

FIGURE 1. nWFM composition impact on eWF.

FIGURE 1. nWFM composition impact on eWF.

Maintaining metal gate conductance for 10nm node

According to the ITRS roadmap, a gate length of 17 nanometers is expected for the 10 nanometer technology node [3]. The problem is that after the high-k cap and etch stop depositions, the gate will have limited space left for the metal fill process [4]. One solution is to fully or mostly fill the trench with WF metal. Using an advanced ALD TiAl deposition process, we were able to fill 13 nanometer wide trenches without any gapfill voids. FIGURE 2 shows the extendible conductance of the ALD TiAl and WF fill process.

FIGURE 2. Conductance curves of various metals filling small trenches.

FIGURE 2. Conductance curves of various metals filling small trenches.

It is known that NMOS low WF metals are more prone to oxidization than high WF PMOS films such as titanium nitride (TiN) and that air exposure affects VT control [5]. In our study, degradation on the conductance curves from air exposure was also observed (FIGURE 3). The air exposed sample showed a large offset of the conductance curve to the right while maintaining the slope, i.e. differential resistivity. The TEM (FIGURE 4) shows an additional layer between the TiN barrier and ALD TiAl. Scanning transmission electron microscope- electron energy loss spectroscopy analysis confirmed high oxygen in the white interface. Thus, it is critical to have an in situ ALD TiAl process on the high k TiN cap to maintain conductivity for the 10 nanometer node.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

Self-aligned contact compatibility and CMOS VT tuning

At the 22 nanometer technology node, a metal gate SAC is necessary to scale contacted gate pitch [1]. This requires a well-controlled etch back of the metal gate, with subsequent capping of the etch stop material such as silicon nitride (SiN) to prevent contact to gate shorts. Tungsten (W) has been used in volume production because it offers a robust etch back process. In our study, we demonstrated that a controlled recess etch can be achieved with the more conductive TiAl fill compared to W (FIGURE 5). In addition, after metal etch back, a SAC cap was successfully formed with a high density plasma (HDP) SiN fill and chemical mechanical planarization (CMP).

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

Multiple WF metals need to be integrated for CMOS VT tuning for NMOS and PMOS. In our study we examined the CMOS ALD TiAl flow for four VT tunings. From the results, we propose a new process flow: 1) after the high-k and etch stop layer deposition steps, a fully clustered barrier TiN and nWFM be deposited. Some areas can be masked by photoresist (PR) and the exposed area modified by ion implantation. 2) Etch off the first nWF layer from the PMOS areas. 3) Deposit the second WF (N-3) and barrier. 4) Perform second ion implantation to shift the WF of the third device. 5) Lastly, ALD TiAl is again etched off from the PMOS area WFM (TiN), followed by W or Al fill to fill the remaining gap. The last TiN material serves as the highest WF as well as the barrier layer for W or Al. This flow provides four VTs and metal fill with a clustered nWFM film stack.

Conclusion

Metal WF modulation for VT tuning using a new scheme tunable in the range of 600 mV was successfully demonstrated for 10 nanometer CMOS integration. Ion implantation dose control enabled continuous WF tuning for multiple VT targets. Metal gate conductance data showed the benefit of in situ processing with a TiN barrier and NMOS WF metal. Based on the results, a CMOS flow with NMOS WF-first was proposed for multi-VT tuning.

References

1. C. Auth et al., VLSI Tech. Sym. Dig., p. 131, (2012)
2. P. Packan et al., IEDM Tech. Dig., p. 659, (2009)
3. ITRS Roadmap 2011 Edition
4. N. Yoshida, et al., VLSI Tech. Sym. Dig., p. 81, (2012) 5. A. Veloso, et al., VLSI Tech. Sym. Dig., p. 33, (2012)

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the U.S. semiconductor industry in technology or public policy. Daane will accept the award at SIA’s annual award dinner on Thursday, Nov. 13.

“For many years, John Daane has been one of the semiconductor industry’s strongest and most influential leaders,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “John represents the heart and soul of our industry and the glue that has strengthened our association. Throughout his career, John has brought together our industry’s leaders to tackle challenges and advance core industry priorities. His leadership has helped the semiconductor industry create jobs, boost economic growth, and maintain America’s global technology leadership. On behalf of the SIA board of directors, it is a privilege to announce John’s selection as the 2014 Robert N. Noyce Award recipient in recognition of his outstanding accomplishments.”

Daane has served as Altera’s president and CEO since November 2000 and was named chairman of the board in May 2003. Prior to joining Altera, Daane spent 15 years at LSI Logic, a semiconductor manufacturer, most recently as executive vice president, communications products group. Daane earned a Bachelor’s Degree from the University of California, Berkeley.

“I am honored and humbled to be selected by my friends and colleagues to receive this award and to join the company of previous Noyce recipients, individuals who are recognized as some of the semiconductor industry’s greatest pioneers and champions,” said Daane. “Perhaps our industry’s greatest strength is our ability to continuously and relentlessly look forward – to the next great achievement or innovation. It is in that spirit that I gratefully accept this award and look forward to helping build an even stronger semiconductor industry.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.