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IBM announced it is investing $3 billion over the next 5 years in two broad research and early stage development programs to push the limits of chip technology needed to meet the emerging demands of cloud computing and Big Data systems. These investments will push IBM’s semiconductor innovations from today’s breakthroughs into the advanced technology leadership required for the future.

The first research program is aimed at so-called “7 nanometer and beyond” silicon technology that will address serious physical challenges that are threatening current semiconductor scaling techniques and will impede the ability to manufacture such chips. The second is focused on developing alternative technologies for post-silicon era chips using entirely different approaches, which IBM scientists and other experts say are required because of the physical limitations of silicon based semiconductors.

Cloud and big data applications are placing new challenges on systems, just as the underlying chip technology is facing numerous significant physical scaling limits.  Bandwidth to memory, high speed communication and device power consumption are becoming increasingly challenging and critical.

The teams will comprise IBM Research scientists and engineers from Albany and Yorktown, New York; Almaden, California; and Europe. In particular, IBM will be investing significantly in emerging areas of research that are already underway at IBM such as carbon nanoelectronics, silicon photonics, new memory technologies, and architectures that support quantum and cognitive computing.

These teams will focus on providing orders of magnitude improvement in system level performance and energy efficient computing. In addition, IBM will continue to invest in the nanosciences and quantum computing–two areas of fundamental science where IBM has remained a pioneer for over three decades.

7 nanometer technology and beyond
IBM Researchers and other semiconductor experts predict that while challenging, semiconductors show promise to scale from today’s 22 nanometers down to 14 and then 10 nanometers in the next several years.  However, scaling to 7 nanometers and perhaps below, by the end of the decade will require significant investment and innovation in semiconductor architectures as well as invention of new tools and techniques for manufacturing.

“The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?” said John Kelly, senior vice president, IBM Research. “IBM engineers and scientists, along with our partners, are well suited for this challenge and are already working on the materials science and device engineering required to meet the demands of the emerging system requirements for cloud, big data, and cognitive systems. This new investment will ensure that we produce the necessary innovations to meet these challenges.”

“Scaling to 7nm and below is a terrific challenge, calling for deep physics competencies in processing nano materials affinities and characteristics. IBM is one of a very few companies who has repeatedly demonstrated this level of science and engineering expertise,” said Richard Doherty, technology research director, The Envisioneering Group.

Bridge to a “Post-Silicon” Era
Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. Their increasingly small dimensions, now reaching the nanoscale, will prohibit any gains in performance due to the nature of silicon and the laws of physics. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost and higher speed processors that the industry has become accustomed to.

With virtually all electronic equipment today built on complementary metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scalability limits of the silicon transistor.

Beyond 7 nanometers, the challenges dramatically increase, requiring a new kind of material to power systems of the future, and new computing platforms to solve problems that are unsolvable or difficult to solve today. Potential alternatives include new materials such as carbon nanotubes, and non-traditional computational approaches such as neuromorphic computing, cognitive computing, machine learning techniques, and the science behind quantum computing.

As the leader in advanced schemes that point beyond traditional silicon-based computing, IBM holds over 500 patents for technologies that will drive advancements at 7nm and beyond silicon — more than twice the nearest competitor. These continued investments will accelerate the invention and introduction into product development for IBM’s highly differentiated computing systems for cloud, and big data analytics.

Several exploratory research breakthroughs that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips, include quantum computing, neurosynaptic computing, silicon photonics, carbon nanotubes, III-V technologies, low power transistors and graphene:

Quantum Computing
The most basic piece of information that a typical computer understands is a bit. Much like a light that can be switched on or off, a bit can have only one of two values: “1” or “0.” Described as superposition, this special property of qubits enables quantum computers to weed through millions of solutions all at once, while desktop PCs would have to consider them one at a time.

IBM is a world leader in superconducting qubit-based quantum computing science and is a pioneer in the field of experimental and theoretical quantum information, fields that are still in the category of fundamental science – but one that, in the long term, may allow the solution of problems that are today either impossible or impractical to solve using conventional machines. The team recently demonstrated the first experimental realization of parity check with three superconducting qubits, an essential building block for one type of quantum computer.

Neurosynaptic Computing
Bringing together nanoscience, neuroscience, and supercomputing, IBM and university partners have developed an end-to-end ecosystem including a novel non-von Neumann architecture, a new programming language, as well as applications. This novel technology allows for computing systems that emulate the brain’s computing efficiency, size and power usage. IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons and a hundred trillion synapses, all while consuming only one kilowatt of power and occupying less than two liters of volume.

Silicon Photonics
IBM has been a pioneer in the area of CMOS integrated silicon photonics for over 12 years, a technology that integrates functions for optical communications on a silicon chip, and the IBM team has recently designed and fabricated the world’s first monolithic silicon photonics based transceiver with wavelength division multiplexing.  Such transceivers will use light to transmit data between different components in a computing system at high data rates, low cost, and in an energetically efficient manner.

Silicon nanophotonics takes advantage of pulses of light for communication rather than traditional copper wiring and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

Businesses are entering a new era of computing that requires systems to process and analyze, in real-time, huge volumes of information known as Big Data. Silicon nanophotonics technology provides answers to Big Data challenges by seamlessly connecting various parts of large systems, whether few centimeters or few kilometers apart from each other, and move terabytes of data via pulses of light through optical fibers.

III-V technologies
IBM researchers have demonstrated the world’s highest transconductance on a self-aligned III-V channel metal-oxide semiconductor (MOS) field-effect transistors (FETs) device structure that is compatible with CMOS scaling. These materials and structural innovation are expected to pave path for technology scaling at 7nm and beyond.  With more than an order of magnitude higher electron mobility than silicon, integrating III-V materials into CMOS enables higher performance at lower power density, allowing for an extension to power/performance scaling to meet the demands of cloud computing and big data systems.

Carbon Nanotubes
IBM Researchers are working in the area of carbon nanotube (CNT) electronics and exploring whether CNTs can replace silicon beyond the 7 nm node.  As part of its activities for developing carbon nanotube based CMOS VLSI circuits, IBM recently demonstrated — for the first time in the world — 2-way CMOS NAND gates using 50 nm gate length carbon nanotube transistors.

IBM also has demonstrated the capability for purifying carbon nanotubes to 99.99 percent, the highest (verified) purities demonstrated to date, and transistors at 10 nm channel length that show no degradation due to scaling–this is unmatched by any other material system to date.

Carbon nanotubes are single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device that will work in a fashion similar to the current silicon transistor, but will be better performing. They could be used to replace the transistors in chips that power data-crunching servers, high performing computers and ultra fast smart phones.

Carbon nanotube transistors can operate as excellent switches at molecular dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of the leading silicon technology. Comprehensive modeling of the electronic circuits suggests that about a five to ten times improvement in performance compared to silicon circuits is possible.

Graphene
Graphene is pure carbon in the form of a one atomic layer thick sheet.  It is an excellent conductor of heat and electricity, and it is also remarkably strong and flexible.  Electrons can move in graphene about ten times faster than in commonly used semiconductor materials such as silicon and silicon germanium. Its characteristics offer the possibility to build faster switching transistors than are possible with conventional semiconductors, particularly for applications in the handheld wireless communications business where it will be a more efficient switch than those currently used.

Recently in 2013, IBM demonstrated the world’s first graphene based integrated circuit receiver front end for wireless communications. The circuit consisted of a 2-stage amplifier and a down converter operating at 4.3 GHz.

Next Generation Low Power Transistors
In addition to new materials like CNTs, new architectures and innovative device concepts are required to boost future system performance. Power dissipation is a fundamental challenge for nanoelectronic circuits. To explain the challenge, consider a leaky water faucet — even after closing the valve as far as possible water continues to drip — this is similar to today’s transistor, in that energy is constantly “leaking” or being lost or wasted in the off-state.

A potential alternative to today’s power hungry silicon field effect transistors are so-called steep slope devices. They could operate at much lower voltage and thus dissipate significantly less power. IBM scientists are researching tunnel field effect transistors (TFETs). In this special type of transistors the quantum-mechanical effect of band-to-band tunneling is used to drive the current flow through the transistor. TFETs could achieve a 100-fold power reduction over complementary CMOS transistors, so integrating TFETs with CMOS technology could improve low-power integrated circuits.

Recently, IBM has developed a novel method to integrate III-V nanowires and heterostructures directly on standard silicon substrates and built the first ever InAs/Si tunnel diodes and TFETs using InAs as source and Si as channel with wrap-around gate as steep slope device for low power consumption applications.

“In the next ten years computing hardware systems will be fundamentally different as our scientists and engineers push the limits of semiconductor innovations to explore the post-silicon future,” said Tom Rosamilia, senior vice president, IBM Systems and Technology Group. “IBM Research and Development teams are creating breakthrough innovations that will fuel the next era of computing systems.”

IBM’s contributions to silicon and semiconductor innovation include the invention and/or first implementation of: the single cell DRAM, the “Dennard scaling laws” underpinning “Moore’s Law”, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed silicon germanium (SiGe), High-k gate dielectrics, embedded DRAM, 3D chip stacking, and Air gap insulators.

IBM researchers also are credited with initiating the era of nano devices following the Nobel prize winning invention of the scanning tunneling microscope which enabled nano and atomic scale invention and innovation.

IBM will also continue to fund and collaborate with university researchers to explore and develop the future technologies for the semiconductor industry. In particular, IBM will continue to support and fund university research through private-public partnerships such as the NanoElectornics Research Initiative (NRI), and the Semiconductor Advanced Research Network (STARnet), and the Global Research Consortium (GRC) of the Semiconductor Research Corporation.

Each year at SEMICON West, the largest and most influential microelectronics exposition in North America, the “Best of West” awards are presented by Solid State Technology and SEMI. The award was established to recognize contributors moving the industry forward with their technological developments in the microelectronics supply chain.

The 2014 Best of West Finalists are:

  • Microtronic: EAGLEview IV — EAGLEview IV is an automated macro defect wafer inspection system that provides industry leading throughput (3,000+ Wafers Per Day), defect detection accuracy, and wafer classification. EAGLEview IV resolves many of the problems of manual/micro wafer inspection by automating and standardizing wafer inspection. South Hall, Booth 729 (Category: Metrology and Test)
  • Nikon Corporation: NSR-S630D Immersion Scanner — The NSR-S630D ArF immersion scanner leverages the well-known Streamlign platform, incorporating further developments in stage, optics, and autofocus technology to deliver unprecedented mix-and-match overlay and focus control with sustained stability to enable the 10/7 nm node.  South Hall, Booth 1705 (Category: Wafer Processing Equipment)   
  • SPTS Technologies:  Rapier XE — Rapier XE is a new, 300mm, plasma etch module which can lower costs and increase yields for device manufacturers utilizing TSVs for 3D packaging.  Designed for via reveal applications, the new module offers blanket silicon etch rates typically 3-4x faster than competing systems. South Hall, Booth 1317 (Category: Wafer Processing Equipment)   

The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 9, 2014.

Berger Pierre-DamienBy Pierre-Damien Berger, VP Business Development & Communication; CEA-Leti

Whatever forecast one uses for the future of the Internet of Things in terms of connected objects or business opportunities, the IoT will be big. Citing industry sources during of “The Internet of Things: from sensors to zero power,” the recent LetiDays conference in Grenoble, France, speakers offered projections venturing up to 50 billion connected objects by 2020.

Jacques Husser, COO of SIGFOX, said the IoT is the next major technological revolution, and that connecting billions or trillions of devices and enabling them to communicate with each other and will require more than high bandwidth. While increasing bandwidth is a key focus for multi-media and voice data network operators, for IoT companies reducing energy consumption and costs are key to handling the continuous volume of small messages from all those things.

SIGFOX, whose network is dedicated to the IoT, provides power-efficient, two-way wireless connectivity for IoT and machine-to-machine communications. Husser said the company’s technology is compatible with existing chipsets from vendors such as Texas Instruments, STMicroelectronics, Silicon Labs, Atmel, NXP and Semtech. Husser said that while SIGFOX’s technology complements 2G, 3G and 4G systems, it does not require a SIM card. Devices’ IP addresses are established during manufacturing.

The company, which has networks operating or in rollout with partners in several countries and major cities, is enabling applications for building and vehicle security, indoor climate monitoring, pet tracking, smart-city apps for parking and lighting management, asset management including billboard monitoring, water utility metering, and health-care apps like fall detection, distress signaling and medicine dispensing. Many more are expected.

Leti’s RF design and antenna expertise were used to help connect SIGFOX’s cellular networks. In addition, Leti is working with other startups and SMEs to develop and connect smart functions in a variety of products that will use the IoT to communicate. Primo1D was spun out of Leti in 2013 to produce E-Thread®, an innovative microelectronic packaging technology that embeds LEDs, RFIDs or sensors in fabric and materials for integration in textiles and plastics using standard production tools.

Leti startup BeSpoon recently launched SpoonPhone, a smartphone equipped with the capability to locate tagged items within a few centimeters’ accuracy. The capability is enabled by an impulse radio ultra-wideband (IR-UWB) integrated circuit developed by Leti and BeSpoon. Leti and Cityzen Sciences, the award-winning designer and developer of smart-sensing products, have begun a project to take the company’s technology to the next level by integrating micro-sensors in textiles during the weaving stage.

Leti and CORIMA, a leading supplier of carbon-composite wheels and frames for track and road-racing cyclists, are developing an integrated sensor system to measure the power output of riders as they pedal.

Citing research by Morgan Stanley Research, Leti’s telecommunications department head Dominique Noguet noted that worldwide shipments of smartphones and tablets exceeded shipments of desktop and notebook PCs for the first time in 2011. This signaled that the web has gone mobile, a fact underscored by a Cisco forecast that M2M mobile data traffic will increase 24x from 24 petabytes per month in 2012 to 563 petabytes in 2017.

Noguet said the IoT growth will present scaling challenges and require new communication protocols for sporadic, asynchronous, decentralized, low-power traffic. In addition to harvesting, or scavenging, energy to assure continuous connectivity, there will be demand for technologies that enable spectrum scavenging in unlicensed spectra, for example, and that use new bands, such as millimeter wave, white spaces and even light.

Leti has numerous ways to support development of the IoT, ranging from embedding antennas in specific materials through characterization and design, to implementing full-blown custom radio technologies. The inclusion of UHF RFID tags for the tire industry was cited as a first example where read/write range performances were a challenge. Leti’s ultra-wideband localization technology is another example where competence in signal processing, real-time design, antenna technology and mixed RF/digital ASIC design was combined to provide a complete solution where no off-the-shelf approach was available.

Noguet also noted potential threats to IoT security, and cited Leti’s involvement in the Santander, Spain, smart city project, which includes experimental advanced research on IoT technologies. Leti and CEA-List were in charge of securing access to the SmartSantander infrastructure and communications over a wireless sensor network. This included ensuring the security of the transactions and protecting users’ privacy.

By Shannon Davis, Web Editor

The core element of the semiconductor industry’s roadmap has been scaling – but Gopal Rao believes that isn’t enough anymore.

“The roadmap has never taken into consideration what the consumers were asking for,” said Mr. Rao, on Wednesday’s closing session at The ConFab 2014.

The industry has enjoyed a stable, predictable industry for many years, as we made PCs and a lot of PCs. However, these are no longer the driving devices in the consumer market, and with different cost structures and more pressure to innovate than ever before, Mr. Rao stressed that the industry’s tendency to solely focus on scaling was no longer going to be enough to keep up with shifting consumer demands. Mr. Rao’s main charge: the industry needs to intercept consumer thought and demand and determine how it is going to impact the semiconductor industry and supply chain.

“We need to cater the roadmap to the technologies that are coming and the products that consumers want,” Mr. Rao said.

In order to adapt, Mr. Rao explained that it was imperative to integrate the entire supply chain into the roadmap if we really want to make significant strides in the manufacturability of these new products.

“We need to look at the roadmap as an ecosystem – not just materials, not just equipment, but the entire picture. We need to understand how to bring the supply chain into the picture,” Mr. Rao said.

To do this, Mr. Rao outlined the elements of effective problem solving and encouraged his audience to become masters of it. To be effective in the evolving technology landscape, Mr. Rao stressed the importance of understanding and analyzing every aspect of the supply chain, down to the smallest component, all of which contribute to defects and can no longer be ignored if quality is to be maintained.

“You need to understand to the smallest degree of your supply chain,” Mr. Rao charged ConFab’s attendees. “You need to analyze and trace the data. If you don’t do that, then the time to market and time to money are sacrificed.”

“We can’t follow Moore’s Law conveniently and forget about what’s two years down the road,” he concluded.

Gopal Rao presents at The ConFab 2014 on June 25, 2014.

Gopal Rao presents at The ConFab 2014 on June 25, 2014.

SPTS Technologies, a manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti in Grenoble, France, to develop 3D-TSV technologies.

The two-year agreement enters under the framework of the Nanoelec Research Technology Institute program which is led by CEA-Leti, and covers co-development of a range of deposition processes for next-generation 3D high aspect ratio through-silicon-via (TSV) solutions. The agreement builds on the long established relationship between the partners who have already collaborated in the past, particularly on the development and optimization of an advanced MOCVD TiN barrier for high aspect ratio TSV.

3D packaging of semiconductor devices, using TSVs to connect stacked die, is accepted as a critical technology to deliver industry performance goals without exceeding power budgets. To scale future 3D devices, new techniques will be needed to manufacture TSV’s of smaller diameter and higher aspect ratio than are used today.  Under this agreement, SPTS and CEA-Leti aim to develop production worthy solutions to address these challenges. Previous collaboration has resulted in a number of key advancements in the formation of TSVs using SPTS’ deep reactive ion etch (DRIE), chemical vapor deposition (CVD) and physical vapor deposition (PVD). One of the key achievements includes optimization of an advanced metal organic chemical vapor deposition (MOCVD) TiN barrier for high aspect ratio TSV.

“The results previously achieved keeps SPTS at the forefront of 3D-TSV development,” said Kevin Crofton, president and chief operating officer of SPTS. “In partnership with CEA-Leti, we plan now to develop technology and processes that will further extend TSV aspect ratios beyond 20:1, with a particular focus on developing an MOCVD copper process as a seed layer to replace ionized PVD.”

“The work with SPTS and other partners will create solutions that will be transferred into industry,” said Dr. Laurent Malier, CEO of CEA-Leti and President of the Nanoelec RTI board. “Combining Leti’s integration expertise with the specific process knowledge of successful equipment manufacturers like SPTS enables innovation and allows us to create an optimized, cost-effective process flow for volume manufacturing of 3D-IC devices.”

North America-based manufacturers of semiconductor equipment posted $1.41 billion in orders worldwide in May 2014 (three-month average basis) and a book-to-bill ratio of 1.00, according to the May EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in May 2014 was $1.41 billion. The bookings figure is 2.4 percent lower than the final April 2014 level of $1.44 billion, and is 6.6 percent higher than the May 2013 order level of $1.32 billion.

The three-month average of worldwide billings in May 2014 was $1.41 billion. The billings figure is 0.3   percent higher than the final April 2014 level of $1.40 billion, and is 15.1 percent higher than the May 2013 billings level of $1.22 billion.

“Semiconductor equipment bookings and billings maintain a consistent pace approaching the end of the second quarter,” said Denny McGuirk, president and CEO of SEMI.  “Like other trends reported across the industry, semiconductor process equipment sales demonstrate positive year-over-year performance.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
December 2013

1,349.7

1,380.8

1.02
January 2014

1,233.2

1,280.3

1.04
February 2014

1,288.3

1,295.4

1.01
March 2014

1,225.5

1,297.7

1.06
April 2014 (final)

1,403.2

1,443.0

1.03
May 2014 (prelim)

1,408.0

1,407.9

1.00

Source: SEMI, June 2014

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

Design and construction professionals are showing unprecedented levels of collaboration through the G450C.

BY ADRIAN MAYNES and FRANK ROBERTSON, G450C, Albany, NY

Hard data and strong collaboration are proving effective in solving the challenges inherent in building 450mm semiconductor fabs. In the past year, the Facilities 450mm Consortium (F450C) — the facilities-focused off-shoot of the Global 450mm Consortium — has provided the unified forum to test and analyze utility requirements, overhead conveyance systems and energy-efficiency strategies. The Global 450mm Consortium (G450C), a New York-based public/private program with leadership from GLOBALFOUNDRIES, IBM, Intel, Samsung, TSMC and the College of Nanoscale Science and Engineering is housed on SUNY’s University at Albany campus and maintains focus on 450mm process and equipment development (FIGURE 1). Combined, preliminary results from the seconsortiaare building the framework for this next-generation fab.

FIGURE 1. The College of Nanoscale Science and Engineering NanoFab Xtension, which houses 25,000 ft2 of cleanroom for 450mm research and development. Source: CNSE.)

FIGURE 1. The College of Nanoscale Science and Engineering NanoFab Xtension, which houses 25,000 ft2 of cleanroom for 450mm research and development. Source: CNSE.)

The F450C came into existence in 2013 facing a series of significant technical hurdles. The purpose of the 450mm fab is to manufacture more advanced integrated circuits at lower cost with a lighter environmental footprint. However, the initial 450mm tool guidelines point to a greater cost per square foot (meter) of cleanroom space, much heavier structural loads and significantly larger tool sizes, which can detract from the manufacturing flexibility the industry seeks. The potential for competing visions among industry leaders and the cyclicality of semiconductor demand in the marketplace add head winds on the path toward widespread 450mm adoption. These factors pose challenges that will need to be managed to ensure 450mm program objectives are achieved.

  • All key players are coming together
  • CNSE is providing a uniquely neutral and technologically advanced home for critical research
  • Work of the G450C is being guided by a strict application of an inside-out design approach
  • Key advances have been made in utility requirements, overhead conveyance systems and energy efficient strategies

Data are pointing to promising advantages of the 450mm model, which may support broad industry adoption.

A collaborative approach

When the complexity of the semiconductor manufac- turing process adds the scale of a 450mm wafer, the facility requirements can seem immense. The current scale of today’s 300mm factories indicates that managing the size and complexity is key to attaining the efficiencies needed for 450mm adoption. Driving to GLOBALFOUNDRIES’ massive facility in upstate New York, for example, feels more like approaching a coliseum than a manufacturing fab (FIGURE 2).

FIGURE 2. GlobalFoundries Fab8.1 located in Malta, NY.

FIGURE 2. GlobalFoundries Fab8.1 located in Malta, NY.

Naturally, the industry is closely examining impacts to the facility infrastructure along with the increase in wafer size, since merely scaling the manufacturing process is not practical. The size of the 450mm fab and its associated utility consumption projections would exceed affordability and exacerbate sustainability concerns without close focus on potential efficiencies.

The facility experts involved in establishing and implementing 450mm infrastructure requirements are facing a similar degree of challenges as the integrated circuit and equipment manufacturers.

Design and construction professionals are showing unprecedented levels of collaboration through the G450C to deconstruct semiconductor facility matter associated with 450mm adoption. This consortium formed in the summer of 2013 to unite collective industry expertise to tackle pressing 450mm facility and infrastructure issues. With a special focus on safety, cost, schedule, sustainability and environmental footprint, this group aims to: reduce production cost; increase manufacturing productivity; and reduce the environmental load associated with each chip manufactured.

Everything starts at the process level

Early development of 450mm silicon and infrastructure began before the turn of the decade, yet it wasn’t until 2013 that 450mm and 300mm process tools began to progress synchronously through technology development at CNSE. The function, operation and shape of a semiconductor facility are driven by the process technology and its corresponding manufacturing requirements. Design progresses from the inside out, starting with the process, in this sequence:

1. Process: the early development of silicon and infrastructure defines the utility process requirements

2. Equipment & Automation: process requirements dictate the process equipment/ tools

3. Production Environment: process equipment defines the manufacturing environment and critical process systems (power, the periphery of the tools, capable of multiple configura- tions for somewhat heavier payloads water, vacuum, chemicals and gases)

4. Site Infrastructure: the facility and its corresponding site requirements are developed

Equipment suppliers have begun providing tools so that G450C can create a 450mm baseline. Industry guidance is for some 450mm tools to maintain 300mm footprint normalized to throughput. Through working with original equipment manufacturers (OEMs) and suppliers, it becomes clear that some tools required to manufacture wafers are bigger and many components are heavier than their 300mm counterparts. This led members of Semiconductor Equipment and Materials International (SEMI) to prioritize the topic of “cranes and hoists” in a survey of potential 450mm standardization focus areas in late 2012. Members of the G450C agreed that industry alignment was needed to deal with the handling of components for 450mm equipment that might be larger and heavier than those currently lifted manually.

In March 2014, a multifaceted work group consisting of IC makers, OEMs, and facility systems suppliers published an initial set of component lifting systems for 450mm fab equipment. The Component Lift working group addressed a number of IC maker concerns around interference with overhead track automation systems, ceiling loading and fab layout flexibility. This led to almost immediate determination that ceiling-mounted cranes generally would not work for wafer fabs. Three broad classes of component lifting were then identified:

1. Generally light-duty custom fixtures integrated with and often mounted on the tools for specific component handling operations

2. Aisle-based mobile lift mechanisms operating from

3. Gantry-like structures addressing the full span of large (e.g., cluster) tools, capable of heavy lifting and conveying payloads beyond the tool periphery

In a 10-month span, the Component Lift working group published a cost of ownership model, safety imperatives, productivity suggestions and other key considerations in their March 2014 guidelines. While more work awaits, this effort is indicative of a new era in which industry collaboration lays the foundation for 450mm success.

Correctly sizing utilities

Vital to the 450mm program’s success is the ability to create an efficient manufacturing facility that builds upon industry know-how and lessons learned from prior technologies. Yesterday’s approach of examining singular utility systems and then searching for ways to improve their individual efficiency is not sufficient. Facility designers must consider how process equipment and facility systems interact as a whole.

In the fall of 2013, the F450C conducted a survey with all aforementioned 450mm consortium member companies to build a roadmap based on the industry’s priority focus areas. A plurality of polled members identified 450mm factory utility right-sizing as the top priority for the F450C. Simply stated, we want smarter utility consumption data to enable more efficient 450mm factories, not singular systems, but as a whole factory.

A “utility right-sizing” focus group was created and has been working since the fall of 2013 to characterize true 450mm utility consumption and requirements. Using the inside-out design process, the first step is to conduct real-time measurements for all critical 450mm process tools.

A critical step in the semiconductor manufacturing process is that of wet process, in which liquid chemicals remove materials from a wafer. This step is well known for its high usage of power, water, drains and chemicals. The G450C and F450C members are installing a series of monitoring devices on CNSE’s first 450mm wet process tool.

Haws Corporation, a F450C member company, has donated a series of effluent monitoring systems that enable utility characterization for acid waste neutralization drains, HF drains and exhaust. By characterizing drain effluents, the industry can more intelligently identify opportunities for reuse, reclaim and recycling. M+W Group, CH2M Hill and the G450C are collaborating to install power and flow meters on this same tool. In the second quarter of 2014, the group will conduct real-time utility measurements at idle, operational and peak modes, and combine the data with 300mm benchmarks to assemble the most comprehensive factory utility model in the history of our industry.

To illustrate why this initiative is a priority, consider that a 10 percent decrease in process equipment power consumption would reduce facility construction capex by ~2 percent. For a $1 billion dollar fab, this equates to an impact of approximately $20 million. A 10 percent decrease in process equipment ultra-pure water (UPW) consumption would reduce UPW system cost by approximately 7 percent and facility construction CAPEX by 0.3 percent.

Wet process is the start. This monitoring methodology will be repeated for all critical tool sets within the 450mm process in the coming years.

Just the beginning

Designing a safe way to install and work on 450mm process tools, combined with measuring and characterizing utilities, are two vital priorities for improving facility sustainability and efficiency. But it is just the beginning.

TABLE 1. (*) Increase is mainly driven by new processes and equipment technology, e.g. EUV, single wafer processing etc. (**) Pending AMHS concept and preference for floor mounted or ceiling suspended maintenance cranes (***) Mainly driven by simultaneous introduction of new lithography technology, not by wafer size transition Source: M+W Group, 2013

TABLE 1.
(*) Increase is mainly driven by new processes and equipment technology, e.g. EUV, single wafer processing etc.
(**) Pending AMHS concept and preference for floor mounted or ceiling suspended maintenance cranes
(***) Mainly driven by simultaneous introduction of new lithography technology, not by wafer size transition
Source: M+W Group, 2013

Edwards Vacuum, an original member of the F450C, is also providing its expertise to advance a “Green Mode” project, focusing on resource reduction and energy savings. About half of the process tools in a semiconductor facility use vacuum pumps and abatement systems to treat exhaust gases. The abatement systems were designed to run at full process capacity, even when the tool is not processing wafers. These “sub-fab” systems have significant impact on utility usage (power, process cooling water, acid wastewater treatment and nitrogen). Putting sub-fab systems into idle or green mode when there are no wafers processed can represent substantial reductions in operating and infrastructure costs. The Green Mode project is a multi-equipment supplier collaboration with the following goals:

1. Identify the impacts of vacuum operation changes at the process chamber, i.e., Green Mode

2. Consider other monitoring parameters that could provide information on vacuum system “health” and performance

3. Collect data to better understand correlation between process conditions and vacuum performance

Results from this project will drive SEMI standards that minimize process risk while adding to utility consumption savings.

From suppliers to scientists, the path to realizing 450mm affordability will continue to require unparalleled industry collaboration. In addition to the facility and infrastructure challenges featured in this article, leaders of the semiconductor industry continue to prioritize roadmap items that will further reduce capex for future 450mm fabs.

The G450C and F450C are also working with global airborne molecular contamination organizations and forums to examine how facility-related design (automated material handling system/stocker evaluation, parts- cleaning design, etc.) can reduce defectivity and improve product yield.

And as the roadmap for 450mm is further defined, there will be more facility and infrastructure projects to come.

The G450C and F450C will continue to coordinate globally to ensure a cost-effective facility transition from 300mm to 450mm. In uncertain economic times, it is electrifying to witness unparalleled collaboration where companies that normally compete in the free market have joined together to deliver a safe, cost-efficient and sustainable fab of the future.

By Debra Vogler, SEMI

The introduction of new materials, such as III-Vs, into high-volume manufacturing of semiconductors, likely will occur sometime around the 7nm and/or 5nm nodes. III-V’s introduction, along with the potential transition to 450mm wafers, and the increasing expansion of global regulatory requirements, will heighten environmental, health and safety (EHS) concerns that must be addressed as the industry goes forward. The Sustainable Manufacturing Forum to be held in conjunction with SEMICON West 2014, will feature experts in the manufacture of semiconductors, microelectronics, nanoelectronics, photovoltaics, and other high-tech products.

One of the Sustainable Manufacturing Forum speakers, Richard Hill, Technology Infrastructure manager at SEMATECH, will discuss how the addition of III-V materials into the high-volume manufacture of semiconductors will bring sustainability issues to the forefront, primarily driven by the toxicity of arsenic that is used in much greater quantities in III-V production. Challenges include wastewater treatment, toxic gas detection control and abatement, and the need for robust protocols to ensure operator and maintenance personnel safety. Hill will speak at the Next Generation Eco Fab session on July 9 at SEMICON West.

SEMATECH recently completed a joint study of III-V EHS challenges with the College of Nanoscale Science and Engineering (SUNY CNSE). The assessment consisted of running 300mm wafers through a representative 5nm III-V process flow (Figure 1). (Many semiconductor industry experts agree that III-V materials will enter the process flows in high volumes at 5nm.) Among the processes that will pose the greatest challenges with respect to III-V materials are MOCVD, CMP, wet etch/clean, dry etch, and film deposition. The project was heavily focused on understanding the levels of arsenic that would be present in wastewater, as well as loading of other III-V materials. The impact of III-V outgassing that could occur during processing and the amounts of gases that could be released when a tool is opened for maintenance were of particular interest in the project.

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Among the high-level challenges associated with wet etch are the potential for arsine and phosphine outgassing (during processing).

“Wet etch tools are designed to have a controlled environment,” said Hill, “but they are not like high-vacuum systems that are designed to contain toxic gases.” Hill told SEMI that if the exhaust system fails during the processing of a wafer, it is critical to know the risks and ensure mitigation. The SEMATECH/CNSE project looked at a range of different chemistries and identified those that are low risk for arsine and phosphine generation (and therefore, a low risk of outgassing) and those that had a high risk of outgassing. The low risk chemistries are, naturally, the ones that the industry should try to design into a III-V flow.

The joint project also evaluated the III-V loading in wastewater from the wet etch process. “There were measurable quantities of arsenic in the waste stream,” said Hill. Though he added that while the levels weren’t significantly high, some treatment of the waste water would have to be done depending on what’s allowable within local discharge limits and permits. With the industry looking ahead to 5nm and already designing the fabs of the future, Hill believes that these results will be important for specifying wastewater treatment.

The joint SEMATECH/CNSE project also evaluated the wastewater stream from the burn wet scrubber when III-V materials are used in a contact etch (dry) process. The study found measurable arsenic in the wastewater. “Fabs of the future will need wet treatment facilities for arsenic and indium,” Hill told SEMI. “In recent years, concerns about indium have been elevated, and we believe that tighter restrictions on it will be introduced in the future.” Chamber clean is also critical when etching (dry) III-V materials. “If you don’t do the right type of cleaning regimen, you could have next-wafer contamination.” Additionally, without the proper protocol, maintenance personnel could be exposed to arsine or phosphine when the chamber is opened, depending on the process. The cleaning protocol is highly dependent on the type of etch being done, and each type could have different requirements.

For Hill, the key takeaway from the joint evaluation was that, while there are risks when processing III-V materials, there are no showstoppers — solutions can be engineered. “People should take these risks seriously, but they shouldn’t be scared off by them,” said Hill.

Sustainability and the Role of Collaboration and Standards

Steve Moffatt, CTO, Front-end Equipment at Applied Materials (also a speaker at the Next Generation Eco Fab session at the Sustainable Manufacturing Forum at SEMICON West), told SEMI that many established procedures for dealing with arsine and phosphine already exist. He views the efforts by the industry going forward as one of accurately quantifying the size and scope of the problem. “The methods are in place, but the absolute quantities of III-Vs will be substantially higher,” said Moffatt.

Additionally, other emissions (e.g., PFCs) that are well regulated and generally understood, will see an increase in the quantities as a result of more layers being processed for 3D chips. Even the potential transition to 450mm wafers will figure into the industry’s need for a more accurate scope of the EHS challenges involved. The increase in wafer size will naturally lead to larger manufacturing equipment noted Moffatt and that, in turn, will drive increases in energy, water, and process chemical consumption at both the tool and fab levels.

As regulatory pressure increases on a global scale, the situation also becomes more complex. Beyond the use of new materials such as III-Vs and nanomaterials, Moffatt commented that new methods of energetics (i.e., ways of putting energy into a processing system) will require very careful and close assessment of the risk control measures. Another sustainability issue arises from the basic fact that, as opposed to the highly prevalent element of silicon in the earth’s crust, many of the newer materials being used in higher quantities for semiconductor manufacturing (e.g.,Ga, As, etc.) are much less abundant. These exotic materials, of necessity, must be handled in the most efficient of ways.

Going forward, there will be increased regulatory pressure to reduce a fab’s carbon footprint and produce more sustainable products. Moffatt says the industry can expect more pressure to reduce greenhouse gas (GHG) emissions along with adhering to conflict minerals regulations and managing EHS concerns throughout the entire life-cycle of a product (Figure 2). “One company can’t do it on its own, it’s a life-cycle consideration,” said Moffatt. “If we have the right collaboration together, we have a greater probability with the right kinds of standards of bringing good, effective green chemistry solutions to high-value problems.”

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Regarding standards activities on energetics, Moffatt pointed to ongoing collaboration and hazard assessment between SEMI, SEMATECH and other industry groups.

“We will need to continually evaluate the need for additional standards activities — both new and updates — in addition to industry collaboration on “Green” chemistry,” said Moffatt.  “As a starting point, sustainability concerns could be built into the initial assessment of new chemicals and processes, which will begin the discussion and raise awareness of these issues.”

Hill (SEMATECH) and Moffatt (Applied Materials) will be joined by speakers from IMEC, Intel, Samsung, Air Products, and MW Group at the “Next Generation Eco Fab” session of the Sustainable Manufacturing Forum at SEMICON West 2014, July 7-10 in San Francisco, Calif.  For more information, visit: http://www.semiconwest.org.