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By Ajit Manocha

At a Glance

“Software is eating the world … and AI is eating software.” Amir Husain, author of The Sentient Machine, at SEMICON West 2018

We’re living in a digital world where semiconductors have been taken for granted. But, Artificial Intelligence (AI) is changing everything – and bringing semiconductors back into the deserved spotlight. AI’s potential market of hundreds of zettabytes and trillions of dollars relies on new semiconductor architectures and compute platforms. Making these AI semiconductor engines will require a wildly innovative range of new materials, equipment, and design methodologies.

Moore’s Law carried us the past 50-plus years and as we’re now stepping into the dawn of AI’s potential, we can see that the coming Cognitive Era will drive its own exponential growth curve. This is great for the world – virtually every industry will be transformed, and people’s lives will get better – and it’s fantastic for our industry. This truly is the very best time to be working in our industry. I’m excited to be at SEMI in this inflection period and at the center of the collaborative platforms that bring the electronics manufacturing supply chain together to Connect, Collaborate, and Innovate to realize the new Cognitive Era. I invite you to partner with SEMI in building the foundation for the Cognitive Era to increase the growth and prosperity of our industry.

The World Wakes Up

Our lives have become digital. An Amazon Echo wakes us up and answers questions about the weather and traffic. Google Maps tells us the best way to get to a meeting. Yelp finds the best nearby restaurant. A Tweet now even informs us of the latest change in government policy. It’s a digital world that we live in – and the world already takes it for granted.

We in the industry know that the digital world only works because of the semiconductors we make and because of our integrated electronics manufacturing supply chain. We make the materials and equipment that, in turn, make the chips that become the beating hearts of the digital economy.

But, semiconductors have been largely invisible – hidden away under and inside a smart speaker, locked deep within a phone, buried in data centers and out of view. Meanwhile, the internet companies like Google, Amazon, Alibaba, Tencent, and Facebook stole the meaning of “Tech” and were given most of the credit for our digital world.

But, finally, things are changing – it’s all coming back to semiconductors!

AI Changing Everything

Over $400B in semiconductors were sold in 2017 – those unseen chips like hearts beating away in Apple computers, in mobile phones for online shopping and social media, and in televisions showing Netflix. Now internet companies Alphabet, Alibaba, Amazon, Facebook, Microsoft and others are rushing to develop their own chips. Silicon is back in the Silicon Valley! Hardware is, once again, the place to be. Why? We are now entering the epoch of Artificial Intelligence (AI) – and semiconductors, and new compute architectures, are the key to AI. At this moment, hardware, not software, is the AI enabler to make leaps in performance and to usher in new architectures to become brain-like with neural networks.

Beyond major AI chip investments like Google’s (Alphabet) $300M+ program to develop its Tensor Processing Unit (TPU) chip, there’s been a surge in new chip startups and VC funding. Last year, VCs (with corporate investors) invested more than $1.5B in new AI chip startups – doubling the rate from the prior year.

After years of consolidation, there is, as some have described, a “Cambrian Explosion” of semiconductor startups with names like Cerebras, Graphcore, Wave Computing, Horizon Robotics, Cambricon Technologies, and DeePhi from the US, Europe, and China. Cambricon (China) has already become the first AI chip “Unicorn” (startup valued $1B+) with a valuation of more than $2.5B after their recent Round B financing. It’s a new silicon world and a new race, as Cade Metz (The New York Times, 1/14/2018) said, “… everyone is starting from the same place: the beginning of a new market.”

Winning at AI is very big business. John Kelly, SVP Cognitive Solutions and Research at IBM, in his SEMICON West keynote earlier this month, said, we’re in the era of Artificial Intelligence with more than a $2T opportunity for AI decision making support on top of the $1.5T IT business in 2025. McKinsey estimates deep learning could account for between $3.5T and $5.8T in annual value.

As John Kelly presented, AI will transform entire industries – not just our personal devices and lives. The $2T AI decision making support opportunity in 2025 is projected to transform the major economy industries as follows:

Moore’s Law describes the exponential increase in the number of transistors per area that has driven growth, and has been the engine for digital innovation, through first the computer era and then the mobility era and now into the dawn of the data era. While the Dennard scaling approach to Moore’s Law may be slowing, the data-centric era continues to drive demand and the industry continues to find new ways to pack more transistors into less volume. Chip sales are forecast to pass $0.5T in 2019 and I predict they will surpass $1T before 2030.

It turns out the Smart is not enough – we must reach “Beyond Smart.”

Beyond Smart – The Cognitive Era

As we move further into the data-centric age, we see it is more than Big Data and AI, it is, instead, the dawn of a wholly new cognitive era. SEMICON West’s 2018 theme was “Beyond Smart” because we are standing at the inflection from sensors triggering actions (smart) to systems that learn and make decisions (cognitive). Devices are moving “beyond smart” to being “cognitive or aware.” Gary Dickerson (CEO of Applied Materials) at SEMICON West said, “… we are in the beginning of the first inning of a major inflection.”

Even in the early dawn of the cognitive era, the volume of data is simply astonishing. In the last 24 months, we create more than 90% of all historic digital data. By 2025 we expect AI to generate 160 zettabytes – with 80% of that unstructured data. Moore’s Law is an exponential, but as John Kelly points out, AI’s deep learning is driving its own exponential with performance/watt increasing 2.5X each year.

AI was the focus of SEMICON West’s Day 1 keynotes – and a common theme through much of the events programming. There was a common language in the keynotes by John Kelly, Gary Dickerson, and William Dally (Chief Scientist and SVP of Research NVIDIA), and others. We heard how AI is based on data, algorithms, and compute. I was inspired by these talks and for the potential for AI and the cognitive era.

Looking ahead, I believe data + algorithms + compute + machine learning = knowledge and cognition. My vision is that this AI knowledge and cognition will be the catalyst to create new modes of systems transformations that will usher in the next Industrial Revolution. As the 4th Industrial Revolution becomes a reality, I look forward to working with others in SEMI Think Tanks to imagine the 5th Industrial Revolution – and its opportunities for our industry. I believe that it will make our lives better, healthier, more prosperous, and more fulfilled.

A sentiment shared by many speakers at SEMICON West was – this is the most exciting time to be in the semiconductor manufacturing industry. Many wished they were just now starting in the industry as this is the most interesting inflection and transformation ever. There is a flood of new architectures, new materials, new equipment, new processes – and a new system-based design approach to enable the Cognitive Era. We, in hardware manufacturing, are in the driver’s seat for this incredible ride.

SEMI is working to help its members speed their time to better business results – and to take full advantage of the Cognitive Era and AI opportunity. At SEMICON West 2018, SEMI provided a broad and deep slate of program education and spotlighted AI expertise across the electronics manufacturing supply. In case you missed it, SEMI also provided

  • Seven keynotes and dozens of expert panelists
  • Semiconductor venture funding program – problems and solutions for the ecosystem
  • SEMI Smart Workforce Pavilion with over 600 students registered to learn about the industry
  • Smart Pavilions including Smart Manufacturing and Smart Automotive

SEMI highlighted the five key vertical application platforms where our industry needs to collaborate across the full supply chain and streamline the supply chain for efficiency. The five are: IoT, Smart Transportation, Smart Manufacturing, Smart MedTech, and Smart Data. These verticals drive huge business potential and are just one of the reasons that SEMICON West has become the gathering place of the extended electronics manufacturing supply chain.

With SEMI, together we can realize the potential of the coming Cognitive Era. SEMI members can advance the industry with SEMI collective action in Workforce Development, Advocacy (public policy and regulatory), Standards to synchronize the industry, and in the many SEMI technology communities and special interest groups – to increase the global industry’s rate of growth and overall level of prosperity. For more information, please visit www.semi.org; to become a member, please visit http://www.semi.org/en/become-member-join-semi.

Ajit Manocha is President and CEO of SEMI

Originally published on the SEMI blog.

In its recently released Mid-Year Update to The McClean Report 2018, IC Insights forecasts that the 2018-2022 global GDP and IC market correlation coefficient will reach 0.95, up from 0.88 in the 2010-2017 time period.  IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth through 2017, as well as its forecast through 2022, in Figure 1.

As shown, over the 2010-2017 timeframe, the correlation coefficient between worldwide GDP lgrowth and IC market growth was 0.88, a strong figure given that a perfect correlation is 1.0.  In the three decades previous to this timeperiod, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation (i.e., essentially no correlation) of -0.10 in the 1990s.

IC Insights believes that the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrate the maturing of the industry that is helping foster a closer correlation between worldwide GDP growth and IC market growth. Other factors include the strong movement to the fab-lite business model and a declining capex as a percent of sales ratio, all trends that are indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile market cycles over the long term.

In 2017, IC industry growth was greatly influenced by the “Capacity/Capital Spending Cycle Model” as the DRAM and NAND flash markets surged and served to drive total IC industry growth of 25%.  It would initially appear that the strong correlation coefficient between worldwide GDP growth and total IC market growth that had been evident from 2010 through 2016 had disappeared in 2017.  However, IC Insights does not believe that is the case.

When excluding the DRAM and NAND flash segments from the IC market in 2017, the remainder of the IC market displayed an 11% increase, which closely correlates to what would be expected given a worldwide GDP increase from 2.4% in 2016 to 3.1% in 2017.  Moreover, the three-point decline in the total IC market growth rate forecast for 2018, when excluding DRAM and NAND flash (from 11% in 2017 to 8% in 2018), is expected to mirror the slight decline expected for worldwide GDP growth this year as compared to last year.  Thus, excluding the amazing surge for the DRAM and NAND flash markets in 2017 and 2018, IC Insights believes that the trend toward an increasingly close correlation between total IC market growth and worldwide GDP growth is still largely intact.

Figure 1

 

Micron (Nasdaq:MU) and Intel today announced an update to their 3D XPoint™ joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019. Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.

The two companies will continue to manufacture memory based on 3D XPoint technology at the Intel-Micron Flash Technologies (IMFT) facility in Lehi, Utah.

“Micron has a strong track record of innovation with 40 years of world-leading expertise in memory technology development, and we will continue driving the next generations of 3D XPoint technology,” said Scott DeBoer, executive vice president of Technology Development at Micron. “We are excited about the products that we are developing based on this advanced technology which will allow our customers to take advantage of unique memory and storage capabilities. By developing 3D XPoint technology independently, Micron can better optimize the technology for our product roadmap while maximizing the benefits for our customers and shareholders.”

“Intel has developed a leadership position delivering a broad portfolio of Optane products across client and data center markets with strong support from our customers,” said Rob Crooke, senior vice president and general manager of Non-Volatile Memory Solutions Group at Intel Corporation. “Intel Optane’s direct connection to the world’s most advanced computing platforms is achieving breakthrough results in IT and consumer applications. We intend to build on this momentum and extend our leadership with Optane, which combined with our high-density 3D NAND technology, offer the best solutions for today’s computing and storage needs.”

Broadcom Inc. (NASDAQ: AVGO), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, and CA Technologies (NASDAQ: CA), one of the world’s leading providers of information technology (IT) management software and solutions, today announced that the companies have entered into a definitive agreement under which Broadcom has agreed to acquire CA to build one of the world’s leading infrastructure technology companies.

Under the terms of the agreement, which has been approved by the boards of directors of both companies, CA’s shareholders will receive $44.50 per share in cash. This represents a premium of approximately 20% to the closing price of CA common stock on July 11, 2018, the last trading day prior to the transaction announcement, and a premium of approximately 23% to CA’s volume-weighted average price (“VWAP”) for the last 30 trading days. The all-cash transaction represents an equity value of approximately $18.9 billion, and an enterprise value of approximately $18.4 billion.

Hock Tan, President and Chief Executive Officer of Broadcom, said, “This transaction represents an important building block as we create one of the world’s leading infrastructure technology companies. With its sizeable installed base of customers, CA is uniquely positioned across the growing and fragmented infrastructure software market, and its mainframe and enterprise software franchises will add to our portfolio of mission critical technology businesses. We intend to continue to strengthen these franchises to meet the growing demand for infrastructure software solutions.”

“We are excited to have reached this definitive agreement with Broadcom,” said Mike Gregoire, CA Technologies Chief Executive Officer. “This combination aligns our expertise in software with Broadcom’s leadership in the semiconductor industry. The benefits of this agreement extend to our shareholders who will receive a significant and immediate premium for their shares, as well as our employees who will join an organization that shares our values of innovation, collaboration and engineering excellence. We look forward to completing the transaction and ensuring a smooth transition.”

The transaction is expected to drive Broadcom’s long-term Adjusted EBITDA margins above 55% and be immediately accretive to Broadcom’s non-GAAP EPS. On a combined basis, Broadcom expects to have last twelve months non-GAAP revenues of approximately $23.9 billion and last twelve months non-GAAP Adjusted EBITDA of approximately $11.6 billion.

As a global leader in mainframe and enterprise software, CA’s solutions help organizations of all sizes develop, manage, and secure complex IT environments that increase productivity and enhance competitiveness. CA leverages its learnings and development expertise across its Mainframe and Enterprise Solutions businesses, resulting in cross enterprise, multi-platform support for customers. The majority of CA’s largest customers transact with CA across both its Mainframe and Enterprise Solutions portfolios. CA benefits from predictable and recurring revenues with the average duration of bookings exceeding three years. CA operates across 40 countries and currently holds more than 1,500 patents worldwide, with more than 950 patents pending.

By Pete Singer

In a keynote talk on Tuesday in the Yerba Buena theater, Dr. John E. Kelly, III, Senior Vice President, Cognitive Solutions and IBM Research, talked about how the era of Artificial Intelligence (AI) was upon us, and how it will dramatically the world. “This is an era of computing which is at a scale that will dwarf the previous era, in ways that will change all of our businesses and all of our industries, and all of our lives,” he said. “This will be another 50, 60 or more years of technology breakthrough innovation that will change the world.  This is the era that’s going to power our semiconductor industry forward. The number of opportunities is enormous.”

Dr. John E. Kelly, III, Senior Vice President, Cognitive Solutions and IBM Research

Kelly, with 40 years of experience in the industry, recalled how the first era of computing began with mechanical computers 100 years ago, and then transition into the programmable era of computing. In 1980, Kelly said “we were trying to stack two 16 kilobis DRAMs to get a 32 bit stack and we were trying to cram a thousand transistors into a microprocessor.” Microprocessors today have 15 billion transistors. “It’s been a heck of a ride,” he said.

IBM’s Summit is not only the biggest computer in the world, this is the smartest computer in the world, according to Kelly.

Kelly pointed to the power of exponentials, noting that Moore’s Law represented the first exponential and Metcalf’s Law — which says the value of the network increases as the square of the number of connected devices to the network – is the second exponential. Kelly said there’s no end to this second potential, as devices such as medical connected devices and Internet of thing devices get connected.

A third exponential is now upon us, Kelly said. “The core of this exponential is that data is doubling every 12 to 18 months. In fact, in some industries like healthcare, data is doubling every six months,” he said. The challenge is that the data is useless unless it can be analyzed. “Our computers are lousy in dealing with that large unstructured data and frankly there aren’t enough programmers in the world to deal with that explosion of data and extract value,” Kelly said. “The only way forward is through the use of machine learning and artificial intelligence to extract insights from that data.”

Kelly talked about IBM’s history of AI – teaching early system 600 machines to play checkers, beating chess grandmaster Gary Kasparov with Deep Blue, Watson’s Jeopardy wins and most recently, Watson Debater. That can “not only can answer questions but can listen to a person’s argument on something, reason and counter-argue in full natural language against that position in a full dialogue, continuously.”

What’s changed? “We continue to make advances in artificial intelligence, machine learning and deep learning algorithms that are just stunning,” Kelly said. “We are now able to learn over smaller and smaller amounts of data and translate that learning from one domain to another to another to another and start to get scale. Now is the time when this exponential is going to really explode.”

How does that equate to opportunity? Kelly said that on top of the existing $1.5-2B information technology industry, there’s another $2 trillion of decision support opportunity for artificial intelligence. “Literally every industry in the world, whether its industrial products, financial services, retail, every industry in the world is going to be impacted and transformed by this,” he said.

Quantum computing, which Kelly describe as a fourth exponential, is also coming which will in turn dwarf all of the previous ones. “Beyond AI, this is going to be the most important thing I’ve ever seen in my career. Quantum computing is a complete game changer,” he said.

The bad news? During his talk, Kelly sounded one cautionary note: “Companies that lead exponentials win. Companies that don’t lead, or even try to quickly follow, fail on exponential curves. Our industry is littered with examples of that,” he said.

IC Insights will release its 200+ page Mid-Year Update to the 2018 McClean Report later this month. The Mid-Year Update revises IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally published in The 2018 McClean Report issued in January of this year.

Figure 1 compares the estimated required capex needed to increase NAND flash bit volume shipments 40% per year, sourced from a chart from Micron’s 2018 Analyst and Investor Event in May of this year, versus the annual capex targeting the NAND flash market segment using IC Insights’ data. As shown, Micron believes that the industry capex needed to increase NAND flash bit volume production by 40% more than doubled from $9 billion in 2015 to $22 billion only two years later in 2017! This tremendous surge in required capital was driven by the move to 3D NAND from planar NAND since 3D NAND requires much more fab equipment and additional cleanroom space to process the additional layers of the device as compared to planar NAND.

Most of the five major NAND flash suppliers have stated that they believe that NAND bit volume demand growth will average about 40% per year over the next few years. Figure 1 shows that the capex needed to support a 40% increase in NAND bit volume shipments was exceeded by 27% last year and is forecast to exceed the amount needed by another 41% this year (NAND bit volume shipments increased 41% in 2017 but 1H18/1H17 bit volume shipments were up only 30%). As a result, it is no surprise that NAND flash prices have already softened in early 2018. Moreover, the pace of the softening is expected to pick up in the second half of this year and continue into 2019.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. With Samsung, SK Hynix, Micron, Intel, Toshiba/Western Digital/SanDisk, and XMC/Yangtze River Storage Technology all planning to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market), IC Insights believes that the risk for significantly overshooting 3D NAND flash market demand is very high and growing.

Figure 1

The development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

BY KIM YESS, Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Fan-out (FO) packaging is one of the most talked- about advanced packaging solutions for heterogeneous integration. Although it has been available for nearly a decade for the chips used in mobile devices, its popularity has spiked in the past two years, thanks to Apple’s adoption of TSMC’s integrated fan-out package-on-package (InFO PoP) for its A10 and A11 processors, and the Apple Watch. As a result, FO has quickly progressed to the mainstream, with outsourced semiconductor and test service providers (OSATs), foundries and integrated device manufacturers (IDMs) vying for market share.

What’s driving FO innovation?

According to Yole Développement, smartphone appli- cation processors are the main beneficiaries of high- density fan-out (HDFO)’s excellent performance and thin profile. As a result, as shown in FIGURE 1, the HDFO market was worth $500 million in 2017 and was predicted to exceed $1 billion if other players, namely Qualcomm, Samsung and Huawei switch to HDFO [1].

Jan Vardaman, TechSearch International, said Apple selected InFO PoP for its A10 processor because of power noise reduction and signal integrity improvement, in addition to being thin enough to enable a low-profile PoP solution as small as 15 x 15 mm.

In addition to HDFO, the market is growing for conventional FO, driven by new applications such as audio CODECs, power management ICs, radar modules and RF[2].

The automotive electronics market—particularly advanced driver assistance systems (ADAS) and autonomous vehicles—is also being explored as a viable application for FO because of the flexibility and fast time to market it provides, as well as the ability to adapt to new sensor system protocols.

Exploring new processes

In this race to provide the most reliable, highest-density solution, many manufacturing approaches have emerged. FO is not only becoming more versatile, it is also reaching high enough densities to offer a cost-effective alternative to 2.5D interposers. As the demand for FO increases, packaging processes are being explored in both the wafer and panel formats. This is driving a need for new and better-performing materials that address more stringent specifications to meet, for example, finer line and space requirements, as well as the improved elongation needed for advanced high-density FO.

Thanks to recent innovations in packaging materials, three new process approaches have been developed to bridge these gaps. One approach involves new carrier- assist release-layer materials for creation of the redistribution layer (RDL)-first/chip-last buildup processes. Another important development is an alternative to lithography dielectric patterning that uses laser-ablated dielectric materials. Lastly, an alternative to the molding process in the chip-first approach that uses a laminated die stencil and gap-fill materials is under development.

Carrier-assist release layer for chip-last FO

Low-density FO is built using a chip-first approach, which involves first placing the chips on a substrate wafer followed by over-mold to create a reconstituted wafer, with subsequent RDL and solder-ball placement. On the other hand, HDFO processes like TSMC’s InFO technology use a chip-last approach. Also known as RDL-first, this approach (with target features of ≤2 μm l/s) begins with a layer-by-layer buildup of the RDL on a carrier wafer, followed by die placement and over-mold.

Currently, manufacturers turn to permanent bonding, followed by backgrinding to remove the carrier wafer. This is because conventional temporary bond/debond materials cannot withstand the downstream RDL processes that subject the build-up layers to high temperatures and vacuum conditions, as well as harsh chemical environments. However, backgrinding is a destructive process, creating debris that can cause damage to the device itself.

The new approach uses neither a temporary nor a permanent bonding process. Instead, it utilizes a release layer on the carrier substrate to allow separation of the FO wafer from the carrier at the end of the process flow.

The challenge with this new method is designing a material that withstands high- temperature process steps as well as strong mechanical stresses without delaminating or distorting the reconstituted wafer. Additionally, the material must be adaptable to the new FO panel-level processes (FOPLP) along with existing round wafers, as the industry innovates in that direction.

Manufacturers are investigating the use of copper foil lamination, as an alternative to physical vapor deposition of the seed layer. The copper laminating process requires a material that is flexible enough to sufficiently laminate layers on top of the substrate, and that can be cured using UV radiation or heat to yield a structurally stable base that meets the thermomechanical and chemical resis- tance requirements of the build-up process.

Additionally, it must be releasable by ultraviolet(UV) laser ablation or other UV exposure. To meet these needs, a new class of so-called “triangle” polymeric materials has been conceived that have advantages over standard-application release layers because they are multi functional. Specifically, these “triangle” materials can be laminated, cured and debonded, adding flexibility to the carrier-assisted process (FIGURE 2).

Dielectric RDL patterning

Traditional RDL patterning uses a complicated, 24-step photolithography process that employs photosensitive dielectric materials and masks to create trace patterns, followed by Cu plating to route the signal from the chip out of the package to the solder balls. This process, developed with round wafers in mind, uses spin-coated dielectrics. Unfortunately, these lithography processes are too costly to utilize in innovative package designs that must meet the stringent requirements for most markets [3].

As the industry moves to HDFO and begins to investigate panel-level processes to reduce cost and improve yield, alternative patterning approaches are being developed that can achieve resolutions down to 5 μm with an ultimate goal of 2 μm l/s. Laser ablation is one alter- native to photolithography for creating finer-featured RDL patterns while achieving all these goals.

The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet processing. In addition, with excimer laser patterning technology, the industry gains a much wider choice of dielectric materials (photopatternable and non-photopatternable) to help achieve further reductions in manufacturing costs as well as enhancements in chip or package performance [4].

By using excimer laser ablation, many process steps and costly materials can be eliminated from the manufacturing flow, including resist coating, baking, developing and resist stripping and etching using harsh chemicals [5].

FIGURE 3 demonstrates the considerable cost savings of laser ablation over photolithography. Activity-based cost modeling was used to carry out the cost comparison between the two processes. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time, amount of labor and cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.

Laser-ablated patterning is a room-temperature process that works by using a dielectric material to build up RDL fixtures, and excimer and solid-state lasers to ablate the material and direct-write a pattern. Laser ablation allows for depth and side-wall angle control, making it possible to create feature sizes <5 μm. It also reduces chemical waste streams. Additionally, fewer steps, fast removal rates and high throughput lead to a lower-cost solution in comparison with traditional photolithography (Fig. 3).

Photosensitive dielectric materials often fall short of meeting the required mechanical and thermal properties, and therefore need a variety of process “work-arounds” that add to the cost of ownership. Alter- natively, non-photopatternable dielectric materials can be designed using a vast selection of chemical platforms, which improves the possibility of meeting the thermal and mechanical property requirements.

As with all new approaches, laser ablation is not without some challenges. Post-laser-ablation cleaning and debris removal, along with surface roughness as a result of the ablation step, need to be addressed. Additionally, the laser system needs to achieve a high ablation rate for high throughput. While the process costs of laser ablation are lower than photolithography, there is still a significant equipment capacity investment required to add laser tools to the manufacturing line. This may delay overcoming the most critical challenge: convincing the industry to embrace laser ablation patterning over conventional approaches.

Development of the dielectric material is ongoing to further push the resolution of laser-ablated materials. In addition to spin and spray coating, other deposition methods being investigated include slot-die coating, ink-jet printing, Vermeer coating, spray coating and laminate film.

Laminated polymeric die-stencil fill concept

Chip-first is the standard approach for conventional FO packages, including embedded wafer level ball grid arrays (eWLBs), redistributed chip packages (RCPs), M-Series and others. It calls for placing die into the mold compound before the RDL processing steps. One of the challenges of this approach that impacts final yield is the die shift that can occur during the RDL processes. Additionally, in multi-die FOWLP configurations that combine disparate technologies to essen- tially form a system-in-package (SiP), the dies may be of different sizes and heights. Additionally, the mismatch in coefficient of thermal expansion (CTE) between all of the materials involved leads to severe warpage of the reconstituted wafer.

A new carrier-based approach developed to combat this problem replaces the over-mold structure around the dies with a laminated die stencil (FIGURE 4). A release layer is first applied to a carrier, followed by a curable adhesive backing layer. Next, the die stencil film is laminated to the curable adhesive backing layer. The dies are then placed in the stencil openings and attached to the adhesive backing layer during thermal curing. The gaps between the dies and stencil are then filled with a flexible yet curable polymeric material, yielding a stable reconstituted substrate. This is followed by construction of the RDLs while still supported on the carrier. Finally, the reconsti- tuted substrate is released from the carrier.

The stencil can be fabricated as a sheet from a variety of high-temperature-stable thermoplastics including, for example, carbon-fiber-filled polyetheretherketone (PEEK), which has an in-plane CTE of <10 ppm/K.

The pre-formed cavities can be configured for different die sizes and types to fabricate SiP components. The curable adhesive backing layer is comparatively soft and tacky before it is cured. This property allows the die-stencil film to be laminated to the structure at low temperatures.

This process not only addresses the die shift issue that plagues the chip-first approach, it also enables varying levels of die thickness. When placed in the stencil, the polymeric material allows the dies to sink and adjusts itself within the stencil. Once the dies are set, the material is cured, which locks them in place. Additionally, the process offers high-temperature stability, better CTE matching for warpage control, and high throughput.

Summary and conclusion

Fan-out packaging is on track to be a game-changing advanced packaging technology that will enable heterogeneous integration architectures. Applications have already expanded beyond smartphones, with HDFO targeting emerging applications.

Substrate handling and RDL strategies will be increasingly important, if not critical, for both conventional and HDFO technologies. To this end, the development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

The gamut of application needs for wafer support includes simple thinning processes during the backside processing of ultrathin, 300-mm silicon wafers, as well as reconstituted substrates for RDL fabrication. In addition to new materials, novel manufacturing approaches are also needed to further optimize the FO process flow.

KIM YESS is Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Acknowledgements

The author would like to thank Amy Lujan, SavanSys, for her contribution to this article regarding activity- based cost modeling.

References

1. Yole Developpement, “Fan-out Packaging Confirms its Success Story,” 3D InCites, September 14, 2017.
2. P. Garrou, “ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications, and Market Growth,” Solid State Technology, October 2017.
3. H.Hichri,M.Arendt,andM.Gingerella,“Novel Process of RDL Formation for Advanced Packaging by Excimer Laser Ablation,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1733-1739. doi: 10.1109/ECTC.2016.225
4. H. Hichri, Ibid.
5. R. Zoberbier, M. Souter, “Laser Ablation, Emerging Patterning Technology for Advanced Packaging,” SUSS MicroTec Lithography GmbH, January 2010

Optimized stepping, based on parallel analysis of die placement errors and prediction of overlay errors, can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The productivity benefits of optimized stepping are demonstrated using a test reticle with known die placement errors.

KEITH BEST, Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Fan out wafer and panel level packaging (FOWLP/ FOPLP) processes place individual known good die on reconstituted wafer (round) or panel (rectangular) substrates, providing more space between die than the original wafer. The additional space is used to expand (fanout) the die’s I/O connections in order to create a pad array large enough to accommodate solder balls that will connect the die to the end-use substrate.The processes used to create these redistribution layers (RDL) are similar to wafer fabrication processes, using patterns defined by photolithography, with feature sizes typically ranging from a few micrometers to tens of micrometers. The placement and reconstitution molding processes introduce significant die placement errors that must be corrected in the photolithography process to ensure accurate overlay registration among the multiple vias and distribution layers that are built up to form the RDL. The errors can be measured on the lithography tool, but this significantly impacts throughput as the measurement process for each die may take as much or more time than the exposure itself.

Current best-practice methods employ an external metrology system to measure the displacement of each die. This metrology data is converted into a stepper correction file that is sent to the lithography stepper tool, eliminating the need to measure displacement on the stepper and more than doubling stepper throughput. An important enhancement to this method, optimized stepping, varies the number of die per exposure based on a predictive yield analysis of the displacement measurements, potentially multiplying throughput 20X or more. Results obtained using a test reticle that includes intentionally displaced die pads, vias, and RDL features typical of an FOWLP/FOPLP process confirm the validity of the approach.

Introduction

Die placements on reconstituted wafer or panel substrates include translational and rotational placement errors. The pick and place process itself introduces initial error. Additional error is created in the mold process and by instability of the mold compound through repeated processing cycles. As a result, the position of the die must be measured before each exposure in the lithog- raphy system to ensure sufficient registration with the underlying layer.

Displacement errors can be measured in the lithography tool, but the measurements are slow, typically taking as much time as the exposure. Moving the measurement to a separate system and feeding corrections to the stepper can double throughput.

Optimized stepping adds predictive yield analysis to the external measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold. FIGURE 1 illustrates the exposure/measurement loop. The measurement and analysis are repeated after each layer is exposed, calculating a new set of corrections. In addition to corrections, the software engine analyzes the displacement errors to predict yield (based on a user desig- nated limit for acceptable registration error) for multiple die exposure fields of varying sizes. The method requires tight integration of the stepper and measurement system with the controlling software.

With RDL features currently reaching sizes as small as 2μm, die placement measurements and pattern overlay registration requirements are also continuing to tighten. The speed of the measurement/correction/prediction calculation for each wafer/panel is also an important consideration. It must be faster than the exposure time to avoid becoming the throughput limiting step. Note that this requirement refers to the total exposure for multiple die per field which can be much less than the time needed to expose each die individually. The metrology system used in this work (Firefly system, Rudolph Technologies) can meet these challenges and measure placement errors for >5,000 die on a 510mm x 515mm panel in less than 10 minutes.

The stepper must be able to accept externally generated corrections for translation, rotation, and magnification.

It must also have a large exposure field and the ability to automatically select different images from the reticle (masking blades), changing the size of the field for each exposure. The stepper used in this work was the JetStep system from Rudolph Technologies.

The third critical piece of the optimized stepping loop is the software engine (Discover software, Rudolph Technol- ogies) which calculates displacement corrections and predicts yield for various multi-die exposure configura- tions. It also enables statistical process control (SPC) and controls genealogy.

Balancing yield and throughput

Optimized stepping uses a reticle that includes multiple exposure fields each comprising die arrays of different sizes. In FIGURE 2 the arrays range from a single die to an 8 X 8 array of 64 die. On a wafer containing random displacement errors, the smallest overlay error will be achieved by aligning the exposure pattern for each die individually. However, this accuracy comes at a high cost of reduced throughput. Optimized stepping analyzes the measured displacement errors and calculates the number of die that will meet a designated overlay error limit for various field sizes. It then selects the combination of fields that maximizes throughput. In operation, the stepper automatically selects the correct reticle image and adjusts the field size to expose the selected array.

The yield prediction algorithm (FIGURE 3) uses a recursive splitting procedure that initially predicts yield for the largest available field. If the prediction does not meet user-defined yield requirements, it splits the field and re-evaluates the prediction, repeating this cycle for decreasing field sizes until all exposures yield satisfactory results. The user designates an aggressiveness factor (larger values mean more aggressive splits) and specifies yield requirements in an exposure shot pyramid that determines the number of failures allowed for each available field size.

Results

Optimized stepping was evaluated using a test reticle with multiple field sizes containing die that included pads, vias and RDL structures typical of FOWLP/FOPLP. The patterns included predefined offsets in some of the structures for feed forward measurement testing. Application of the corrections calculated from the die placement error measurements yielded overlay errors of < +/-3μm (FIGURE 4).

Productivity vs. yield

FIGURE 5 illustrates the potential benefits of optimized stepping applied to a panel process. In the example the panel contains approximately 4,500 die. A conventional serial process, with placement errors measured on the stepper, takes a little over six hours, including three hours for measurement and three hours for exposure. Making the measurements outside the stepper in parallel with the exposure halves the cycle time per panel to three hours, and the exposure time becomes the throughput limiting step. The third case is optimized for productivity, using larger field sizes and more relaxed yield requirements. It reduces cycle time to less than 10 minutes. The final case balances throughput against more stringent yield require- ments and results slightly higher cycle times that are still nearly an order of magnitude shorter than the conventional serial process of the first case.

Conclusion

Optimized stepping can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The method also provides a means to balance productivity (throughput) against yield, adding an extra dimension of flexibility for optimizing profitability. Optimized stepping requires a stepper that can use externally calculated corrections and automatically change field size and reticle position. The metrology system must have sufficient accuracy and speed (faster than the accelerated exposure time). The control software must be able to predict yields based on measured displacement errors and control the stepper. Using a test reticle with known displacement errors, we have verified the accuracy of the metrology system and correction procedures and demonstrated the productivity benefits of optimized stepping.

KEITH BEST is Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

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