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Historically, the DRAM market has been the most volatile of the major IC product segments.  A good example of this was displayed over the past two years when the DRAM market declined 8% in 2016 only to surge by 77% in 2017! The March Update to the 2018 McClean Report (to be released later this month) will fully detail IC Insights’ latest forecast for the 2018 DRAM and total IC markets.

In the 34-year period from 1978-2012, the DRAM price-per-bit declined by an average annual rate of 33%. However, from 2012 through 2017, the average DRAM price-per-bit decline was only 3% per year! Moreover, the 47% full-year 2017 jump in the price-per-bit of DRAM was the largest annual increase since 1978, surpassing the previous high of 45% registered 30 years ago in 1988!

In 2017, DRAM bit volume growth was 20%, half the 40% rate of increase registered in 2016.  For 2018, each of the three major DRAM producers (e.g., Samsung, SK Hynix, and Micron) have stated that they expect DRAM bit volume growth to once again be about 20%.  However, as shown in Figure 1, monthly year-over-year DRAM bit volume growth averaged only 13% over the nine-month period of May 2017 through January 2018.

Figure 1 also plots the monthly price-per-Gb of DRAM from January of 2017 through January of 2018.  As shown, the DRAM price-per-Gb has been on a steep rise, with prices being 47% higher in January 2018 as compared to one year earlier in January 2017.  There is little doubt that electronic system manufacturers are currently scrambling to adjust and adapt to the skyrocketing cost of memory.

DRAM is usually considered a commodity like oil.  Like most commodities, there is elasticity of demand associated with the product.  For example, when oil prices are low, many consumers purchase big SUVs, with little concern for the vehicle’s miles-per-gallon efficiency.  However, when oil prices are high, consumers typically look toward smaller or alternative energy (e.g., hybrid or fully electric) options.

Figure 1

Figure 1

While difficult to precisely measure, it is IC Insights’ opinion that DRAM bit volume usage is also affected by elasticity, whereby increased costs inhibit demand and lower costs expand usage and open up new applications.  As shown in Figure 1, the correlation coefficient between the DRAM price-per-bit and the year-over-year bit volume increase from January 2017 through January 2018 was a strong -0.88 (a perfect correlation between two factors moving in the opposite direction would be -1.0).  Thus, while system manufacturers are not scaling back DRAM usage in systems currently shipping, there have been numerous rumors of some smartphone producers scaling back DRAM in next-generation models (i.e., incorporating 4GB of DRAM per smartphone instead of 5GB).

In 2018, IC Insights believes that the major DRAM suppliers will be walking a fine line between making their shareholders even happier than they are right now and further alienating their customer base.  If, and it is a BIG if, the startup Chinese DRAM producers can field a competitive product over the next couple of years, DRAM users could flock to these new suppliers in an attempt to get out from under the crushing price increases now being thrust upon them—with the “payback” to the current major DRAM suppliers being severe.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $37.6 billion for the month of January 2018, an increase of 22.7 percent compared to the January 2017 total of $30.6 billion. Global sales in January were 1.0 percent lower than the December 2017 total of $38.0 billion, reflecting normal seasonal market trends. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“After notching its highest-ever annual sales in 2017, the global semiconductor industry is off to a strong and promising start to 2018, posting its highest-ever January sales and 18th consecutive month of year-to-year sales increases,” said John Neuffer, president and CEO, Semiconductor Industry Association. “All major regional markets saw double-digit growth compared to last year, with the Americas leading the away with year-to-year growth of more than 40 percent. With year-to-year sales also up across all major semiconductor product categories, the global market is well-positioned for a strong start to 2018.”

Year-to-year sales increased substantially across all regions: the Americas (40.6 percent), Europe (19.9 percent), Asia Pacific/All Other (18.6 percent), China, (18.3 percent), and Japan (15.1 percent). Month-to-month sales increased slightly in Europe (0.9 percent), held flat in China, but fell somewhat in Asia Pacific/All Other (-0.6 percent), Japan (-1.0 percent), and the Americas (-3.6 percent).

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Jan 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.95

8.63

-3.6%

Europe

3.37

3.40

0.9%

Japan

3.24

3.21

-1.0%

China

12.01

12.01

0.0%

Asia Pacific/All Other

10.41

10.35

-0.6%

Total

37.99

37.59

-1.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

6.14

8.63

40.6%

Europe

2.84

3.40

19.9%

Japan

2.79

3.21

15.1%

China

10.16

12.01

18.3%

Asia Pacific/All Other

8.73

10.35

18.6%

Total

30.64

37.59

22.7%

Three-Month-Moving Average Sales

Market

Aug/Sep/Oct

Nov/Dec/Jan

% Change

Americas

8.54

8.63

1.1%

Europe

3.36

3.40

1.1%

Japan

3.20

3.21

0.3%

China

11.65

12.01

3.1%

Asia Pacific/All Other

10.33

10.35

0.1%

Total

37.09

37.59

1.4%

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Enabling the AI Era with Materials Engineering

Screen Shot 2018-03-05 at 12.24.49 PMPrabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials

A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of “Smart Everything” from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live

Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.

In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.

In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.

Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.

In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.

3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.

In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.

BY SYAHIRAH MD ZULKIFLI, BERNICE ZEE AND WEN QIU, Advanced Micro Devices, Singapore; ALLEN GU, ZEISS, Pleasanton, CA

3D integration and packaging has challenged failure analysis (FA) techniques and workflows due to the high complexity of multichip architectures, the large variety of materials, and small form factors in highly miniaturized devices [1]. The drive toward die stacking with High Bandwidth Memory (HBM) allows the ability to move higher bandwidth closer to the CPU and offers an oppor- tunity to significantly expand memory capacity and maximize local DRAM storage for high throughput in the data center. However, the integration of HBM results in more complex electrical communications, due to the emerging use of a physical layer (PHY) design to connect the chip and subsystems. FIGURE 1 shows the schematic of a 2.5D stacked die package designed so that some HBM μbumps are electrically connected to the main CPU through a PHY connection. In general, the HBM and CPU signal length needs to be minimized to reduce drive strength requirements and power consumption at the PHY.

Screen Shot 2018-03-01 at 11.46.34 AM

This requirement poses new challenges in FA fault isolation. A traditional FA workflow using electrical fault isolation (EFI) techniques to isolate the defect becomes less effective for chip-to-chip interconnects because there are no BGA balls for electrically probing the μbumps at the PHY. As a result, new defect localization techniques and FA flows must be investigated.

XRM theory

X-ray imaging is widely employed for non-destructive FA inspection because it can explore interior structures of chips and packages, such as solder balls, silver paste and lead frames. Thus, many morphological failures, such as solder-ball crack/burn-out and bumping failure inside IC packages, can be imaged and analyzed through X-ray tools. In 2D X-ray inspection, an X-ray irradiates samples and a 2D detector utilizes the projection shadow to construct 2D images. This technique, however, is not adequate for revealing true 3D structures since it projects 3D structures onto a 2D plane. As a result, important information, such as internal faulty regions of electronic packages, may remain hidden. This disadvantage can be overcome by using 3D X-ray microscopic technology, derived from the original computed tomography (CT) technique. In a 3D imaging system, a series of 2D X-ray images are captured at different angles while a sample rotates.

These 2D images are used to reconstruct 3D X-ray tomographic slices using mathematic models and algorithms. The spatial resolution of the imaging technique can be improved through the integration of an optical microscopy system. This improved technology is called 3D X-ray microscopy (XRM) [2]. FIGURE 2 shows an example 3D XRM image for a stacked die. The image clearly shows the internal structures – including the TSV, C4 bumps and μbump of the electronic components – without physically damaging or altering the sample. The high resolution and quality shown here are essential to inspect small structural defects inside electronic devices. With its non-destructive nature, 3D XRM has been useful for non-destructive FA for IC packaging devices.

Screen Shot 2018-03-01 at 11.46.42 AM

Failure analysis approach

The purpose of an FA workflow is to have a sequence of analytical techniques that can help to effectively and quickly isolate the failure and determine the root cause. Typical FA workflows for flip-chip devices consist of non-destructive techniques such as C-Mode scanning acoustic microscopy (C-SAM) and time domain reflectometry (TDR) to isolate the failure, followed by destructive physical failure analysis (PFA). However, there are limitations to each of these techniques when posed with the failure analysis of a more complex stacked die package.

C-SAM allows the inspection of abnormal bumps, delamination and any mechanical failure. A focused soundwave is directed from a transducer to a small point on a target object and is reflected when it encounters a defect, inhomogeneity or a boundary inside the material. The transducer transforms the reflected sound pulses into electromagnetic pulses, which are displayed as pixels with defined grey values thereby creating an image [3]. However, stacked die composed of a combination of multiple thin layers may complicate C-SAM analysis. This is because the thin layers have smaller spacing between the adjacent interface, and shorter delay times for ultrasound traveling from one interface to another. Therefore, failures between the die and die attach may not be easily detected, and false readings may even be expected.

TDR is an electrical fault isolation tool that enables failure localization through electrical signal data. The TDR signal carries the impedance load information of electrical circuitry; hence, the reflected signals show the discontinuity location that has caused the mismatch of impedance. In-depth theory on TDR is further discussed in Chin et al [4]. However, TDR can only estimate where the failure lies, whether it is in the substrate, die or interposer region. To pin point the exact location within the area of failure is difficult, due to limitations in separating the various small structures through the TDR signal. Additionally, some of the pulse power is reflected for every impedance change, posing challenges regarding unique defect isolation and signal complexity – especially for stacked die [5]. In cases where the failure pins reside in the HBM μbump region, no BGA ball out is available to probe and send an electrical pulse through.

Physical Failure Analysis (PFA) is a destructive method to find and image the failure once non-destructive fault isolation is complete. PFA can be done both mechanically and by focused ion beam (FIB). For stacked dies, FIB is predominantly used to image smaller interconnect structures such as TSVs and μbumps. However, the drawback is that the success of documenting the failure through PFA is largely dependent on how well the non-destructive FA techniques can isolate the failure region. Without good clear fault isolation direction, the failure region might be destroyed or missed during the PFA process, and thus no root cause can be derived.

The integration of XRM into the FA flow can help to overcome the limitations of the various analysis techniques to isolate the failure. It is a great advantage to image small structures and failures with the high spatial resolution and contrast provided by XRM and without destroying the sample. For failures in stacked die, XRM can be integrated into the FA flow for further fault isolation with high accuracy. The visualization of defects and failed material prior to destructive analysis increases FA success rates. However, the trade-off for imaging small defects at high resolution is time. For stacked die failures, C-SAM and TDR can first be performed to isolate the region of failure. With a known smaller region of interest to focus on, the time taken for XRM to visualize the area at high resolution is significantly reduced.

In cases where failures are identified in the HBM μbump, XRM is an effective technique to isolate the failure through 3D defect visualization. With the failure region isolated, XRM can then act as a guide to perform further PFA. Following are three case studies where XRM was used to image HBM packages with stacked dies.

Case studies

In the first case study, we explore the application of XRM as the primary means of defect visualization where other non-destructive testing and FA techniques are not possible. An open failure was reported for non-underfilled stacked die packages during a chip package interaction (CPI) study. The suspected open location was within the μbump joints at the HBM stack/ interposer interface. The initial approach exposed the bottom-most die of the HBM stack, followed by FIB cross-sectioning at the specified location. Performing the destructive approach to visualize the integrity of μbump joints in non-underfilled stack die packages was virtually impossible due to the fragility of silicon. The absence of underfill (UF) means that the HBM does not properly adhere to the interposer and is susceptible to peel off. In addition, there was no medium to release shear stresses experienced by the μbump joints upon bending stresses, which could not be absorbed by the package. As seen in FIGURE 3, parallel lapping of the HBM stack without UF caused die crack and peeling.

Screen Shot 2018-03-01 at 11.46.50 AM

Consequently, to avoid aggravating the damage on the sample, 3D XRM was performed to inspect and visualize the suspected location using a 0.7μm/voxel and 4X objective without any sample preparation. FIGURE 4 shows an example virtual slice where the micro-cracks throughout the row of μbump joints are visualized. The micro-cracks are measured a few microns wide. It is worth noting that the micro-cracks were visible with a short scan time of 1.5 hrs.

Screen Shot 2018-03-01 at 11.47.00 AM

With the critical defect information in 3D, PFA was performed on a sample that was underfilled to facilitate ease of sample preparation. SEM images in FIGURE 5 validated the existence of μbump micro-cracks observed by 3D XRM inspection.

In the second case study, the 3D XRM technique was applied to a stacked die package with a failure at a specific HBM/XPU physical interface (PHY) μbump connection. This μbump connection provides specific communication between the HBM stack and XPU die, and there is no package BGA ball out to enable electrical probing. Accordingly, it was not possible to verify if the failure type was an open or short. In addition, there was no means to determine if the failure was at the HBM or XPU die. Since defects from previous lots were open failures at the PHY μbump of the HBM, 3D XRM was performed at the suspected HBM open region using a 0.85μm/voxel and 4X objective.

As no defect was observed, XRM was then applied to the corresponding XPU PHY μbump. Contrary to the anticipated μbump open, a short was observed between two μbumps as shown in FIGURES 6a and 6b.

Screen Shot 2018-03-01 at 11.47.22 AM Screen Shot 2018-03-01 at 11.47.28 AM

 

The μbump short resulted from a solder extrusion bridging two adjacent μbumps. If 3D XRM had not been performed, a blind physical cross-section likely would have been performed on the initially suspected open region. As a result, the actual failure region may have been missed and/or destroyed.

In the final case study, an open failure was reported at a signal pin of a stack die package. As per the traditional FA flow, C-SAM and TDR techniques were applied to isolate the fault. C-SAM results showed an anomaly, and TDR suggested an open in the substrate as demonstrated in FIGURE 7a and 7b respectively.

Screen Shot 2018-03-01 at 11.47.10 AM Screen Shot 2018-03-01 at 11.47.16 AM

To verify the observations made by C-SAM and TDR non-destructive techniques, 3D XRM was performed using a 0.80μm/voxel and 4X objective at the region of

FIGURE 8 revealed a crack between the failure C4 bump and associated TSV. A physical cross-section was performed and the passivation cracks between the TSV and interposer backside redistribution layer (RDL) was observed as shown in FIGURE 9.

Screen Shot 2018-03-01 at 11.47.35 AM

In this case, 3D XRM provided 3D information for the FA engineer to focus on. Without the visual knowledge on the defect’s nature and location, the defect would have been missed during PFA.

Summary and conclusions

3D integration and packaging have brought about new challenges for effective defect localization, especially when traditional electrical fault isolation is not possible. 3D XRM enables 3D tomographic imaging of internal structures in chips, interconnects and packages, providing 3D structural information of failure areas without the need to destroy the sample. 3D XRM is a vital and powerful tool that helps failure analysis engineers to overcome FA challenges for novel 3D stacked-die packages.

Acknowledgement

This article is based on a paper that was presented at the 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017).

References

  1. F. Altmann and M. Petzold, “Innovative Failure Analysis Techniques for 3-D Packaging Developments,” IEEE Design & Test, Vol. 33, No. 3, pp. 46-55, June 2016.
  2. C. Y. Liu, P. S. Kuo, C. H. Chu, A. Gu and J. Yoon, “High resolution 3D X-ray microscopy for streamlined failure analysis workflow,” 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 216-219.
  3. M. Yazdan Mehr et al., “An overview of scanning acoustic microscope, a reliable method for non-destructive failure analysis of microelectronic components,” 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro- electronics and Microsystems, Budapest, 2015, pp.1-4.
  4. J. M. Chin et al., “Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview,” Microelectronics Reliability, Vol. 51, Issue 9, pp. 1440-8, Nov. 2011.
  5. W. Yuan et al., “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” 2007 8th International Conference on Electronic Packaging Technology, Shanghai, 2007, pp. 1-5.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.

The success and proliferation of integrated circuits has largely hinged on the ability of IC manufacturers to continue offering more performance and functionality for the money.  Driving down the cost of ICs (on a per-function or per-performance basis) is inescapably tied to a growing arsenal of technologies and wafer-fab manufacturing disciplines as mainstream CMOS processes reach their theoretical, practical, and economic limits. Among the many levers being pulled by IC designers and manufacturers are: feature-size reductions, introduction of new materials and transistor structures, migration to larger-diameter silicon wafers, higher throughput in fab equipment, increased factory automation, three-dimensional integration of circuitry and chips, and advanced IC packaging and holistic system-driven design approaches.

For logic-oriented processes, companies are fabricating leading-edge devices such as high-performance microprocessors, low-power application processors, and other advanced logic devices using the 14nm and 10nm generations (Figure 1).  There is more variety than ever among the processes companies offer, making it challenging to compare them in a fair and useful way.  Moreover, “plus” or derivative versions of each process generation and half steps between major nodes have become regular occurrences.

For five decades, the industry has enjoyed exponential improvements in the productivity and performance of integrated circuit technology.  While the industry has continued to surmount obstacles put in front of it, the barriers are getting bigger.  Feature size reduction, wafer diameter increases, and yield improvement all have physical or statistical limits, or more commonly…economic limits.  Therefore, IC companies continue to wring every bit of productivity out of existing processes before looking to major technological advances to solve problems.

The growing design and manufacturing challenges and costs have divided the integrated circuit world into the haves and have-nots.  In the June 1999 Update to The McClean Report, IC Insights first described its “Inverted Pyramid” theory, where it was stated that the IC industry was in the early stages of a new era characterized by dramatic restructuring and change.  It was stated that the marketshare makeup in various IC product segments was becoming “top heavy,” with the shares held by top producers leaving very little room for remaining competitors. Although the Update described the emerging inverted pyramid phenomenon from a marketshare perspective, an analogous trend can be seen regarding IC process development and fabrication capabilities. The industry has evolved to the point where only a very small group of companies can develop leading-edge process technologies and fabricate leading-edge ICs.

Figure 1

Figure 1

CEA-Leti’s chief scientist today issued a forward-looking call to action for the microelectronics industry to create a radically new, digital-communication architecture for the Internet of Things in which “a great deal of analytics processing occurs at the edge and at the end devices instead of in the Cloud”.

Delivering a keynote presentation at the kickoff of ISSCC 2018, Barbara De Salvo said this architecture will include human-brain inspired hardware coupled to new computing paradigms and algorithms that “will allow for distributed intelligence over the whole IoT network, all-the-way down to ultralow-power end-devices.”

“We are entering a new era where artificial-intelligence systems are … shaping the future world,” said De Salvo, who also is Leti’s scientific director. “With the end of Moore’s Law in sight, transformative approaches are needed to address the enduring power-efficiency issues of traditional computing architectures.”

The potential efficiencies of processing data at the edge of networks – e.g. by small computers located near IoT-connected devices – rather than at distant data centers or the Cloud are increasingly cited as long-term goals for the Internet of Things. But the challenges to realizing this vision are formidable. For example, IoT battery-powered devices lack both processing power to analyze the data they receive and a power source that would support data processing.

To break through these barriers, De Salvo called for a “holistic research approach to the development of low-power architectures inspired by the human brain, where process development and integration, circuit design, system architecture and learning algorithms are simultaneously optimized.” She envisions a future in which optimized neuromorphic hardware will be implemented as a highly promising solution for future ultralow-power cognitive systems that extend well beyond the IoT.

“Emerging technologies such as advanced CMOS, 3D technologies, emerging resistive memories, and silicon photonics, coupled with novel brain-inspired paradigms, such as spike-coding and spike-time-dependent-plasticity, have extraordinary potential to provide intelligent features in hardware, approaching the way knowledge is created and processed in the human brain,” she said.

De Salvo’s presentation, “Brain-Inspired Technologies: Towards Chips that Think”, included summaries of key research findings in a variety of fields that will play a role in developing brain-inspired technologies for computing and data-handling requirements of a “hyperconnected” world.

IC industry wafer capacity, specifically in the memory segment, was inadequate to meet demand throughout 2017. However, with Samsung, SK Hynix, Micron, Intel, Toshiba/WD, and XMC/Yangtze River Storage Technology planning to significantly ramp up 3D NAND flash capacity over the next few years, and Samsung and SK Hynix boosting DRAM capacity this year and next, what does this mean for total industry capacity growth?  In its 2018-2022 Global Wafer Capacity report, IC Insights shows that new manufacturing lines are expected to boost industry capacity 8% in both 2018 and 2019 (Figure 1). From 2017-2022, annual growth in IC industry capacity is forecast to average 6.0% compared to 4.8% average growth from 2012-2017.

annual wafer trends

Figure 1

Large swings in the addition or contraction of wafer capacity by the industry, as a whole, appear to be moderating. Since 2010, annual changes in wafer capacity volume have been in the relatively narrow range of 2-8%, with the largest year-to-year difference being just three percentage points.  This suggests that IC manufacturers are better today than in years past about trying to match supply with demand.  It’s still an incredibly difficult task for companies to gauge how much capacity will be needed to meet demand from customers, especially given the time it takes a company to move from the decision to build a new fab to that fab being ready for mass production.

Many companies, DRAM and NAND flash suppliers in particular, have become much more active with new fab construction and expansion projects at existing fabs.  This surge in activity comes after four years (2014-2017) when capacity growth lagged wafer start volume increases.  During the past few years, IC producers have worked to increase utilization rates from the low levels in 2012-2013.

If all the new fab capacity expected to be brought on-line in 2019 happens as planned, the volume of capacity added that year will approach the record set in 2007.  Figure 2 shows more that 18 million wafers per year of new capacity is expected to be added in 2019, and this number even assumes some of the massive DRAM and NAND fabs being built by Chinese companies will not be carried out quite as aggressively as has been advertised.  IC Insights believes that construction of these China-owned fabs is progressing slower than planned.

Figure 2

Figure 2

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the global semiconductor industry posted sales totaling $412.2 billion in 2017, the industry’s highest-ever annual sales and an increase of 21.6 percent compared to the 2016 total. Global sales for the month of December 2017 reached $38.0 billion, an increase of 22.5 percent over the December 2016 total and 0.8 percent more than the previous month’s total. Fourth-quarter sales of $114.0 billion were 22.5 percent higher than the total from the fourth quarter of 2016 and 5.7 percent more than the third quarter of 2017. Global sales during the fourth quarter of 2017 and during December 2017 were the industry’s highest-ever quarterly and monthly sales, respectively. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

Worldwide semiconductor revenues, year-to-year percent change

Worldwide semiconductor revenues, year-to-year percent change

“As semiconductors have become more heavily embedded in an ever-increasing number of products – from cars to coffee makers – and nascent technologies like artificial intelligence, virtual reality, and the Internet of Things have emerged, global demand for semiconductors has increased, leading to landmark sales in 2017 and a bright outlook for the long term,” said John Neuffer, SIA president and CEO. “The global market experienced across-the-board growth in 2017, with double-digit sales increases in every regional market and nearly all major product categories. We expect the market to grow more modestly in 2018.”

Several semiconductor product segments stood out in 2017. Memory was the largest semiconductor category by sales with $124.0 billion in 2017, and the fastest growing, with sales increasing 61.5 percent. Within the memory category, sales of DRAM products increased 76.8 percent and sales of NAND flash products increased 47.5 percent. Logic ($102.2 billion) and micro-ICs ($63.9 billion) – a category that includes microprocessors – rounded out the top three product categories in terms of total sales. Other fast-growing product categories in 2017 included rectifiers (18.3 percent), diodes (16.4 percent), and sensors and actuators (16.2 percent). Even without sales of memory products, sales of all other products combined increased by nearly 10 percent in 2017.

Annual sales increased substantially across all regions: the Americas (35.0 percent), China (22.2 percent), Europe (17.1 percent), Asia Pacific/All Other (16.4 percent), and Japan (13.3 percent). The Americas market also led the way in growth for the month of December 2017, with sales up 41.4 percent year-to-year and 2.1 percent month-to-month. Next were Europe (20.2 percent/-1.6 percent), China (18.1 percent/1.0 percent), Asia Pacific/All Other (17.4 percent/0.2 percent), and Japan (14.0 percent/0.9 percent).

“A strong semiconductor industry is foundational to America’s economic strength, national security, and global technology leadership,” said Neuffer. “We urge Congress and the Trump Administration to enact polices in 2018 that promote U.S. innovation and allow American businesses to compete on a more level playing field with our counterparts overseas. We look forward to working with policymakers in the year ahead to further strengthen the semiconductor industry, the broader tech sector, and our economy.”

By Emmy Yi, SEMI Taiwan 

Driven by emerging technologies like Artificial Intelligence (AI), Internet of Things (IoT), machine learning and big data, the digital transformation has become an irreversible trend for the electronics manufacturing industry. The global market for smart manufacturing and smart factory technologies is expected to reach US$250 billion in 2018.

“The semiconductor manufacturing process has reached its downscaling limit, making outstanding manufacturing capabilities indispensable for corporations to stay competitive,” said Ana Li, Director of Outreach and Member Service at SEMI. “Advances in cloud computing, data processing, and system integration technologies will be key to driving the broad adoption of smart manufacturing.”

ompany representatives shared insights and successes in manufacturing digitalization.

ompany representatives shared insights and successes in manufacturing digitalization.

To help semiconductor manufacturing companies navigate the digital transformation, SEMI recently held the AI and Smart Manufacturing Forum, a gathering of industry professionals from Microsoft, Stark Technology, Advantech, ISCOM, and Tectura to examine technology trends and smart manufacturing opportunities and challenges. The nearly 100 guests at the forum also included industry veterans from TSMC, ASE, Siliconware, Micron, and AUO. Following are key takeaways from the forum:

1)    Smart manufacturing is the key for digital transformation
Industry 4.0 is all about using automation to better understand customer needs and help drive efficiency improvements that enable better strategic manufacturing decisions. For electronics manufacturers, thriving in the digital transformation should begin with research and development focused on optimizing processes, developing innovative business models, and analyzing data in ways that support their customers’ business values and objectives. Digitization is also crucial for manufacturers to target the right client base, increase productivity, optimize operations and create new revenue opportunities.

2)    Powerful data analysis capabilities will enable manufacturing digitalization

As product development focuses more on smaller production volumes, companies need a powerful data analysis software to accelerate decision-making and problem-solving processes, enhance integration across different types of equipment, and improve management efficiency across enterprise resources including business operations, marketing, and customer service.

3)    The digital transformation will fuel revenue growth
Connectivity and data analysis, the two essential concepts of smart manufacturing, are not only essential for companies to improve facility management efficiency and production line planning but also key for maintaining healthy revenue growth.

“With our more than 130 semiconductor manufacturers and long fab history, Taiwan is in a strong position to help the industry evolve manufacturing to support the explosion of new data-intensive technologies,” said Chen-Wei Chiang, the Senior Specialist at the Taichung City Government’s Economic Development Bureau. “We look forward to working with SEMI to help manufacturers realize the full potential of smart manufacturing.”

With the advent of new data-intensive technologies including AI and IoT, advanced manufacturing processes that improve product yield rates and reduce production costs will become even more important for manufacturers to remain competitive. SEMI Taiwan will continue to assemble representatives from the industry, government, academia and research to examine critical topics in smart manufacturing. To learn more, please contact Emmy Yi, SEMI Taiwan, at
[email protected] or +886.3.560.1777 #205.