Tag Archives: letter-dd-tech

By David W. Price, Douglas G. Sutherland, Jay Rathert, John McCormack and Barry Saville

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the third in a series on process control strategies for automotive semiconductor devices. For this article, we are pleased to include insights from our colleagues at KLA-Tencor, John McCormack and Barry Saville. 

Semiconductors continue to grow in importance in the automotive supply chain, requiring IC manufacturers to adapt their processes to produce chips that meet automotive quality standards. The first article in this series1 focused on the fact that the same types of IC manufacturing defects that cause yield loss also cause poor chip reliability and can lead to premature failures in the field. To achieve the high reliability required in automotive ICs, additional effort must be taken to ensure that sources of defects are eliminated in the manufacturing process. The second article in this series2 outlined strategies, such as frequent tool monitoring and a continuous improvement program, that reduce the number of defects added at each step in the IC manufacturing process. This article explores how to drive tool monitoring to a higher level of performance in order to help automotive IC manufacturers achieve chip failure rates below the parts per billion level.

As a reminder, tool monitoring is the established best practice for isolating the source of random defectivity contributed by the fab’s process tools. During tool monitoring, a bare wafer is inspected to establish its baseline defectivity, run through a specific process tool (or chamber), and then inspected again. Any defects that were added to the wafer must have come from that specific process tool. This method can reveal the cleanest “golden” tools in the fab, as well as the “dog” tools that contribute the most defects and require corrective action. With plots of historical defect data from the process tools, goals and milestones for continuous improvement can be implemented.

When semiconductor fabs design their tool monitoring strategy, they must decide on the minimum size of defects that they want to detect and monitor. If historical test results have shown that smaller defects do not impact yield, then fabs will run their inspection tools at a lower sensitivity so that they no longer detect these smaller defects. By doing this, they can focus only on the larger yield-killer defects, avoiding distraction from the smaller “nuisance” defects. This approach works for a consumer fab that is only trying to optimize yield, but what about the automotive fab? Recall that yield and reliability issues are caused by the same defects types – yield and reliability defects differ only in their size and/or where they land on the device pattern.2 Therefore, a tool monitoring strategy that leaves the fab blind to smaller defects may be missing the very defects that will be responsible for future reliability issues.

Moreover, it’s important to understand that defects that seem small and inconsequential at one process layer may have a dramatic impact later in the process flow – their impact can be exacerbated by the subsequent process steps. The two SEM images in figure 1 were taken at exactly the same location on the same wafer, but at different steps of the manufacturing process. The image on the left shows a single, small defect that was found on the wafer after a deposition layer. This defect was previously thought to be a nuisance defect with no negative effect on the die pattern or chip performance. The image on the right shows that same deposition defect after metal 1 pattern formation. The presumed nuisance defect has altered the quality of the metal line printed several process steps later. This chip might pass electrical wafer sort, but this type of metal deformity could easily become a reliability issue in the field when activated by automotive environmental stressors.

Figure 1. The left image shows small particle created at a deposition layer. The right image shows the exact same location on the wafer after the metal 1 pattern formation. The metal line defect was caused by the small particle at the prior deposition layer. This type of deformity in the metal line could easily become a reliability issue in the field.

So how does an automotive IC fab determine the smallest defect size that will pose a reliability risk? To start, it is important to understand the impact of different defect sizes on reliability. Consider, for example, the different magnitudes of a line open defect shown in figure 2. A chip that has a pattern structure with a full line open will likely fail at electrical wafer sort and thus does not pose any reliability risk. A chip with a 50% line open – a line that is pinched or otherwise restricted to ~50% of its cross-sectional area – will likely pass electrical wafer sort but poses a significant reliability risk in the field. If this chip is used in a car, environmental conditions such as heat, humidity and vibrations, can cause degradation of this defect to a full line open, resulting in chip failure.

Figure 2. The image on the left shows a full line open, while the right image shows a ~50% line open. The chip on the left will fail at sort (assuming there is no redundancy). The chip on the right may pass electrical wafer sort but is a reliability risk in the field.

As a next step, it is important to understand how different size defects affect a chip’s pattern integrity. More specifically, what is the smallest defect that will result in a line open? What is the smallest defect that will result in a 50% line open?

Figure 3 shows the results of a Monte Carlo simulation that models the impact of different size defects introduced at a BEOL film deposition step. Minimum defect size is plotted on the vertical axis against varying metal layer pitch dimensions. This data corresponds to the metal 1 spacing for the 7nm, 10nm, 14nm and 28nm design nodes, respectively.

The green data points correspond to the smallest defects that will cause a full line open and the orange data points correspond to the smallest defects that will produce a 50% line open (i.e., a potential reliability failure). In each case the smallest defect that will cause a potential reliability failure is 50-75% of the smallest defect that will cause a full line open.

Figure 3. The green data points show the minimum defect size required to cause a full line open at the minimum metal pitch. The orange data points show the minimum defect size needed to cause a 50% line open. The x-axis is the metal 1 spacing for the 7nm (far left data point), 10nm, 14nm and 28nm (far right data point) design nodes.

These modeling results imply that to control for, and reduce, the number of reliability defects present in the process, fabs need to capture smaller defects. Therefore, they require higher sensitivity inspections than what is required for yield optimization. In general, detection of reliability defects requires an inspection sensitivity that is one node ahead of the current design node plan for yield alone. Simply put, a fab’s previous standards for reducing defectivity to optimize yield will not be sufficient to optimize reliability.

Increasing the sensitivities of the tool monitoring inspection recipes, or in some cases, using a more capable inspection system, will find smaller defects and possibly reveal previously hidden signatures of defectivity, as in Figure 4 below. While these signatures may have had a tolerable impact on yield in a consumer fab, they represent an unacceptable risk to reliability for automotive fabs pursuing continuous improvement and Zero Defect standards.

Figure 4: Hidden defect signatures that may impact reliability are often revealed with appropriate tool monitoring sensitivity. Zero Defect standards require corrective action on the process tool contributing these defects.

There are several important unpatterned wafer defect inspection factors for a fab to consider when creating a strategy to improve tool monitoring inspection sensitivity to find the small, reliability-related defects contributed by process tools. First, it is important to recognize that in a mature fab where yields are already high, there is rarely a single process layer or module that will be the “silver bullet” to reducing defectivity adequately to meet reliability improvement goals. Rather, it is sum of small gains across many layers that produce the desired gains in reliability. Because yield and the associated reliability improvements are cumulative across layers, reliability gains achieved through process tool monitoring using unpatterned wafer inspection are best demonstrated using a multi-layer regression model:

Yield = f(Ys)+f(SFS1)+f(SFS2)+ f(SFS3)+ ….. f(SFSN) + error

  • Ys = systematic yield loss (not particles related)
  • SFSx = cumulative Sursfcan unpatterned wafer inspection detected particles for many layers
  • Error = Yield loss mechanisms not detected by Surfscan

This implies that reliability improvements require a fab’s commitment to continuous improvement in defectivity levels across all processes and process modules.

Second, the fab should consider the quality of the bare wafer used for process tool monitoring. Recycling bare wafers increases the surface roughness with each cycle, an attribute known as haze. This haze level is fundamentally noise that affects the inspection system’s ability to differentiate the signal of smaller defects. Variability in haze across the population of test wafers acts as a limit to overall inspection recipe capability, requiring normalization, calibration and haze limits to reduce the impact of this noise source on defect sensitivity.

Next, the fab should ensure that the monitor step closely mimics the process that a production, patterned wafer follows. Small time-saving deviations in the monitor wafer flow to short cut the process may inadvertently skip the causal mechanism of defectivity. Furthermore, an over-reliance on mechanical handling checks alone bypasses the process completely and misses the critical contribution the process plays in particle generation.

When increasing the inspection recipe sensitivity, the fab must co-optimize both the “pre” and “post” inspection together. Often cycling the bare wafer through a process step can “decorate” small pre-existing defects on the wafer that were initially below the detection threshold. Once decorated, the defects now appear bigger and are more easily detected. In an unoptimized “post” inspection, these decorated defects can look like “adders,” leading to a false alarm and inadvertent process tool down time. Optimizing the inspections together maximizes the sensitivity and increases the confidence in the excursion alarms while avoiding time-consuming false alarms.

Lastly, it is important to review and classify the defects found during unpatterned inspection to correlate their relevance to the defects found at the equivalent patterned wafer process step. Only then can the fab be confident that the source of the defects has been isolated and appropriate corrective action has been taken.

To meet the high reliability demands of the automotive industry, IC manufacturers will need to go beyond simply monitoring and controlling the number of yield limiting defects on the wafer. They will need to improve the sensitivity of their tool monitoring inspections to one node smaller than what would historically be considered relevant. Only with this extra sensitivity can they detect and eliminate defects that would otherwise escape the fab and cause premature reliability failures. Additionally, when implementing a tool monitoring strategy, fabs need to carefully consider multiple factors, such as monitor wafer recycling, pre and post inspection sensitivity and the importance of a fab-wide continuous improvement program. With so much riding on automotive semiconductor reliability, increased sensitivity to smaller defects is an essential part of an optimal Zero Defect continuous improvement program.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

John McCormack is a Senior Director at KLA-Tencor. Barry Saville is Consulting Engineer at KLA-Tencor. John and Barry both have over 25 years of experience in yield improvement and defectivity reduction, working with many IC manufacturers around the world.

References:

  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.

Leti, an institute of CEA-Tech, has developed a novel retinal-projection concept for augmented reality (AR) uses based on a combination of integrated optics and holography. The lens-free optical system uses disruptive technologies to overcome the limitations of existing AR glasses, such as limited field-of-view and bulky optical systems.

TVs and smartphones that project digital images emit light all around them, as quasi-isotropic sources. Because the images are projected generally over the air without directivity, many viewers see the same image. In typical AR glasses, images are transmitted close to the eyes (high directivity) by a microdisplay that includes an optical system and an optical combiner.

These microdisplays create a small near-to-eye image, which is transformed by the optical system, enabling the user to see it despite the short focusing distance. The combiner superimposes the digital image to the viewers’ vision of the real environment.

CEA-Leti’s innovation is a transparent retinal-projection device that projects various light waves to the eyes from a glass surface. Images are formed in the retina by the interference of light waves, which eliminates the need for optical systems or combiners. The light propagating in the air doesn’t form an image until it interferes precisely in the retina.

CEA-Leti presented its results Feb. 6 at SPIE Photonics West 2019 in a paper titled “Integrated Optical Network Design for a Retinal Projection Concept Based on Single-Mode Si3N4 Waveguides at 532 nm”.

The project focused on the design and numerical simulations of integrated Si3N4 optical components and the optical circuit at λ = 532 nm. It required building blocks for designing an optical integrated circuit capable of creating an array of emissive points. Starting with single-mode waveguides to efficiently transport light around the circuit, many other components were designed to manipulate light in different locations. Components for extracting the light, such as diffraction gratings, were also designed and simulated. The team minimized losses of different parts of the circuit, such as waveguide-bending areas, to increase energy efficiency of the system.

CEA-Leti’s integration of the device and its use of a holographic layer also allow creation of compact AR glasses with a larger field-of-view than existing systems, while the transparent retinal projection device allows ambient light to pass through the device for enhanced AR applications.

“Combining integrated optics and holography is a new research area for the scientific community developing display applications,” said Basile Meynard, a Ph.D. student and lead author of the paper. “It is also a way to imagine a display device that works more as a data transfer system than as an imaging system.”

The novel approach will require further development before it reaches the commercialization stage. In the medium to long term, the retinal projection concept is expected to support more compact and higher virtual-image quality applications similar to existing AR glasses.

This research project builds on CEA-Leti’s many years of development of micro-displays for near-to-eye displays, such as organic LED technologies (OLED) and liquid crystal devices (LCD). More recently, the institute has made significant strides in the field of inorganic LED display manufacturing.

“Our teams are continuously looking for potential disruptive technologies that could pave the way to new families of display devices down the road,” said Christophe Martinez, optical senior scientist and project leader in Leti. “The investigation on retinal displays is part of this exploration of future optical solutions.”

SEMI-FlexTech, an industry-led, public/private partnership, today issued a Request for Proposals (RFP) for artificial intelligence (AI), Human-Machine Interface (HMI), sensor system and other projects to advance the flexible hybrid electronics (FHE) ecosystem. Approximately $5 million is allocated for these projects. Manufacturers and developers in the electronics supply chain are encouraged to respond to the SEMI-FlexTech 2019 RFP. Primary funding will be provided by the U.S. Army Research Laboratory (ARL) through SEMI-FlexTech.

Topics in this 2019 Solicitation are:

  1. Reference designs for FHE sensor systems
  2. FHE Power
  3. Artificial Intelligence (AI) for additive manufacturing
  4. Mixed mode interconnect and metallization for FHE
  5. Human-Machine Interfaces (HMI)
  6. Open concepts for sensor and FHE technologies and agile, expedient manufacturing

Details about each topic are included in the full RFP.

SEMI-FlexTech’s R&D program focuses on developing the infrastructure required to support world-class manufacturing capabilities for FHE devices and products. Because flexible and printed electronics development often requires expertise across multiple disciplines including printing, materials science and advanced semiconductor packaging, SEMI-FlexTech prefers multi-institutional teams. Participation of organizations new to the SEMI-FlexTech program is especially welcome.

The program is designed to support more risky technical approaches, as well as those proposing step improvements to current technology. The proposal process consists of two stages:

  1. White paper submission
  2. Submission of full proposal from respondents selected after white paper review

White papers will be accepted until March 1, 2019, at 5:00 p.m. PST. Full proposals will be due by April 15, 2019, and award notifications will be issued on or about June 1, 2019.

“SEMI-FlexTech is excited to again partner with ARL in advancing the flexible electronics industry,” said Dr. Melissa Grupen-Shemansky, SEMI CTO for flexible electronics and advanced packaging. “The topics provided are a rich set of technology initiatives that will appeal to many of our members.”

SEMI-FlexTech and ARL personnel will be available for consultation at FLEX 2019 in Monterey, California, February 18-21, 2019.  A webinar for those interested in learning more will be held on Friday, February 8, 2019, at 10:00 a.m. PST.

Researchers at the University of Exeter have developed an innovative technique that could help create the next generation of everyday flexible electronics.

A team of engineering experts have pioneered a new way to ease production of van der Waals heterostructures with high-K dielectrics- assemblies of atomically thin two-dimensional (2-D) crystalline materials.

One such 2-D material is graphene, which comprises of a honeycomb-shaped structure of carbon atoms just one atom thick.

While the advantages of van der Waals heterostructures is well documented, their development has been restricted by the complicated production methods.

Now, the research team has developed a new technique that allows these structures to achieve suitable voltage scaling, improved performance and the potential for new, added functionalities by embedding a high-K oxide dielectric.

The research could pave the way for a new generation of flexible fundamental electronic components.

The research is published in the journal Science Advances.

Dr Freddie Withers, co-author of the paper and from the University of Exeter said: “Our method to embed a laser writable high-K dielectric into various van der Waals heterostructure devices without damaging the neighbouring 2D monolayer materials opens doors for future practical flexible van der Waals devices such as, field effect transistors, memories, photodetectors and LED’s which operate in the 1-2 Volt range”

The quest to develop microelectronic devices to increasingly smaller size underpins the progress of the global semiconductor industry – a collection of companies that includes the tech and communication giants Samsung and Toshiba – has been stymied by quantum mechanical effects.

This means that as the thickness of conventional insulators is reduced, the ease at which electrons can escape through the films.

In order to continue scaling devices ever smaller, researchers are looking at replacing conventional insulators with high-dielectric-constant (high-k) oxides. However, commonly used high-k oxide deposition methods are not directly compatible with 2D materials.

The latest research outlines a new method to embed a multi-functional, nanoscaled high-K oxide, only a within van der Waals devices without degrading the properties of the neighbouring 2D materials.

This new technique allows for the creation of a host of fundamental nano-electronic and opto-electronic devices including dual gated graphene transistors, and vertical light emitting and detecting tunnelling transistors.

Dr Withers added: “The fact we start with a layered 2D semiconductor and convert it chemically to its oxide using laser irradiation allows for high quality interfaces which improve device performance.

“What’s especially interesting for me is we found this oxidation process of the parent HfS2 to take place under laser irradiation even when its sandwiched between 2 neighbouring 2D materials. This indicates that water needs to travel between the interfaces for the reaction to occur.”

Intentionally “squashing” colloidal quantum dots during chemical synthesis creates dots capable of stable, “blink-free” light emission that is fully comparable with the light produced by dots made with more complex processes. The squashed dots emit spectrally narrow light with a highly stable intensity and a non-fluctuating emission energy. New research at Los Alamos National Laboratory suggests that the strained colloidal quantum dots represent a viable alternative to presently employed nanoscale light sources, and they deserve exploration as single-particle, nanoscale light sources for optical “quantum” circuits, ultrasensitive sensors, and medical diagnostics.

“In addition to exhibiting greatly improved performance over traditional produced quantum dots, these new strained dots could offer unprecedented flexibility in manipulating their emission color, in combination with the unusually narrow, ‘subthermal’ linewidth,” said Victor Klimov, lead Los Alamos researcher on the project. “The squashed dots also show compatibility with virtually any substrate or embedding medium as well as various chemical and biological environments.”

The new colloidal processing techniques allow for preparation of virtually ideal quantum-dot emitters with nearly 100 percent emission quantum yields shown for a wide range of visible, infrared and ultraviolet wavelengths. These advances have been exploited in a variety of light-emission technologies, resulting in successful commercialization of quantum-dot displays and TV sets.

The next frontier is exploration of colloidal quantum dots as single-particle, nanoscale light sources. Such future “single-dot” technologies would require particles with highly stable, nonfluctuating spectral characteristics. Recently, there has been considerable progress in eliminating random variations in emission intensity by protecting a small emitting core with an especially thick outer layer. However, these thick-shell structures still exhibit strong fluctuations in emission spectra.

In a new publication in the journal Nature Materials, Los Alamos researchers demonstrated that spectral fluctuations in single-dot emission can be nearly completely suppressed by applying a new method of “strain engineering.” The key in this approach is to combine in a core/shell motif two semiconductors with directionally asymmetric lattice mismatch, which results in anisotropic compression of the emitting core.

This modifies the structures of electronic states of a quantum dot and thereby its light emitting properties. One implication of these changes is the realization of the regime of local charge neutrality of the emitting “exciton” state, which greatly reduces its coupling to lattice vibrations and fluctuating electrostatic environment, key to suppressing fluctuations in the emitted spectrum. An additional benefit of the modified electronic structures is dramatic narrowing of the emission linewidth, which becomes smaller than the room-temperature thermal energy.

Samsung Electronics Co., Ltd. today introduced its latest innovations in modular MicroLED display technology during its annual First Look CES event at the Aria Resort & Casino in Las Vegas. The revolutionary new MicroLED technology designs featured at the event included: a new 75” display, a 219” The Wall as well as other various groundbreaking sizes, shapes and configurations for a next-generation modular MicroLED display – a 2019 CES Best of Innovation Award winner.

“For decades, Samsung has led the way in next-generation display innovation,” said Jonghee Han, President of Visual Display Business at Samsung Electronics. “Our MicroLED technology is at the forefront of the next screen revolution with intelligent, customizable displays that excel in every performance category. Samsung MicroLED has no boundaries, only endless possibilities.”

Featuring self-emissive technology and modular capabilities, Samsung’s MicroLED displays deliver unparalleled picture quality, versatility and design. These transformative TV displays are made up of individual modules of self-emissive MicroLEDs, featuring millions of inorganic red, green and blue microscopic LED chips that emit their own light to produce brilliant colors on screen – delivering unmatched picture quality that surpasses any display technology currently available on the market.

At last year’s CES, Samsung introduced MicroLED by unveiling The Wall, the critically acclaimed, award-winning 146” MicroLED display. Due to the technical advancements in the ultra-fine pitch semiconductor packaging process that narrow the gap between the microscopic LED chips, Samsung has been able to create a stunning 4K MicroLED display in a smaller, more home-friendly 75” form factor.

Thanks to the modular nature of MicroLED, this technology offers flexibility in screen size that allows users to customize it to fit any room or space. By adding MicroLED modules, users can expand their display to any size they desire. The modular functionality of MicroLED will allow users in the future to create the ultimate display even at irregular 9×3, 1×7 or 5×1 screen sizes that suits their spatial, aesthetic and functional needs.

Samsung’s MicroLED technology also optimizes the content no matter the size and shape of the screen. Even when adding more modules, Samsung MicroLED displays can scale to increase the resolution — all while keeping the pixel density constant. Additionally, MicroLED can support everything from the standard 16:9 content, to 21:9 widescreen films, to unconventional aspect ratios like 32:9, or even 1:1 – without having to make any compromises in its picture quality.

Finally, because MicroLED displays are bezel-free, there are no borders between modules – even when you add more. The result is a seamless, stunning infinity pool effect that allows the display to elegantly blend into any living environment. The possibilities for eye-catching designs are enhanced by new Ambient Mode features.

For more detail on Samsung’s 2019 QLED 8K and MicroLED lines, please visit booth #15006 in the Central Hall of the Las Vegas Convention Center during CES 2019 (January 8-11, 2019).

Plessey, a developer of award-winning optoelectronic technology solutions, announces a collaboration with EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, to bring high-performance GaN-on-Silicon (GaN-on-Si) monolithic microLED technology to the mass market. microLEDs are the key optical technology for next-generation AR applications.

Plessey has purchased a GEMINI® production wafer bonding system from EVG to enable bonding and alignment at Plessey’s fabrication facility in Plymouth, UK. This enables Plessey to bond its GaN-on-Si microLED arrays to the panel’s backplane at a wafer level, and with the high level of alignment precision necessary to enable very small pixel dimensions.

EVG’s patented SmartView®NT Automated Bond Alignment System technology is suitable for Plessey’s requirements because it allows face-to-face alignment of the wafers with very high precision. A maximum level of automation and process integration is achieved by the GEMINI Automated Production Wafer Bonding System. Wafer-to-wafer alignment and wafer bonding processes up to 300mm for volume manufacturing are all performed in one fully automated platform.

John Whiteman, VP of Engineering at Plessey, explained: ‘The modular design of the GEMINI system is ideal for our requirements. Having the pre-treatment, clean, alignment and bonding enabled within one system means higher yield and throughput in production. The excellent service provided by EVG has been critical to bringing the system online quickly and efficiently.’

Paul Lindner, executive technology director at EV Group, commented: ‘We are honoured that Plessey selected our state-of-the-art GEMINI system to support their ambitious technology development roadmaps and high-volume production plans.’

This announcement marks another key milestone for Plessey in investment in production-grade equipment to bring GaN-on-Si based monolithic microLED products to market.

Veeco Instruments Inc. (Nasdaq: VECO) and ALLOS Semiconductors GmbH announced today the completion of another phase of their mutual effort to provide the industry with leading GaN-on-Silicon epiwafer technology for microLED production. The purpose of the companies’ most recent collaboration was to demonstrate the reproducibility of ALLOS’ 200 mm GaN-on-Si epiwafer technology on Veeco’s Propel® MOCVD reactor when producing epiwafers for many prominent global consumer electronics companies.

“To bring microLED technology into production, simply presenting champion values for a single metric is insufficient. It is essential to achieve the whole set of specifications for each wafer with excellent repeatability and yield,” said Peo Hansson, Ph.D., senior vice president and general manager of Veeco’s Compound Semiconductor business unit. “This successful joint effort reaffirms the power of combining Veeco’s superior MOCVD expertise with ALLOS’ GaN-on-Silicon epiwafer technology to provide customers a novel, proven and reliable approach to accelerate microLED adoption.”

Sorting and binning are standard methods to achieve wavelength consistency for conventional LEDs. But microLEDs are too small and numerous to be sorted and binned; therefore, the uniformity of the epitaxial deposition is even more critical. The most important success factor for turning the promise of microLED displays into mass production reality is to achieve extremely good emission wavelength uniformity, which eliminates the need to test and sort individual microLED chips. Depending on the application and mass transfer approach, the target requirements of the industry are between +/-1 nm and +/-4 nm bin (min/max) on the epiwafer. Through this collaborative project, Veeco and ALLOS further improved the critical wavelength uniformity with the best wafer having a standard deviation of just 0.85 nm, representing an industry first on a production system.

“Veeco and ALLOS validated wafer-to-wafer reproducibility with an average wavelength standard deviation for all wafers of 1.21 nm and the peak wavelength within a +/- 0.5 nm range. With these results we made another significant leap towards the +/-1 nm bin goal on an epiwafer,” said Burkhard Slischka, CEO of ALLOS. “Our technology is already available on 200 mm wafer diameter, which enables the use of low-cost and high yield silicon lines for microLED chip production. Additionally, we have a clear roadmap to enable 300 mm.”

Innovators in display technology are focusing on microLED as the next significant technological shift. According to research firm Yole Développement, the market for microLED displays could potentially reach 330 million units by 2025. This optimism is fueled by the promise of microLED technology (sub-100 micrometer edge length), which is considered the critical enabler to achieving the ultimate display with much lower power consumption. However, development of such displays has been hindered by high material costs and low yield and throughput of microLED mass transfer technology. This joint technical effort effectively addresses these challenges as Veeco and ALLOS continue to work with customers to further improve GaN-on-Si epiwafer and microLED mass transfer technology.

Veeco and ALLOS will showcase details of their breakthrough achievements at the International Workshop on Nitride Semiconductors (IWN) in Kanazawa, Japan on Nov. 12, 2018.

Plessey, a developer of award-winning optoelectronic technology solutions, announces it has placed an order for its next reactor from AIXTRON SE (FSE: AIXA), a global provider of deposition equipment to the semiconductor industry. The AIX G5+ C metal organic chemical vapour deposition (MOCVD) reactor will boost Plessey’s manufacturing capability of gallium nitride on silicon (GaN-on-Si) wafers targeting next-generation microLED applications.

With an automatic cassette-to-cassette (C2C) wafer transfer module, the new AIXTRON reactor will be installed and operational during Q1 of 2019 at Plessey’s 270,000 sq ft fabrication facility located in Plymouth, UK. The AIX G5+ C MOCVD system has two separate chamber set-up options, which enables configurations of 8 x 6in or 5 x 8in GaN-on-Si wafers to be automatically loaded and removed from the system in an enclosed cassette environment. The system will be an addition to the company’s existing metal organic chemical vapour deposition (MOCVD) reactors, also supplied by AIXTRON, which provide configurations of 7 x 6in or 3 x 8in with manual loading.

Productivity is further enhanced by the new reactor’s automated self-cleaning technology, which helps to deliver a very low level of wafer defects by ensuring the reactor is clean on every run, significantly reducing downtime for maintenance. The new equipment also provides faster ramp and cool down along with a high susceptor unload temperature to reduce the recipe time.

The AIX G5+ C reactor will support Plessey’s extensive production roadmap to increase R&D capacity of its monolithic microLEDs based on its proprietary GaN-on-Si technology. Plessey’s microLEDs offer extremely low power, high brightness and very high pixel density to create the potential for disruption in many existing application areas that use conventional display technologies such as LCD and OLED.

Plessey’s mission is to become the world’s leading company developing innovative illuminators for display engines and full-field emissive microLED displays. The complex devices combine very high-density RGB pixel arrays with high-performance CMOS backplanes to produce very high-brightness, low-power, and high-frame-rate image sources for head-mounted displays, and wearable electronics devices for augmented reality and virtual reality systems.

Quantum dots are nanometer-sized boxes that have attracted huge scientific interest for use in nanotechnology because their properties obey quantum mechanics and are requisites to develop advanced electronic and photonic devices. Quantum dots that self-assemble during their formation are particularly attractive as tunable light emitters in nanoelectronic devices and to study quantum physics because of their quantized transport behavior. It is important to develop a way to measure the charge in a single self-assembled quantum dot to achieve quantum information processing; however, this is difficult because the metal electrodes needed for the measurement can screen out the very small charge of the quantum dot. Researchers at Osaka University have recently developed the first device based on two self-assembled quantum dots that can measure the single-electron charge of one quantum dot using a second as a sensor.

The device was fabricated using two indium arsenide (InAs) quantum dots connected to electrodes that were deliberately narrowed to minimize the undesirable screening effect.

This is a scanning electron micrograph of InAs self-assembled quantum dot transistor device. Credit: Osaka University

“The two quantum dots in the device showed significant capacitive coupling,” says Haruki Kiyama. “As a result, the single-electron charging of one dot was detected as a change in the current of the other dot.”

The current response of the sensor quantum dot depended on the number of electrons in the target dot. Hence the device can be used for real-time detection of single-electron tunneling in a quantum dot. The tunneling events of single electrons in and out of the target quantum dot were detected as switching between high and low current states in the sensor quantum dot. Detection of such tunneling events is important for the measurement of single spins towards electron spin qubits.

“Sensing single charges in self-assembled quantum dots is exciting for a number of reasons,” explains Akira Oiwa. “The ability to achieve electrical readout of single electron states can be combined with photonics and used in quantum communications. In addition, our device concept can be extended to different materials and systems to study the physics of self-assembled quantum dots.”

An electronic device using self-assembled quantum dots to detect single-electron events is a novel strategy for increasing our understanding of the physics of quantum dots and to aid the development of advanced nanoelectronics and quantum computing.