Tag Archives: letter-materials-top

The worldwide race to create more, better and reliable quantum processors is progressing fast, as a team of TU Delft scientists led by Professor Vandersypen has realised yet again. In a neck-and-neck race with their competitors, they showed that quantum information of an electron spin can be transported to a photon, in a silicon quantum chip. This is important in order to connect quantum bits across the chip and allowing to scale up to large numbers of qubits. Their work was published today in the journal Science.

The quantum computer of the future will be able to carry out computations far beyond the capacity of today's computers. Credit: TU Delft

The quantum computer of the future will be able to carry out computations far beyond the capacity of today’s computers. Credit: TU Delft

The quantum computer of the future will be able to carry out computations far beyond the capacity of today’s computers. Quantum superpositions and entanglement of quantum bits (qubits) make it possible to perform parallel computations. Scientists and companies worldwide are engaged in creating increasingly better quantum chips with more and more quantum bits. QuTech in Delft is working hard on several types of quantum chips.

Familiar material

The core of the quantum chips is made of silicon. “This is a material that we are very familiar with,” explains Professor Lieven Vandersypen of QuTech and the Kavli Institute of Nanoscience Delft, “Silicon is widely used in transistors and so can be found in all electronic devices.” But silicon is also a very promising material for quantum technology. PhD candidate Guoji Zheng: “We can use electrical fields to capture single electrons in silicon for use as quantum bits (qubits). This is an attractive material as it ensures the information in the qubit can be stored for a long time.”

Large systems

Making useful computations requires large numbers of qubits and it is this upscaling to large numbers that is providing a challenge worldwide. “To use a lot of qubits at the same time, they need to be connected to each other; there needs to be good communication”, explains researcher Nodar Samkharadze. At present the electrons that are captured as qubits in silicon can only make direct contact with their immediate neighbours. Nodar: “That makes it tricky to scale up to large numbers of qubits.”

Neck-and-neck race

Other quantum systems use photons for long-distance interactions. For years, this was also a major goal for silicon. Only in recent years have various scientists made progress on this. The Delft scientists have now shown that a single electron spin and a single photon can be coupled on a silicon chip. This coupling makes it possible in principle to transfer quantum information between a spin and a photon. Guoji Zheng: “This is important to connect distant quantum bits on a silicon chip, thereby paving the way to upscaling quantum bits on silicon chips.”

On to the next step

Vandersypen is proud of his team: “My team achieved this result in a relatively short time and under great pressure from worldwide competition.” It is a true Delft breakthrough: “The substrate is made in Delft, the chip created in the Delft cleanrooms, and all measurements carried out at QuTech,” adds Nodar Samkharadze. The scientists are now working hard on the next steps. Vandersypen: “The goal now is to transfer the information via a photon from on electron spin to another.”

A new technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

BY ROBERT PAGLIARO, RP Innovative Engineering Solutions, LLC, Mesa, AZ

As semiconductor based electronic devices have become smaller, faster, smarter, 3-dimensional, and multi-functional the methods and materials required to fabricate them demand novel approaches to be developed and implemented in the device manufacturing facilities. Amongst the most challenging requirements are the need to lower the thermal budgets of the front end thermal processes and to minimize the semiconductor material consumption that comes with the conventional oxidizing (hydrogen peroxide and ozone based chemistries) wet cleaning processes chemistries such as APM, HPM, SPM and SOM.

A novel wet surface preparation method that removes existing surface contamination and native oxide from semiconductor surfaces and then passivates them with a pristine and stable hydrogen passivated surface has been developed and commercialized by APET Co, Ltd. in a system called the TeraDox. This patented technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

The TeraDox system is an enhanced version of the APET FRD (HF etching, Rinse and Dry). The name TeraDox implies the ability to provide a process chemistry with < 1 ppb impurities, particularly dissolved oxygen, which allows for producing pristine and stable H-passivated semiconductor surfaces. Dilute HF and HCl (dHF and dHCl) are the etching chemistries used for removing the native and chemical oxides from Si, SiGe and Ge surfaces. The TeraDox system has a single vessel wet processor and a wafer transfer/drying hood that allows for a segue between the load, chemical fill, etch, insitu-rinse, dry and unload steps of the process sequence, while keeping the process chemistry and the wafers in a continuous ambient of ultra- pure N2. This equipment and process design eliminate the exposure of the wafers to air and minimizes gas perme- ation throughout the entire oxide removal and H-passiv- ation process sequence. These are all critical elements to achieving the best surface quality results. While there are a variety of important parameters towards achieving a pristine and stable H-passivated surface one of the most enabling ingredients to the APET TeraDox process and equipment IP is the PPT level degassing capability for the UPW and aqueous chemicals used in the H-passivation process. The unique UPW and chemical degassing apparatus require an optimized hardware configuration with membrane contactors and facilities used for the vacuum + UHP N2 sweep gas to achieve a DO degassing efficiency > 99.999%. This ultra-high degassing efficiency allows for a Dissolved Oxygen (DO) concen- tration capability of < 100 ppt.

It has been well proven and documented by multiple world-renowned surface scientists [1,2,3] since the late 1980s that the level of dissolved oxygen (DO), as well as other dissolved impurities (such as CO2, TOC, silica and N2), has a direct impact on the efficiency of H-passivation and the native oxide (initial and changing thickness vs. queue time) that follows the removal of native and chemical oxides from semicon- ductor surfaces. Queue time (Q-time) is the amount of time that the H-passivated wafer are exposed to air before being placed in an inert environment for the subsequent process step (epi, poly silicon, metal, ion implantation etc.). It can be seen in FIGURE 1 how native oxide regrowth occurs after HF treatment in air and UPW vs. exposure time [1].

Screen Shot 2017-12-06 at 12.26.01 PM

A similar DO vs. surface oxide and carbon relationship is also verified using encapsulated SIMS. This method uses dynamic SIMS to measure the amount of O, C that are trapped at the epi layer/silicon wafer interface. This has been a widely used characterization method to assess a pre-low temperature epi surface prepa- ration process’ hydrogen surface passivation quality since the early 90s. The typical epi cap is ~80-150nm and is deposited using a 650°C SiH4 source deposition process. The objective is to be able to minimize the thermal budget of the pre-deposition bake step which is required to remove any surface oxides and organics to allow perfect epitaxial deposition with no contami- nants or defects at the interface.

FIGURE 2 demonstrates how the encapsulated SIMS interface O (areal oxide density, AOD) using a 650°C SiH4 no bake Si deposition process is strongly dependent on the DO concentration. Three samples are depicted with different surface preparation conditions, a reference wafer with no surface preparation, a wafer dHF wet processedwith the UPW DO ~ 1ppb, and a wafer dHF wet processed with the DO ~0.1 ppb.

Screen Shot 2017-12-06 at 12.26.31 PM

It can be seen in FIGURE 3 how applying a 700C/80T/60s bake before a 650C Si deposition process with the UPW DO at 0.1ppb yields non-detectable O and C. This SIMS data info is relatively old (2010) but is still good for reference. The current APET TeraDox wet process capability can provide non-detectable O and C without a bake before the 650°C Si deposition process.

Screen Shot 2017-12-06 at 12.26.46 PM

As mentioned earlier, undesirable native oxide thickness increases with queue time on H-passivated Si, SiGe and Ge surfaces. So, it is important to minimize the Q-time between the H-passivation process and the subsequent process step, but the quality and stability of the H-passivation does need to accommodate practical queue times in a manufacturing environment. The H-passivation from the APET TeraDox process has proven to be stable enough for up to at least 8-hour Q-times for most low temperature process applications, which makes it suitable for most semiconductor device manufacturing facilities.

Aside from the low surface oxygen benefit from having ultra-low DO in this process there are other very important benefits to this as well. Having ultra-low DO prevents water marks, microroughness (faceting), bacterial contamination and material consumption. If there is no DO in the UPW or the etching chemistry then there is no competing mechanism to simultaneously oxidize and etch the semiconductor material during the oxide etch and insitu-rinse steps. If the surface is being oxidized/etched then orientation selective faceting will occur. Faceting leads to gener- ation a mix of mono-, di- and tri- hydride terminations on the different orientations of the semiconductor surface. An example is silicon (100), which if it is kept atomically smooth after the oxide is removed by HF, the surface will be dominated by di-hydride terminations. If the surface is faceted it will contain lower energy mono-hydride terminations. Higher energy hydride bonds lead to better surface stability while the lower energy hydride bonds make the surface less stable and will re-oxidize faster with Q-time.

So in general, the pristineness and the atomic smoothness of the semiconductor surface are what dictates the quality and stability of the H-passivating surface preparation process.

While the TeraDox process performance has continued to improve with the new innovations, the capabilities have surpassed the detection limits of conven- tional measurement methods like encapsulated SIMS characterization. Encapsulated SIMS also has a lot of drawbacks and limitations which make it an impractical process monitoring method in manufacturing facil- ities. The need to have a more sensitive measurement method that can measure “as processed” surfaces in a fast, real time and non-destructive manner had become an urgent requirement.

There are a variety of very good electrical and optical measurement methods that have been in use for many years, but most of them do not provide surface specific information directly. Surface parameters such as surface recombination velocity and lifetime (SRV and Ts) can be calculated relatively accurately using multiple step procedures by measurement methods such as uPCD, QSS-PC, PL and SPV. SRV (surface recombination velocity) and Ts (surface recombination lifetime) are extremely sensitive to surface contamination such as C, O metals and dopants as well as micro- roughness. This diverse sensitivity make it ideal for assessing surface preparation methods.

Until recently, only one measurement technique has been found that can measure the SRV and Teff (effective lifetime) of the surface directly and quickly on as processed H-passivated wafers. While doing a lot of research for the ideal measurement method to pair with the APET TeraDox H-passivation process, it was discovered that an enhanced version of the CADIPT department at the University of Toronto’s PCR-LIC technology, called Quantitative Lock-in Carrierog- raphy and Imaging (Q-LIC), could have the unique and enabling capabilities needed for this application. After completing an array of screening and optimization testing over the course of 8 months, the results have validated Q-LIC as an ideal measurement method for “as processed” H-passivated surfaces. In FIGURE 4, the plot demonstrates the SRV vs Q-time for four different wet cleans and an unprocessed control. The data shows strong evidence of the differentiation between different H-passivation methods (process and equipment), the level of DO in the wet process chemistry, and the dynamically changing surface state over time.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

APET currently has five patents, related to this technology, integrated on the commercially available TeraDox wet process equipment, four of which include the use of vacuum/N2 sweep degassing with membrane contactors for both the UPW and chemical degassing.

The UPW degassing is done in a separate stand-alone module (called the APET Dox unit) that treats up to 60 lpm of UPW before going to the main unit. All Dox units are guaranteed to have DO < 1 ppb, but all of the units in use to date achieve < 200 ppt. The most recently installed Dox unit system has a base DO level of ~30-40 ppt. Aside from the importance of PPT level degassing of the UPW much attention has also been given towards the design and materials used in the entire TeraDox system to prevent gas permeation into the UPW supply and the process chemistry to achieve optimum H-passivation. The most recent TeraDox related patent that was issued to APET was for chemical degassing. The degassing of the HF and HCl are typically overlooked in this application. Typically, HF comes in ~48% and HCl in ~37% concentrations with the balance of these supplied mixtures is in DO saturated water. So even diluted etching chemistries of up to 400 (UPW) :1 (chemical) ratios will typically still produce a composite DO of > 3ppb in the process vessel, even if the UPW supply is degassed to 0 ppt. Having the unique chemical degassing capability to < 1ppb DO significant improves the overall performance of the H-passivation process. The chemical degassing apparatus is integrated into the HF and HCl chemical delivery lines inside the TeraDox system’s main unit.

In summary, APET has developed and commercialized a unique and enabling wet surface preparation technology, the TeraDox process and equipment, that can produce pristine and stable hydrogen passivated semiconductor surfaces. While there are several critical factors and innovations that enable the TeraDox’s unique process performance capabilities, the fully integrated “dry in/dry out” system design and the unique PPT level degassing of the process chemistries are the most facili- tating features on the TeraDox system.


A special thanks to Dr. Andreas Mandelis and his staff at the University of Toronto for their support in optimizing their Q-LIC system to provide data for this paper as well as demonstrating a suitable measurement method for the “as processed” H-passivation application.


1. M. Morita et al, J. Appl. Phys. 88 (3), 1 (1990)
2. A. Philipossian, J. Electrochem. Soc. 139 No. 10, 2956 (1992)
3. F. H. Li, M. K. Balazs, and S. Anderson, J. Electrochem. Soc. 152,
G669 (2005)

Graphene ribbons that are only a few atoms wide, so-called graphene nanoribbons, have special electrical properties that make them promising candidates for the nanoelectronics of the future: While graphene – a one atom thin, honeycomb-shaped carbon layer – is a conductive material, it can become a semiconductor in the form of nanoribbons. This means that it has a sufficiently large energy or band gap in which no electron states can exist: it can be turned on and off – and thus may become a key component of nanotransistors.

The microscopic ribbons lie criss-crossed on the gold substrate. Credit: EMPA

The microscopic ribbons lie criss-crossed on the gold substrate. Credit: EMPA

The smallest details in the atomic structure of these graphene bands, however, have massive effects on the size of the energy gap and thus on how well-suited nanoribbons are as components of transistors. On the one hand, the gap depends on the width of the graphene ribbons, while on the other hand it depends on the structure of the edges. Since graphene consists of equilateral carbon hexagons, the border may have a zigzag or a so-called armchair shape, depending on the orientation of the ribbons. While bands with a zigzag edge behave like metals, i.e. they are conductive, they become semiconductors with the armchair edge.

This poses a major challenge for the production of nanoribbons: If the ribbons are cut from a layer of graphene or made by cutting carbon nanotubes, the edges may be irregular and thus the graphene ribbons may not exhibit the desired electrical properties.

Creating a semiconductor with nine atoms

Empa researchers in collaboration with the Max Planck Institute for Polymer Research in Mainz and the University of California at Berkeley have now succeeded in growing ribbons exactly nine atoms wide with a regular armchair edge from precursor molecules. The specially prepared molecules are evaporated in an ultra-high vacuum for this purpose. After several process steps, they are combined like puzzle pieces on a gold base to form the desired nanoribbons of about one nanometer in width and up to 50 nanometers in length.

These structures, which can only be seen with a scanning tunneling microscope, now have a relatively large and, above all, precisely defined energy gap. This enabled the researchers to go one step further and integrate the graphene ribbons into nanotransistors. Initially, however, the first attempts were not very successful: Measurements showed that the difference in the current flow between the “ON” state (i.e. with applied voltage) and the “OFF” state (without applied voltage) was far too small. The problem was the dielectric layer of silicon oxide, which connects the semiconducting layers to the electrical switch contact. In order to have the desired properties, it needed to be 50 nanometers thick, which in turn influenced the behavior of the electrons.

However, the researchers subsequently succeeded in massively reducing this layer by using hafnium oxide(HfO2) instead of silicon oxide as the dielectric material. The layer is therefore now only 1.5 nanometers thin and the “on”-current is orders of magnitudes higher.

Another problem was the incorporation of graphene ribbons into the transistor. In the future, the ribbons should no longer be located criss-cross on the transistor substrate, but rather aligned exactly along the transistor channel. This would significantly reduce the currently high level of non-functioning nanotransistors.

U.S. semiconductor chemical suppliers lost market share to Japanese and European competitors in every major segment over the past decade, according to the report entitled Chemicals and Materials for Sub-100 nm IC Manufacturing,” recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

“Despite a shift in semiconductor manufacturing from the U.S. to Japan, to Korea, and then to China, the chemical supply chain is still dominated by U.S., Japanese, and European chemical companies,” noted Dr. Robert Castellano, president of The Information Network.

Within this supply chain, U.S. chemical manufacturers lost market share in every major chemical sector over the past decade, according to The Information Network’s report. Specific details for the top three suppliers in each of the sectors are listed in the table below:



The first sector is one of the more interesting, because GlobalWafers, a Taiwanese company, acquired SunEdison in late 2016 making it the first company to break into the top three that wasn’t from headquartered in the U.S., Japan, or Europe,” added Dr. Castellano.

According to the report, the company held a 13.5% share in 2004 (when it was called MEMC) but it dropped to 10.1% in 2016 (when it was called SunEdison).

In each of the other sectors, the U.S. company dropped in market share. In the liquid chemicals sector, KMG Chemicals dropped from first place to third place, but gained market share because of its acquisition of OM Chemicals in 2014.

The trick is to be able to use beryllium atoms in gallium nitride. Gallium nitride is a compound widely used in semiconductors in consumer electronics from LED lights to game consoles. To be useful in devices that need to process considerably more energy than in your everyday home entertainment, though, gallium nitride needs to be manipulated in new ways on the atomic level.

“There is growing demand for semiconducting gallium nitride in the power electronics industry. To make electronic devices that can process the amounts of power required in, say, electric cars, we need structures based on large-area semi-insulating semiconductors with properties that allow minimising power loss and can dissipate heat efficiently. To achieve this, adding beryllium into gallium nitride – or ‘doping’ it – shows great promise,” explains Professor Filip Tuomisto from Aalto University.

Sample chamber of the positron accelerator. Credit: Hanna Koikkalainen

Sample chamber of the positron accelerator. Credit: Hanna Koikkalainen

Experiments with beryllium doping were conducted in the late 1990s in the hope that beryllium would prove more efficient as a doping agent than the prevailing magnesium used in LED lights. The work proved unsuccessful, however, and research on beryllium was largely discarded.

Working with scientists in Texas and Warsaw, researchers at Aalto University have now managed to show – thanks to advances in computer modelling and experimental techniques – that beryllium can actually perform useful functions in gallium nitride. The article published in Physical Review Letters shows that depending on whether the material is heated or cooled, beryllium atoms will switch positions, changing their nature of either donating or accepting electrons. “Our results provide valuable knowledge for experimental scientists about the fundamentals of how beryllium changes its behaviour during the manufacturing process. During it – while being subjected to high temperatures – the doped compound functions very differently than the end result,” describes Tuomisto.

If the beryllium-doped gallium nitride structures and their electronic properties can be fully controlled, power electronics could move to a whole new realm of energy efficiency.

“The magnitude of the change in energy efficiency could as be similar as when we moved to LED lights from traditional incandescent light bulbs. It could be possible to cut down the global power consumption by up to ten per cent by cutting the energy losses in power distribution systems,” says Tuomisto.

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) reported significant advances in the thermoelectric performance of organic semiconductors based on carbon nanotube thin films that could be integrated into fabrics to convert waste heat into electricity or serve as a small power source.

The research demonstrates significant potential for semiconducting single-walled carbon nanotubes (SWCNTs) as the primary material for efficient thermoelectric generators, rather than being used as a component in a “composite” thermoelectric material containing, for example, carbon nanotubes and a polymer. The discovery is outlined in the new Energy & Environmental Science paper, Large n- and p-type thermoelectric power factors from doped semiconducting single-walled carbon nanotube thin films.

“There are some inherent advantages to doing things this way,” said Jeffrey Blackburn, a senior scientist in NREL’s Chemical and Materials Science and Technology center and co-lead author of the paper with Andrew Ferguson. These advantages include the promise of solution-processed semiconductors that are lightweight and flexible and inexpensive to manufacture. Other NREL authors are Bradley MacLeod, Rachelle Ihly, Zbyslaw Owczarczyk, and Katherine Hurst. The NREL authors also teamed with collaborators from the University of Denver and partners at International Thermodyne, Inc., based in Charlotte, N.C.

Ferguson, also a senior scientist in the Chemical and Materials Science and Technology center, said the introduction of SWCNT into fabrics could serve an important function for “wearable” personal electronics. By capturing body heat and converting it into electricity, the semiconductor could power portable electronics or sensors embedded in clothing.

Blackburn and Ferguson published two papers last year on SWCNTs, and the new research builds on their earlier work. The first paper, in Nature Energy, showed the potential that SWCNTs have for thermoelectric applications, but the films prepared in this study retained a large amount of insulating polymer. The second paper, in ACS Energy Letters, demonstrated that removing this “sorting” polymer from an exemplary SWNCT thin film improved thermoelectric properties.

The newest paper revealed that removing polymers from all SWCNT starting materials served to boost the thermoelectric performance and lead to improvements in how charge carriers move through the semiconductor. The paper also demonstrated that the same SWCNT thin film achieved identical performance when doped with either positive or negative charge carriers. These two types of material–called the p-type and the n-type legs, respectively–are needed to generate sufficient power in a thermoelectric device. Semiconducting polymers, another heavily studied organic thermoelectric material, typically produce n-type materials that perform much worse than their p-type counterparts. The fact that SWCNT thin films can make p-type and n-type legs out of the same material with identical performance means that the electrical current in each leg is inherently balanced, which should simplify the fabrication of a device. The highest performing materials had performance metrics that exceed current state-of-the-art solution-processed semiconducting polymer organic thermoelectrics materials.

“We could actually fabricate the device from a single material,” Ferguson said. “In traditional thermoelectric materials you have to take one piece that’s p-type and one piece that’s n-type and then assemble those into a device.”

Scientists at the University of Sussex may have found a solution to the long-standing problem of brittle smart phone screens.

Professor Alan Dalton and his team have developed a new way to make smart phone touch screens that are cheaper, less brittle, and more environmentally friendly. On top of that, the new approach also promises devices that use less energy, are more responsive, and do not tarnish in the air.

Dr. Matthew Large, University of Sussex, flexes a screen made from acrylic plastic coated in silver nanowires and grapheme to illustrate the kind of touch screens that can potentially be produced using the new approach Credit: Dr. Matthew Large

Dr. Matthew Large, University of Sussex, flexes a screen made from acrylic plastic coated in silver nanowires and grapheme to illustrate the kind of touch screens that can potentially be produced using the new approach Credit: Dr. Matthew Large

The problem has been that indium tin oxide, which is currently used to make smart phone screens, is brittle and expensive. The primary constituent, indium, is also a rare metal and is ecologically damaging to extract. Silver, which has been shown to be the best alternative to indium tin oxide, is also expensive. The breakthrough from physicists at the University of Sussex has been to combine silver nanowires with graphene – a two dimensional carbon material. The new hybrid material matches the performance of the existing technologies at a fraction of the cost.

In particular, the way in which these materials are assembled is new. Graphene is a single layer of atoms, and can float on water. By creating a stamp – a bit like a potato stamp a child might make – the scientists can pick up the layer of atoms and lay it on top of the silver nanowire film in a pattern. The stamp itself is made from poly(dimethyl siloxane); the same kind of silicone rubber used in kitchen utensils and medical implants.

Professor Alan Dalton from the school of Maths and Physical Science at the University of Sussex, says:

“While silver nanowires have been used in touch screens before, no one has tried to combine them with graphene. What’s exciting about what we’re doing is the way we put the graphene layer down. We float the graphene particles on the surface of water, then pick them up with a rubber stamp, a bit like a potato stamp, and lay it on top of the silver nanowire film in whatever pattern we like. “And this breakthrough technique is inherently scalable. It would be relatively simple to combine silver nanowires and graphene in this way on a large scale using spraying machines and patterned rollers. This means that brittle mobile phone screens might soon be a thing of the past.

“The addition of graphene to the silver nanowire network also increases its ability to conduct electricity by around a factor of ten thousand. This means we can use a fraction of the amount of silver to get the same, or better, performance. As a result screens will be more responsive and use less power.”

Dr Matthew Large, lead researcher on the project within the school of Maths and Physical Science at the University of Sussex, says:

“Although silver is also a rare metal, like indium, the amount we need to coat a given area is very small when combined with graphene. Since graphene is produced from natural graphite – which is relatively abundant – the cost for making a touch sensor drops dramatically.

“One of the issues with using silver is that it tarnishes in air. What we’ve found is that the graphene layer prevents this from happening by stopping contaminants in the air from attacking the silver. “What we’ve also seen is that when we bend the hybrid films repeatedly the electrical properties don’t change, whereas you see a drift in the films without graphene that people have developed previously. This paves the way towards one day developing completely flexible devices.”

Fibers made of carbon nanotubes configured as wireless antennas can be as good as copper antennas but 20 times lighter, according to Rice University researchers. The antennas may offer practical advantages for aerospace applications and wearable electronics where weight and flexibility are factors.

The research appears in Applied Physics Letters.

The discovery offers more potential applications for the strong, lightweight nanotube fibers developed by the Rice lab of chemist and chemical engineer Matteo Pasquali. The lab introduced the first practical method for making high-conductivity carbon nanotube fibers in 2013 and has since tested them for use as brain implants and in heart surgeries, among other applications.

The research could help engineers who seek to streamline materials for airplanes and spacecraft where weight equals cost. Increased interest in wearables like wrist-worn health monitors and clothing with embedded electronics could benefit from strong, flexible and conductive fiber antennas that send and receive signals, Pasquali said.

The Rice team and colleagues at the National Institute of Standards and Technology (NIST) developed a metric they called “specific radiation efficiency” to judge how well nanotube fibers radiated signals at the common wireless communication frequencies of 1 and 2.4 gigahertz and compared their results with standard copper antennas. They made thread comprising from eight to 128 fibers that are about as thin as a human hair and cut to the same length to test on a custom rig that made straightforward comparisons with copper practical.

“Antennas typically have a specific shape, and you have to design them very carefully,” said Rice graduate student Amram Bengio, the paper’s lead author. “Once they’re in that shape, you want them to stay that way. So one of the first experimental challenges was getting our flexible material to stay put.”

Contrary to earlier results by other labs (which used different carbon nanotube fiber sources), the Rice researchers found the fiber antennas matched copper for radiation efficiency at the same frequencies and diameters. Their results support theories that predicted the performance of nanotube antennas would scale with the density and conductivity of the fiber.

“Not only did we find that we got the same performance as copper for the same diameter and cross-sectional area, but once we took the weight into account, we found we’re basically doing this for 1/20th the weight of copper wire,” Bengio said.

“Applications for this material are a big selling point, but from a scientific perspective, at these frequencies carbon nanotube macro-materials behave like a typical conductor,” he said. Even fibers considered “moderately conductive” showed superior performance, he said. Although manufacturers could simply use thinner copper wires instead of the 30-gauge wires they currently use, those wires would be very fragile and difficult to handle, Pasquali said.

“Amram showed that if you do three things right — make the right fibers, fabricate the antenna correctly and design the antenna according to telecommunication protocols — then you get antennas that work fine,” he said. “As you go to very thin antennas at high frequencies, you get less of a disadvantage compared with copper because copper becomes difficult to handle at thin gauges, whereas nanotubes, with their textile-like behavior, hold up pretty well.”

The huge increase in computing performance in recent decades has been achieved by squeezing ever more transistors into a tighter space on microchips.

However, this downsizing has also meant packing the wiring within microprocessors ever more tightly together, leading to effects such as signal leakage between components, which can slow down communication between different parts of the chip. This delay, known as the “interconnect bottleneck,” is becoming an increasing problem in high-speed computing systems.

One way to tackle the interconnect bottleneck is to use light rather than wires to communicate between different parts of a microchip. This is no easy task, however, as silicon, the material used to build chips, does not emit light easily, according to Pablo Jarillo-Herrero, an associate professor of physics at MIT.

Now, in a paper published today in the journal Nature Nanotechnology, researchers describe a light emitter and detector that can be integrated into silicon CMOS chips. The paper’s first author is MIT postdoc Ya-Qing Bie, who is joined by Jarillo-Herrero and an interdisciplinary team including Dirk Englund, an associate professor of electrical engineering and computer science at MIT.

The device is built from a semiconductor material called molybdenum ditelluride. This ultrathin semiconductor belongs to an emerging group of materials known as two-dimensional transition-metal dichalcogenides.

Unlike conventional semiconductors, the material can be stacked on top of silicon wafers, Jarillo-Herrero says.

“Researchers have been trying to find materials that are compatible with silicon, in order to bring optoelectronics and optical communication on-chip, but so far this has proven very difficult,” Jarillo-Herrero says. “For example, gallium arsenide is very good for optics, but it cannot be grown on silicon very easily because the two semiconductors are incompatible.”

In contrast, the 2-D molybdenum ditelluride can be mechanically attached to any material, Jarillo-Herrero says.

Another difficulty with integrating other semiconductors with silicon is that the materials typically emit light in the visible range, but light at these wavelengths is simply absorbed by silicon.

Molybdenum ditelluride emits light in the infrared range, which is not absorbed by silicon, meaning it can be used for on-chip communication.

To use the material as a light emitter, the researchers first had to convert it into a P-N junction diode, a device in which one side, the P side, is positively charged, while the other, N side, is negatively charged.

In conventional semiconductors, this is typically done by introducing chemical impurities into the material. With the new class of 2-D materials, however, it can be done by simply applying a voltage across metallic gate electrodes placed side-by-side on top of the material.

“That is a significant breakthrough, because it means we do not need to introduce chemical impurities into the material [to create the diode]. We can do it electrically,” Jarillo-Herrero says.

Once the diode is produced, the researchers run a current through the device, causing it to emit light.

“So by using diodes made of molybdenum ditelluride, we are able to fabricate light-emitting diodes (LEDs) compatible with silicon chips,” Jarillo-Herrero says.

The device can also be switched to operate as a photodetector, by reversing the polarity of the voltage applied to the device. This causes it to stop conducting electricity until a light shines on it, when the current restarts.

In this way, the devices are able to both transmit and receive optical signals.

The device is a proof of concept, and a great deal of work still needs to be done before the technology can be developed into a commercial product, Jarillo-Herrero says.

The researchers are now investigating other materials that could be used for on-chip optical communication.

Most telecommunication systems, for example, operate using light with a wavelength of 1.3 or 1.5 micrometers, Jarillo-Herrero says.

However, molybdenum ditelluride emits light at 1.1 micrometers. This makes it suitable for use in the silicon chips found in computers, but unsuitable for telecommunications systems.

“It would be highly desirable if we could develop a similar material, which could emit and detect light at 1.3 or 1.5 micrometers in wavelength, where telecommunication through optical fiber operates,” he says.

To this end, the researchers are exploring another ultrathin material called black phosphorus, which can be tuned to emit light at different wavelengths by altering the number of layers used. They hope to develop devices with the necessary number of layers to allow them to emit light at the two wavelengths while remaining compatible with silicon.

“The hope is that if we are able to communicate on-chip via optical signals instead of electronic signals, we will be able to do so more quickly, and while consuming less power,” Jarillo-Herrero says.

An oversupply of polysilicon will double in 2018 despite strong demand in solar and semiconductor markets, according to a report Opportunities in The Solar Cell Market For Thin Film Technology, recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

Consumption of polysilicon is booming as the semiconductor industry, particularly DRAM and NAND, is reaching record revenue and shipment growth. Solar installations are also growing strongly, increasing 35.5% in 2016.

Nevertheless, increased capacity put in place by polysilicon incumbents and capacity growth of Chinese manufactures pegged to increase 35% in 2017 is giving rise to an oversupply that will grow from 7.1% in 2016 to 15.0% in 2018.

As shown in the Table below, the industry will see an oversupply of 76,000 metric tonnes in 2018.

  2016 2018 2020
New PV (MW) 78,260 86,909 101,361
Inventory Requirement (MW) 3,913 4,345 5,068
Inventory % of demand 5% 5% 5%
Total PV Module Shipments (MW) 82,173 91,254 106,429
Efficiency loss 3% 3% 3%
Total PV Cell Shipments (MW) 84,638 93,992 109,622
Thin Film Supply (MW) 4,696 4,606 4,460
Polysilicon Consumed (Tonne/MW) 5 5 5
Total Solar Poly Required (MT) 423,696 464,804 546,845
Poly demand from Semis (MT) 34,180 40,119 39,044
Total Poly Demand (MT) 457,876 504,923 585,889
Poly Supply (MT) 490,250 580,910 640,453
Over Supply (MT) 32,374 75,987 54,564
% Over Supply 7.1% 15.0% 9.3%
Source: The Information Network (www.theinformationnet.com)

“In addition to polysilicon capacity increases, the transition from slurry wire slicing to diamond wire is creating more silicon wafers by reducing kerf loss, adding to the oversupply noted Dr. Robert Castellano, President of The Information Network.

The Information Network is a consulting and market research company addressing the semiconductor, LCD, HDD, and solar industries.