Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling.

BY IULIANA RADU and AARON THEAN, imec, Leuven, Belgium

Spin logic devices are an emerging beyond-CMOS technology that may push beyond Moore’s law, enabling functional scaling beyond the 5nm technology node. These exotic devices lend themselves to majority logic operation, which differs in many ways from the classical NAND-based operation. Imec looks into spin torque majority gates and spin wave majority gates, two concepts that completely change the way we think of computing and scaling. As shown at the 2015 IEDM conference, circuit simulations with these majority gates outperform equivalent CMOS circuits in terms of area and power consumption. Meanwhile, experimental work has been started to learn about the materials, about the devices behavior and about the technology challenges that lie ahead.

Spintronic majority gates, an efficient way to build circuits

As we approach 5nm logic technology in 2020, CMOS device density scaling faces serious challenges due to escalating process costs and parasitics. This inevitably leads to questions of sustainability of traditional Moore’s law where cost and data processing supposedly scale favorably with increasing device density. This begs the question: are there specialized devices and computational paradigms out there that break away from these fundamental trappings of CMOS scaling? The search is on and novel beyond-CMOS devices are being intensively studied.

This varied class of devices may enhance and complement the functionality of CMOS circuits. Among the promising concepts are spintronic devices (FIGURE 1), which exploit the electron’s spin, a quantum attribute that relates to magnetism, rather than its charge to perform logic operations. Spin logic devices promise to be non-volatile and lend themselves to ultralow-energy operation. But one of their biggest trumps is the ability to build majority gates, ‘democratic’ devices that return true if more than 50% of their inputs are true. For example, if two inputs are in a true state and a third one is in a false state, the expected state at the output is true. With these majority gates, logic AND and OR operations can be emulated. Also, this concept of majority logic operation differs in many ways from the classical NAND-based logic, where an output is false only if all its inputs are true. It presents a concept shift that completely changes the way we synthesize circuits. But the advantages are huge: majority gates enable arithmetic circuits that are much more compact and energy-efficient than conventional NAND or XOR gate-based circuits. For example, while a one-bit adder in CMOS technology requires about 25 transistors, the equivalent wave computing circuit only requires 5 transducers and 4 waveguides to perform the same operation.

Two ways of encoding information

Spintronic majority gates can come in several flavors, differing in the way the information is encoded and processed in the device, and in the way transduction from the charge domain to the spin (magnetism) domain is executed. At imec, two concepts are studied extensively: the spin torque majority gate (STMG) and the spin wave majority gate (SWMG).

In a STMG, the information is encoded in magnetic domain walls. Domain walls are interfaces that separate regions with different magnetization direction. The majority gate itself consists of a cross-shaped free layer that is common to 4 magnetic tunnel junctions (3 inputs, 1 output). The magnetization direction of the 3 ‘input’ free layers is switched using spin transfer torque, provided by a current through each of the magnetic tunnel junctions. Based on quantum interactions between electrons known as exchange, the domain walls propagate and interact, and the majority magnetization direction wins. The output state is measured via tunneling magnetoresistance.

In a SWMG, the computation principle is based on the interference of spin waves. The information can be encoded either in the amplitude or in the phase of the waves. Spin waves are low-energy collective excita- tions in magnetic materials. They can be generated by a so-called magneto-electric cell, which converts voltage into a spin wave. Key elements of this cell are a piezoelectric layer (that converts voltage into strain) and a magnetostrictive layer (in which the strain produces a change in magnetization or magne- tization anisotropy). In its turn, the change in magne- tization can generate a spin wave in a magnetic spin wave bus. The same cell is used to read the output state of the majority gate (FIGURE 2).

Both concepts have been studied intensively, and approaches of how to handle the computation have been proposed. An experimental demonstration is however still missing. At imec, we have enlarged our basic understanding of both STMG and SWMG and used simulations to validate device functioning. We have compared the two types of majority gates against equivalent circuits in 10nm FinFET CMOS technology. And we present our first experimental results, and highlight the main challenges for both concepts.

Spin torque majority gate – compact and technology friendly

We used micromagnetic simulations to validate the functioning of the STMG and identify its operating conditions. For this majority gate, the switching of the magnetization state is current controlled. If the applied current or the pulse length are not enough, the output fails to switch. Even if the applied current pulses provide enough energy to switch, other failure modes can appear. For example, the domain walls that are being formed can become ‘stuck’ at the crossing of the device. This happens when the width of the cross exceeds a certain value, typically in the 15-20nm range. This makes these devices difficult to demonstrate experimentally as it requires patterning and etching to small size and tight pitch between the magnetic tunnel junctions. However, this initial impediment holds great promise for further device scaling. A major advantage of this majority gate is the use of technology friendly materials, compa- rable to the materials used in magnetic memories.

We have benchmarked the device against equivalent 10nm CMOS circuits by comparing key metrics of area, power and delay. On average, the STMG circuits have about 10x smaller area, and provide a means for further scaling. However, being current controlled, the STMG circuits have a longer delay, making them less efficient than equivalent CMOS circuits. Further advances in materials stacks are needed to improve their performance, comparable to those needed in general for magnetic memory.

At imec, we are currently building the first STMG devices on 300mm wafers. Particular attention is paid to the magnetic tunnel junction pillar etch development (FIGURE 3).

Spin wave majority gate – compact, ultralow-power but challenging materials

We used micromagnetic simulations to model the spin wave propagation in SWMGs and to simulate the magnetic behavior of the magneto-electric cell that converts the applied voltage into a spin wave. This cell is a critical component for the device functionality. We mapped out the parameter space where the magneto-electric cell is expected to work optimally and used these parameter ranges as input for circuit synthesis. Building magneto- electric cells experimentally is very challenging as the materials to be used are not typically used in standard fabs and cleanrooms. For this reason, and to help choose the right materials, we have performed circuit synthesis and benchmarked them against CMOS. Based on materials parameters extracted from these simulations we have chosen a starting set of materials for our experiments.

One of the questions to be answered is how piezoelectrics behave at very high frequencies (gigahertz range) as needed for logic devices. Piezoelectric materials are being used in many applications, where they typically operate at low frequencies (up to hundreds of kHz). At imec, we started first experiments to grow piezoelectric materials in a thin film and to learn how these materials behave in the high frequency domain. And although more experiments are needed to improve the performance and map out the reliability behavior, our preliminary results are very encouraging. An important drawback of the spin wave technology is that the required materials (both the magnetostrictive and the piezoelectric materials) are very different from standard CMOS materials (FIGURE 4).

The spin wave technology was also benchmarked against CMOS circuits. The spin wave circuits take on average 3.5 times less area and about 400 times lower power than their CMOS counterparts. However, the spin wave circuits are on average 12 times slower, mainly because of the large switching delay of the magneto-electric cell. SWMGs may therefore be used for ultralow-power applications, where latency is a secondary consideration (FIGURE 5).

Building arithmetic circuits on top of CMOS

Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling. In the future, more experimental work is planned to learn about the new materials required, to validate circuit assessment, and to finally demonstrate functional devices.

Once these technologies have become more mature, we can start thinking of multi-device architectures that combine CMOS-based and spin logic devices. An interesting approach is to stack, on top of CMOS technology, arithmetic circuits made of spintronic majority gates. The high-performance functions could be executed by the CMOS-based devices and the ultralow-power functions by the spin logic arithmetic circuits. So, rather than replacing Si CMOS based transistors in the future, this beyond-CMOS technology is intended to enhance and complement the functionality of CMOS-based devices.

Spintronics belongs to the beyond-CMOS segment, where we look into new materials and device architectures, and even into new computing paradigms and circuits. Beyond-CMOS research is part of imec’s multiple roadmap scenario that is built around 3 pillars: Si extension, beyond Si and beyond CMOS. Each of these segments has its own mission and approach to enabling scaling. And each of the new technologies will bring in enabling modules and devices that will serve the application diversity in the new era of electronics: the internet of things. And the results will support the quest of the semiconductor industry to find solutions that enable continual functional scaling of cost and energy per bit by departing from the familiar CMOS scaling.

Suggested additional reading

1. Spintronic majority gates, I. P. Radu et al., IEDM 2015 (https://www.researchgate.net/publication/286882975_ Spintronic_Majority_Gates)

2. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS, O. Zografos et al., Proceedings of the 15th International IEEE Conference on Nanotechnology (NANO), 2015(http://infoscience.epfl.ch/ record/211004)

3. “With our multiple roadmap scenario, we anticipate the appli- cation diversity in the new Era of Electronics”, imec annual overview 2015, vision by Aaron Thean (click on the name of Aaron at http://magazine.imec.be/data/80/reader/reader. html?t=1452505511353#!preferred/1/package/80/pub/86/ page/8)