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At this week’s 2017 Symposia on VLSI Technology and Circuits, imec, a research and innovation hub in nano-electronics and digital technology, reported record breaking values below 10^-9 Ohm.cm² for PMOS source/drain contact resistivity. These results were obtained through shallow Gallium implantation on p-SiliconGermanium (p-SiGe) source/drain contacts with subsequent pulsed nanosecond laser anneal.

In future N7/N5 nodes, the source/drain contact area of the transistors becomes so small that the contact resistance threatens to become the dominating parasitic factor, resulting in suboptimal transistor functioning. Researchers have therefore been working on techniques to reduce the contact resistance on highly doped n-Si and p-SiGe source/drain contacts, aiming for values below 10^-9 Ohm.cm². Together with colleagues from the KU Leuven (Belgium), Fudan University (Shanghai, China), and Applied Materials (Sunnyvale, USA), imec’s specialists concentrated on p-SiGe contacts, comparing the effects of high-dose Boron and Gallium doping.

For the comparison, the researchers implanted SiGe separate wafers with a high dose of Gallium or Boron and applied various anneal processes. They then fabricated multi-ring circular transmission line model structures, which are highly sensitive to contact resistance. Subsequent measurements revealed the lowest contact resistance for the Gallium-implanted structures annealed with Applied Material’s nanosecond laser anneal. This process uniquely causes a Ge/Ga surface segregation, which is responsible for the ultralow sub-10^-9 Ohm.cm² contact resistivity. This result show a possible way to process next-generation technology nodes.

Naoto Horiguchi, distinguished member of the technical staff at imec indicated: “This breakthrough achievement in our search to develop solutions for next generation deeply-scaled CMOS provides a possible path for further performance improvement using the current source/drain schemes in N7/N5 nodes.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

imec tin

Imec, a research and innovation hub in nanoelectronics and digital technology, announced today at the 2017 Symposia on VLSI Technology and Circuits the world’s first demonstration of a vertically stacked ferroelectric Al doped HfO2 device for NAND applications. Using a new material and a novel architecture, imec has created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention. The achievement shows that ferro-electric memory is a highly promising technology at various points in the memory hierarchy, and as a new technology for storage class memory. Imec will further develop the concept in collaboration with the world’s leading producers of memory ICs.

Ferro-electric materials consist of crystals that exhibit spontaneous polarization; they can be in one of two states, which can be reversed with a suitable electric field. This non-volatile characteristic resembles ferromagnetism, after which they have been named. Discovered more than five decades ago, ferro-electric memory has always been considered ideal, due to its very low power needs, non-volatile character and high switching speed. However, issues with the complex materials, the breakdown of the interfacial layer and bad retention characteristics have presented significant challenges. The recent discovery of a ferro-electric phase in HfO2, a well-known and less complex material, has triggered a renewed interest in this memory concept.

“With HfO2, there is now a material with which we can process ferro-electric memories that are fully CMOS compatible. This allows us to make a ferro-electric FET (FeFET) in both planar and vertical varieties,” noted Jan Van Houdt, imec’s chief scientist for memory technology. “We are working to overcome some of the remaining issues, such as retention, precise doping techniques and interface properties, in order to stabilize the ferro-electric phase. We are now confident that our FeFET concept has all the required characteristics. It is, in fact, suitable for both stand-alone and embedded memories at various points in the memory hierarchy, going all the way from non-volatile DRAM to Flash-like memories. It has particularly interesting characteristics for future storage-class memory, which will help overcome the current bottleneck caused by the differences in speed between fast processors and slower mass memory.”

Imec recently presented the first, extremely positive results to its partners. The research center is now offering further development and industrialization of the vertical FeFET as a program to all its memory partners, which include the world’s major companies producing memory ICs.

“FeFETs can be used as a technology to build memory very similar to Flash-memory, but with additional advantages for further scaling, simplified processing, and power consumption,” added Van Houdt. “With our longstanding R&D and processing experience on advanced Flash, we are uniquely positioned to offer our partners a head start in this exciting opportunity. They can then decide how best to fit ferro-electric memories in their products and chips.”

Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, Toshiba, Sandisk and TSMC.

imec ferroelectric

By Paula Doe, SEMI

The future of contamination control in the next-generation supply chain for beyond 14nm-node semiconductor processes faces stringent challenges. While Moore’s Law is driving scale reduction, the industry is also facing ever-increasing process sensitivity, integration challenges of new materials and the need for unprecedented purity at process maturity.

“The supply chain needs a paradigm shift in thinking about defect control. What was just process variation for previous technology nodes can now be an excursion!” says Dr. Archita Sengupta, Intel senior GSM Technologist, leading the filtration and related supply chain contamination control program, who will discuss these challenges and possible solutions in the session on key materials issues at SEMICON West 2017 on July 11 in San Francisco at Moscone Center.

There are new materials being used for the first time, and even familiar materials need to be treated with new and different specifications. Even if the needed parameters are correctly specified, there may not be an accurate way to measure those parameters under HVM conditions, at least that most material suppliers can afford.  Chemicals, advanced filtration and purification, chemical delivery systems and equipment manufacturing can all be sources of wafer contamination. “The interaction between the tool and the chemicals is also increasingly important,” she notes. “All this is going to add more cost for the industry supply chain for quality control, but it will cost more in the end if we don’t proactively work together throughout the supply chain to figure out what matters to control and how!”

Stability is key

The most important thing material suppliers can do to meet customer quality demands is to maintain absolute stability of everything about their material and manufacturing process, suggests Jim Mulready, VP Global Quality Assurance, JSR Micro, who will also present at SEMICON West. “Traditional quality control, where the QC data at the end of my line only has to meet the customer’s specifications, doesn’t work,” he says, noting that the material supplier doesn’t have the same process tool, the same substrate, or the same process conditions as the customer, so the testing can’t duplicate the customer’s result. Moreover, the process sensitivity is getting tighter at every generation, with the tolerance of defects often being beyond the supplier’s ability to detect them. So, no specification can ever be precise enough to capture everything the customer really needs.  “Often tightening the specs doesn’t solve the problem,” he notes. “There are plenty of examples of material that was well within spec but didn’t function properly. The problem is not inadequate specs, it’s inadequate attention to other quality tools. The spec is necessary, but not sufficient.”

“The systematic (as opposed to technical) root cause of the material problems I faced as fab materials quality manager at Intel almost always came down to a problem in stability,” says Mulready, where there was a change to the material the supplier didn’t think was important, a change in the processing that they didn’t catch, or a change in the incoming raw material that they didn’t detect. “Material suppliers have to accept that the customers’ definition of quality becomes their definition of quality, and the main rule is to make sure that a material that’s working does not change at all. Consistency is the key for the end user, so it must be for us as well.  A spec alone will not measure or ensure that.  It takes robust change control, process control, and incoming raw material control.”

Semiconductor makers meanwhile, need to start paying attention not just to their immediate suppliers, but also to their suppliers’ supply chain; for example, not just the resist but also the resin and even the monomers used to make it. While the material suppliers need to qualify the incoming material, and serve as a kind of safety valve between the chemical industry and the IC makers, it can be difficult for them to control the supply quality when they are a very minor customer for the commodity chemical suppliers.  Those suppliers in turn may have no interest in investing in the tools needed to measure the particular properties of concern, and there may be a need for the IC customer to help inflict some pressure.

For more details on the SEMICON West 2017 Materials program, “Material Supply Challenges for Current and Future Leading-edge Devices,” organized by SEMI’s Chemical & Gas Manufacturers Group (CGMG), see www.semiconwest.org/programs-catalog/material-supply-leading-edge-devices. To see the full SEMICON West agenda, visit www.semiconwest.org/agenda-glance.

Graphene and related two dimensional (2D) materials have raised massive interest and investment during the last years. However, the amount of 2D-materials-based commercial devices available in the market is still very low.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

The research group led by Dr. Mario Lanza, a Young 1000 Talent Professor born in Barcelona (Spain) and based in Soochow University (China), is leading a global effort to investigate the properties of layered dielectrics. In their recent investigation, published in the journal 2D Materials, Prof. Lanza and co-workers synthesized a resistive random access memory (RRAM) using graphene/hexagonal-boron-nitride/graphene (G/h-BN/G) van der Waals structures. Furthermore, they developed a compact model to accurately describe its functioning. The model is based on the nonlinear Landauer approach for mesoscopic conductors, in this case atomic-sized filaments formed within the 2D materials system. Besides providing excellent overall fitting results (which have been corroborated in log-log, log-linear and linear-linear plots), the model is able to explain the dispersion of the data obtained from cycle-to-cycle in terms of the particular features of the filamentary paths, mainly their confinement potential barrier height.

The development of theoretical models to describe the functioning of electronic devices is one essential step enabling device/systems simulation, which is essential before device mass production. The device selected in this case, the RRAM device, is the most promising technology for future high-density information storage.

Currently, most parts of a smart phone are made of silicon and other compounds, which are expensive and break easily, but with almost 1.5 billion smart phones purchased worldwide last year, manufacturers are on the lookout for something more durable and less costly.

Dr. Elton Santos from Queen's University Belfast Credit: Queen's University Belfast

Dr. Elton Santos from Queen’s University Belfast
Credit: Queen’s University Belfast

Dr. Elton Santos from Queen’s University’s School of Mathematics and Physics, has been working with a team of top-notch scientists from Stanford University, University of California, California State University and the National Institute for Materials Science in Japan, to create new dynamic hybrid devices that are able to conduct electricity at unprecedented speeds and are light, durable and easy to manufacture in large scale semiconductor plants.

The team found that by combining semiconducting molecules C60 with layered materials, such as graphene and hBN, they could produce a unique material technology, which could revolutionise the concept of smart devices.

The winning combination works because hBN provides stability, electronic compatibility and isolation charge to graphene while C60 can transform sunlight into electricity. Any smart device made from this combination would benefit from the mix of unique features, which do not exist in materials naturally. This process, which is called van der Waals solids, allows compounds to be brought together and assembled in a pre-defined way.

Dr. Elton Santos explains: “Our findings show that this new ‘miracle material’ has similar physical properties to Silicon but it has improved chemical stability, lightness and flexibility, which could potentially be used in smart devices and would be much less likely to break.

“The material also could mean that devices use less energy than before because of the device architecture so could have improved battery life and less electric shocks.”

He added: “By bringing together scientists from across the globe with expertise in chemistry, physics and materials science we were able to work together and use simulations to predict how all of the materials could function when combined – and ultimately how these could work to help solve every day problems.

“This cutting-edge research is timely and a hot-topic involving key players in the field, which opens a clear international pathway to put Queen’s on the road-map of further outstanding investigations.”

The project initially started from the simulation side, where Dr. Santos predicted that such assembly of hBN, graphene and C60 could result in a solid with remarkable new physical and chemical properties. Then, he talked with his collaborators Professor Alex Zettl and Dr. Claudia Ojeda-Aristizabal at the University of California, and California St University in Long Beach (CA) about the findings. There was a strong synergy between theory and experiments throughout the project.

Dr. Santos said: “It is a sort of a ‘dream project’ for a theoretician since the accuracy achieved in the experiments remarkably matched what I predicted and this is not normally easy to find. The model made several assumptions that have proven to be completely right.”

The findings, which have been published in one of the most prestigious journals in the world ACS Nano, open the doors for further exploration of new materials. One issue that still needs to be solved with the team’s current research is that graphene and the new material architecture is lacking a ‘band gap’, which is the key to the on-off switching operations performed by electronic devices.

However, Dr. Santos’ team is already looking at a potential solution – transition metal dichalcogenides (TMDs). These are a hot topic at the moment as they are very chemically stable, have large sources for production and band gaps that rival Silicon.

He explains: “By using these findings, we have now produced a template but in future we hope to add an additional feature with TMDs. These are semiconductors, which by-pass the problem of the band gap, so we now have a real transistor on the horizon.”

Chemists have tried to synthesize carbon nanobelts for more than 60 years, but none have succeeded until now. A team at Nagoya University reported the first organic synthesis of a carbon nanobelt in Science. Carbon nanobelts are expected to serve as a useful template for building carbon nanotubes and open a new field of nanocarbon science.

The new nanobelt, measuring 0.83 nanometer (nm) in diameter, was developed by researchers at Nagoya University’s JST-ERATO Itami Molecular Nanocarbon Project, and the Institute of Transformative Bio-Molecules (ITbM). Scientists around the world have tried to synthesize carbon nanobelts since the 1950s and Professor Kenichiro Itami’s group has worked on its synthesis for 12 years.

“Nobody knew whether its organic synthesis was even possible or not,” says Segawa, one of the leaders of this study who had been involved in its synthesis for 7 and a half years. “However, I had my mind set on the synthesis of this beautiful molecule.”

Carbon nanobelts are belt-shaped molecules composed of fused benzene rings, which are aromatic rings consisting of six carbon atoms. Carbon nanobelts are a segment of carbon nanotubes, which have various applications in electronics and photonics due to their unique physical characteristics.

Current synthetic methods produce carbon nanotubes with inconsistent diameters and sidewall structures, which changes their electrical and optical properties. This makes it extremely difficult to isolate and purify a single carbon nanotube that has a specific diameter, length and sidewall structure. Therefore, being able to precisely control the synthesis of structurally uniform carbon nanotubes will help develop novel and highly functional materials.

Carbon nanobelts have been identified as a way to build structurally uniform carbon nanotubes. However, synthesizing carbon nanobelts is challenging due to their extremely high strain energies. This is because benzene is stable when flat, but becomes unstable when they are distorted by fusion of the rings.

To overcome this problem, Guillaume Povie, a postdoctoral researcher of the JST-ERATO project, Yasutomo Segawa, a group leader of the JST-ERATO project, and Kenichiro Itami, the director of JST-ERATO project and the center director of ITbM, have succeeded in the first chemical synthesis of a carbon nanobelt from a readily available precursor, p-xylene (a benzene molecule with two methyl groups in the 1,4- (para-) position) in 11 steps.

The key to this success is their synthetic strategy based on the belt-shaped formation from a macrocycle precursor with relatively low ring strain. In their strategy, the team prepared a macrocycle precursor from p-xylene in 10 steps, and formed the belt-shaped aromatic compound by a coupling reaction. Nickel was essential to mediate the coupling process.

“The most difficult part of this research was this key coupling reaction of the macrocycle precursor,” says Povie. “The reaction did not proceed well day after day and it took me three to four months for testing various conditions. I have always believed where there’s a will, there’s a way.”

In 2015, Itami launched a new initiative in his ERATO project to focus particularly on the synthesis of the carbon nanobelt. At the so-called “belt festival,” various new synthetic routes for the carbon nanobelt were proposed and more than 10 researchers were involved in the project. On September 28, 2016, exactly a year after the start of the festival, the carbon nanobelt structure was finally revealed by X-ray crystallography in front of the Itami group members. Everyone held their breath while staring at the screen during X-ray analysis, and cheered when the cylindrical shape image of the carbon nanobelt appeared on the screen. Itami, Segawa and Povie expressed their joy with a high five (movie: https://www.youtube.com/watch?v=cABZla9w0uo).

“It was one of the most exciting moments in my life and I will never forget it,” says Itami. “Since this is the result of a decade-long study, I greatly appreciate all the past and current members of my group for their support and encouragement. Thanks to their skill, toughness, sense and strong will of all members, we achieved this successful result.”

The synthesized carbon nanobelt is a red-colored solid and exhibits deep red fluorescence. Analysis by X-ray crystallography revealed that the carbon nanobelt has a cylindrical shape in the same manner as carbon nanotubes. The researchers also measured its light absorption and emission, electric conductivity and structural rigidity by ultraviolet-visible absorption fluorescence, and Raman spectroscopic studies, as well as theoretical calculations.

“Actually, the synthesis part was finished last August but I could not rest until I was able to confirm the X-ray structure of the carbon nanobelt,” says Povie. “I was really happy when I saw the X-ray structure.”

The carbon nanobelt will be released to the market in the future. “We are looking forward to discovering new properties and functionalities of the carbon nanobelt with researchers from all over the world,” say Segawa and Itami.

Two-dimensional graphene consists of single layers of carbon atoms and exhibits intriguing properties. The transparent material conducts electricity and heat extremely well. It is at the same time flexible and solid. Additionally, the electrical conductivity can be continuously varied between a metal and a semiconductor by, e.g., inserting chemically bound atoms and molecules into the graphene structure – the so-called functional groups. These unique properties offer a wide range of future applications as e.g. for new developments in optoelectronics or ultrafast components in the semiconductor industry. However, a successful use of graphene in the semiconductor industry can only be achieved if properties such as the conductivity, the size and the defects of the graphene structure induced by the functional groups can already be modulated during the synthesis of graphene.

In an international collaboration scientists led by Andreas Hirsch from the Friedrich-Alexander-Universität Erlangen-Nürnberg in close cooperation with Thomas Pichler from the University of Vienna accomplished a crucial breakthrough: using the latter’s newly developed experimental set-up they were able to identify, for the first time, vibrational spectra as the specific fingerprints of step-by-step chemically modified graphene by means of light scattering. This spectral signature, which was also theoretically attested, allows to determine the type and the number of functional groups in a fast and precise way. Among the reactions they examined, was the chemical binding of hydrogen to graphene. This was implemented by a controlled chemical reaction between water and particular compounds in which ions are inserted in graphite, a crystalline form of carbon.

This is a section of a graphene network with chemically bound hydrogen atom: the spectral vibrational signature of the single carbon-carbon bonds adjacent to the bound hydrogen atom is highlighted in different colors. Copyright: Frank Hauke, FAU

This is a section of a graphene network with chemically bound hydrogen atom: the spectral vibrational signature of the single carbon-carbon bonds adjacent to the bound hydrogen atom is highlighted in different colors. Copyright: Frank Hauke, FAU

Additional benefits

“This method of the in-situ Raman spectroscopy is a highly effective technique which allows controlling the function of graphene in a fast, contact-free and extensive way already during the production of the material,” says J. Chacon from Yachay Tech, one of the two lead authors of the study. This enables the production of tailored graphene-based materials with controlled electronic transport properties and their utilisation in semiconductor industry.

A case study is presented based on the use of high throughput experimentation (HTE) for the discovery of new memory materials.

BY LARRY CHEN, MARK CLARK, CHARLENE CHEN, SUSAN CHENG and MILIND WELING, IMI Inc., San Jose, CA

The ever increasing demands for data translate into more sophisticated and specific thin film requirements for semiconductor materials. Each film layer has to not only demonstrate desired film properties, but also show good interfacial behavior with neighboring layers to contribute to the performance of the whole film stack or device. As a result, modern thin film material systems are including more elements from the periodic table with more complex compositions. The demand for short time to market has also increased, making the development of new materials even more difficult. In this paper, we present a case study of using high throughput experimentation (HTE) for the discovery of new memory materials. By using a combinatorial approach of sputtering technology, HTE can be applied to PVD chalcogenides and other materials targeted at memory semiconductors.
PVD background

Ever since the deposition of materials by magnetron sputtering was introduced by F. M. Penning, the technology has become a major method for industrial thin film deposition, which typically generates dense, hard, and robust thin film materials at relatively low production cost. The technology has been applied to major industries such as semiconductors, photovoltaics, optical coatings, displays, hard mechanical coatings, and so on. However, optimizing the magnetron sputtering processes has always been challenging to process and hardware design engineers, since material properties like density, crystalline structure, grain size, optical indices of a deposited film strongly depend on various process parameters, such as power, pressure, substrate temperature, sputter gas type, plasma type, sputter source to substrate distance, substrate bias, and pumping throughput. Additionally, the material properties heavily depend on the underlying layers, including the chosen substrate, below a film stack due to a texture effect in film structure and a formation of interfacial layers which comes from the intermixing of both materials. All the above parameters contribute to increasing the level of complexity of the development.

The semiconductor industry is constantly searching for new materials with unprecedented physical, optical, electrical, and mechanical properties, not only as a single film but also as a component of complex featured film stacks or functioning devices. This requires exploration of new materials not limited to pure or binary systems, but to ternary, quaternary systems and beyond. A very efficient solution to cope with the increasing complexity of development and the demand for short development time is a combinatorial approach.

The combinatorial approach can be defined as a process that couples the capability for parallel production of large arrays of diverse materials together with different high-throughput measurement techniques for various intrinsic and performance properties supported by data analytics for identifying lead materials [3]. For magnetron sputtering technology, the optimization of process param- eters has to be included as a major component of combinatorial approach. Considering all the multi-dimensional space of the development mentioned above, the combinatorial approach can be an excellent and efficient way of developing new materials in magnetron sputtering in terms of cost and time.

HTE methodology for PVD materials discovery

Platform Considerations As all process parameters in magnetron sputtering are somewhat correlated, it has been challenging for process engineers to come up with fully optimized process parameters for thin film production. In addition, semiconductor production facilities are typically optimized for consistent, efficient, high volume production of a single product at a time, and not for a wide range of simultaneous experiments. These factors make it challenging for memory manufacturers to test multiple materials, conditions and devices in an efficient manner, and without compromising either data quality or production throughput.

IMI’s high throughput experimentation (HTE) platform is set up for accelerated experimentation. Its combina- torial PVD tool typically has four sputter guns and one additional port at the center. All sputter guns can be equipped with various types of target materials including chalcogenides, puremetals, oxides, and nitrides, and each sputter source can be operated by different plasma modes independently, such as direct current (DC), pulsed direct current (PDC), and radio frequency (RF) with the ability to co-sputter with all four guns. The additional port at the center can be equipped with an ion beam source for ion beam assisted deposition, or ion beam cleaning, or an additional sputter gun which enables five gun co-sputtering operation. Process parameter windows can cover larger regimes than most production tool process parameters (Table 1).

Screen Shot 2017-04-28 at 1.03.58 PM

FIGURE 1 shows an example of a multi-target sputter chamber capable of controllably forming a variety of compounds in an array across a 300 mm substrate and an example substrate shown at right. The materials can also be deposited on a die-to-die basis (not shown) over a 300mm wafer test vehicle for direct device testing without the need for patterning. The effectiveness of the combinatorial screening can be increased by guiding the selection of material compositions using both semi-phenomenological and DFT-based modeling, as well as relating the experimental data to the results obtained from simulated annealing using ab-initio molecular dynamics and further DFT analysis of the simulated quasi-amorphous structures.

Deposition methodology

Two different methods can be used to deposit the combinatorial films of interest: site isolated spot and gradient approaches. For the site isolated spot approach, multiple numbers of spots were deposited on a substrate. Each individual spot represents a split condition from a design of experiment (DOE). Film composition can be controlled through the co-sputter of guns, which are equipped with targets consisting of different materials. Also, the process condition of each spot can be varied through the process parameter settings. All deposition conditions and procedures are fully automated.

In the gradient approach, non-uniform film in terms of composition and thickness is intentionally generated on top of a substrate by co-sputtering through an open large area aperture. A semi-empirical model is used for the control of non-uniformity. The modeling also helps in controlling the film composition throughout a target’s lifetime. In this approach, composition gradients and the thickness gradients can be generated by a single film deposition on a substrate. Theoretically, an infinite number of variations can be analyzed within a film, which is only limited by the spatial resolution of metrologies.

Characterization and device performance

Once films have been deposited via PVD, characterization can be carried out, including testing of physical, optical and electrical parameters. These can range from general film characteristics including composition, thickness and crystallinity, to device-specific electrical parameters such as leakage, threshold voltage, and On/ Off ratio.

Measuring and analyzing large numbers of data generated from HTE methodology can be time- consuming. By using the automated metrology tools and a unified database system, measurements and analysis steps can be expedited to limit bottlenecks and deliver data most efficiently. A multi-stage approach can also help to prioritize and focus experimental resources on the most promising candidates.

Screen Shot 2017-04-28 at 1.04.05 PM

HTE vs traditional methods

Key benefits of the HTE approach include the expedited learning cycle, cost reduction, and improved data quality. For semiconductor applications, a single 200mm or 300mm wafer can hold more than 30 splits, which can lead to a reduction in cycle of learning time (one device wafer instead of more than 30). Additionally, as all spots on a single wafer go through the same follow-up device fabrication steps together, data can be free from unexpected fluctuations of subsequent steps. Overall, the HTE approach can expedite the learning cycle by 5 ~ 10 times compared to single substrate based approach. A comparison of both HTE with traditional methods is summarized in Table 2.

Screen Shot 2017-04-28 at 1.04.12 PM

A case study in NVM

New materials for memory elements such as non-volatile memory (NVM) selectors must meet a wide range of performance parameters (FIGURE 3 shows a typical memory cell with the selector element called out), in order to reduce sneak currents and manage variability in memory arrays.

Screen Shot 2017-05-12 at 12.20.15 PM

 

Table 3 lists some of the key parameters desired in a memory selector material.

Of course, optimizing all of these parameters simultaneously in a single element or compound (and one that is practical for high volume memory manufacturing) is challenging. IMI’s HTE methodology enables rapid and simultaneous optimization of key trade-offs between performance, reliability and integration, in the quest for an ideal selector.

HTE for NVM selector materials

Use of a HTE methodology allows rapid screening of NVM selector candidate material compounds, compo- sitions and stacks. IMI has conducted multiple customer engagements in memory selector materials screening, and a typical experimental workflow is outlined in FIGURE 4, showing progression from PVD deposition, through physical and electrical characterizations of films and devices.

Screen Shot 2017-04-28 at 1.04.28 PM

This experimental process can be carried out multiple times, through subsequently more advanced stages on a fewer number of samples, as promising candidates are narrowed down and further optimized. FIGURE 5 shows a possible strategy for testing a series of candi- dates through three different stages. In the earlier stages, a wide range of options could be screened quickly, but the more extensive (and time consuming) characterization and analysis can be saved for later stages, when only the best performing candidates are already selected. This enables the best use of deposition and testing resources, leading to optimal results in an efficient timeframe.

Screen Shot 2017-04-28 at 1.04.36 PM Screen Shot 2017-04-28 at 1.04.41 PM

Fast and high-quality experimental results

IMI has extensive experience in working both on dynamic random access memory (DRAM) as well as NVM materials. In DRAM, the company has worked on development of dielectric, electrode and interface layer materials. IMI’s process engineers, materials scientists and electrical engineers work upfront with a customer on the design of experiments to ensure the delivery of rapid cycles of learning with the most efficient use of resources.

A typical customer project might range between a few months up to a year or more, encompassing hundreds or even thousands of different experiments. In NVM selectors alone, IMI has conducted:
• 2500+experiments on Metal Chalcogenides
• 2000+ experiments on MIEC
• 1000+experiments on Transition Metal Oxides

Conclusion

High throughput experimentation can offer rapid, high quality materials data when effectively applied to PVD memory selector development. However it does require an advanced platform, and a facility and team experienced in efficient deposition and testing of the materials and devices. Materials and device expertise is also helpful in managing and optimizing the experimental workflow for maximum efficiency and high quality data.

The new Samsung Galaxy S8 equipped with 64 gigabytes (GB) of NAND flash memory carries a bill of materials (BOM) cost that comes out to US$301.60, much higher than for previous versions of the company’s smartphones, according to a preliminary estimate from IHS Markit (Nasdaq: INFO).

After $5.90 in basic manufacturing costs are added, Samsung’s total cost to make the Galaxy S8 rises to $307.50; the unsubsidized price for a 64GB Galaxy S8 starts at around $720. The preliminary estimated total at this point is $43.34 higher than that of the Galaxy S7 previously performed by IHS Markit, and is $36.29 higher than the total build cost of the Galaxy S7 Edge, considered a better comparison to the Galaxy S8. IHS Markit has not yet performed a teardown analysis on the larger Galaxy S8 Plus.

“The higher total BOM costs for the Galaxy S8 seem to be part of a trend that reflects something of an arms race in features among Apple, Samsung and other phone manufacturers, as they all try to add new and distinguishing hardware features,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “While there are new non-hardware features in the Galaxy S8, such as a virtual assistant called Bixby, from a teardown perspective the hardware in the Galaxy S8 and that of the forthcoming new iPhone is expected to be very similar.”

The introduction of the Galaxy S8 comes at a delicate time for the embattled South Korean electronics giant, which is eager to put behind the challenges associated with the Galaxy Note 7, whose exploding batteries prompted a worldwide recall.

The latest salvo from Samsung shows how it’s keen to regain consumer confidence and attain leadership in the smartphone landscape, a nearly saturated but still highly competitive space that remains key to retaining subscriber loyalties and winning new converts.

First smartphone capable of gigabit-LTE speeds

Both the Galaxy S8 and S8 Plus feature a 10-nanometer (nm) system-on-chip (SoC) along with CAT-16 LTE modem and radio. The CDMA version of the S8, intended for use in the United States as well as in China, will feature the Snapdragon 835 chipset from San Diego-based Qualcomm. In comparison, a version of the phone featuring Samsung’s homegrown Exynos 8895 chipset will be used for the rest of the world.

The CAT-16 LTE radio allows the new Galaxy phone to aggregate three carriers of up to 20 megahertz each. Combined with 4×4 MIMO antennas and higher-order modulation of 256 QAM, the LTE modem is capable of reaching peak theoretical speeds of one gigabit per second. “Gigabit LTE is very much the marquee specification for 2017 flagship smartphones,” said Wayne Lam, principal analyst of smartphone electronics, IHS Markit. “Keep in mind that gigabit speeds are a best-case scenario and that a user’s real-world experience will be limited to what mobile networks can provide.”

New “Infinity Display” design fits better in hand

The redesigned Galaxy S8 has a tall, narrow shape that is 1.5 millimeters narrower than the previous Galaxy S7, providing slick new ergonomics while also optimizing screen real estate. The screen curves around the edges, and Samsung designers have maximized the display, relative to the size of the phone, with a 5.8-inch 2960×1440 AMOLED display and an elongated aspect ratio of 18.5:9. Compared to conventional 16:9 aspect-ratio Quad HD smartphone displays, the Galaxy S8 features an additional 15 percent more pixels in a form factor that is easier to hold in the hand. The device’s haptic engine, which provides the “click” feel for users, also has been improved for longer-duty cycles and a more dynamic response.

Double the base-model storage

Both the Galaxy S8 and S8 Plus feature 4GB of RAM and built-in storage of 64GB—twice the standard built-in storage found in the Galaxy S7 as well as the iPhone 7. Storage for the new Samsung phones can also be expanded, up to 256GB, via a microSD card. The Samsung NAND flash memory and DRAM on the S8 come in at a cost of $41.50. Rassweiler said: “While in previous years the cost per gigabyte has generally fallen in both the NAND flash and DRAM areas, we have seen rising prices in both DRAM and NAND flash recently due to some tightness in the marketplace. The cost of memory in the S8 reflects these recent market dynamics, even though we expect the erosion in memory pricing—something that occurs regularly in the memory market—to resume during the course of the year.”

Battery

The battery capacity on the Galaxy S8, at 3000 milliamp hour (mAh), is the same as that found in last year’s Galaxy S7. However, compared to the Galaxy S7 Edge, which had a 3600mAh battery, Samsung played it safe after the Note 7 incident and included a considerably less dense battery pack. Overall cost estimate for the Galaxy S8 battery pack is $4.50.

Single camera lens

Although the Galaxy S8 and S8 Plus come with new features and the latest components, each still has only a single camera in the back—essentially the same as the camera module found in last year’s Galaxy S7. Apple’s iPhone 7 Plus, the newly launched LG G6 and many Chinese OEMs are now promoting dual cameras as a key feature. Owing to the asymmetric placement of the rear fingerprint sensor, it would have been likely that a dual-camera design was scrapped at the last minute in the design cycle.

Reflecting the structure of composites found in nature and the ancient world, researchers at the University of Illinois at Urbana-Champaign have synthesized thin carbon nanotube (CNT) textiles that exhibit both high electrical conductivity and a level of toughness that is about fifty times higher than copper films, currently used in electronics.

Scanning Electron Microscope Images of architectured carbon nanotube (CNT) textile made at Illinois. Colored schematic shows the architecture of self-weaved CNTs, and the inset shows a high resolution SEM of the inter-diffusion of CNT among the different patches due to capillary splicing. Credit: University of Illinois

Scanning Electron Microscope Images of architectured carbon nanotube (CNT) textile made at Illinois. Colored schematic shows the architecture of self-weaved CNTs, and the inset shows a high resolution SEM of the inter-diffusion of CNT among the different patches due to capillary splicing. Credit: University of Illinois

“The structural robustness of thin metal films has significant importance for the reliable operation of smart skin and flexible electronics including biological and structural health monitoring sensors,” explained Sameh Tawfick, an assistant professor of mechanical science and engineering at Illinois. “Aligned carbon nanotube sheets are suitable for a wide range of application spanning the micro- to the macro-scales including Micro-Electro-Mechanical Systems (MEMS), supercapacitor electrodes, electrical cables, artificial muscles, and multi-functional composites.

“To our knowledge, this is the first study to apply the principles of fracture mechanics to design and study the toughness nano-architectured CNT textiles. The theoretical framework of fracture mechanics is shown to be very robust for a variety of linear and non-linear materials.”

Carbon nanotubes, which have been around since the early nineties, have been hailed as a “wonder material” for numerous nanotechnology applications, and rightly so. These tiny cylindrical structures made from wrapped graphene sheets have diameter of a few nanometers–about 1000 times thinner than a human hair, yet, a single carbon nanotube is stronger than steel and carbon fibers, more conductive than copper, and lighter than aluminum.

However, it has proven really difficult to construct materials, such as fabrics or films that demonstrate these properties on centimeter or meter scales. The challenge stems from the difficulty of assembling and weaving CNTs since they are so small, and their geometry is very hard to control.

“The study of the fracture energy of CNT textiles led us to design these extremely tough films,” stated Yue Liang, a former graduate student with the Kinetic Materials Research group and lead author of the paper, “Tough Nano-Architectured Conductive Textile Made by Capillary Splicing of Carbon Nanotubes,” appearing in Advanced Engineering Materials. To our knowledge, this is the first study of the fracture energy of CNT textiles.

Beginning with catalyst deposited on a silicon oxide substrate, vertically aligned carbon nanotubes were synthesized via chemical vapor deposition in the form of parallel lines of 5μm width, 10μm length, and 20-60μm heights.

“The staggered catalyst pattern is inspired by the brick and mortar design motif commonly seen in tough natural materials such as bone, nacre, the glass sea sponge, and bamboo,” Liang added. “Looking for ways to staple the CNTs together, we were inspired by the splicing process developed by ancient Egyptians 5,000 years ago to make linen textiles. We tried several mechanical approaches including micro-rolling and simple mechanical compression to simultaneously re-orient the nanotubes, then, finally, we used the self-driven capillary forces to staple the CNTs together.”

“This work combines careful synthesis, and delicate experimentation and modeling,” Tawfick said. “Flexible electronics are subject to repeated bending and stretching, which could cause their mechanical failure. This new CNT textile, with simple flexible encapsulation in an elastomer matrix, can be used in smart textiles, smart skins, and a variety of flexible electronics. Owing to their extremely high toughness, they represent an attractive material, which can replace thin metal films to enhance device reliability.”

In addition to Liang and Tawfick, co-authors include David Sias and Ping Ju Chen.