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Glass fibres do everything from connecting us to the internet to enabling keyhole surgery by delivering light through medical devices such as endoscopes. But as versatile as today’s fiber optics are, scientists around the world have been working to expand their capabilities by adding semiconductor core materials to the glass fibers.

Ursula Gibson, a professor of physics at the Norwegian University of Science and Technology, holds a glass fiber with a semiconductor core. Rapid heating and cooling of this kind of fiber allows the researchers to make functional materials with applications beyond traditional fiber optics. Credit: Nancy Bazilchuk

Ursula Gibson, a professor of physics at the Norwegian University of Science and Technology, holds a glass fiber with a semiconductor core. Rapid heating and cooling of this kind of fiber allows the researchers to make functional materials with applications beyond traditional fiber optics. Credit: Nancy Bazilchuk

Now, a team of researchers has created glass fibers with single-crystal silicon-germanium cores. The process used to make these could assist in the development of high-speed semiconductor devices and expand the capabilities of endoscopes says Ursula Gibson, a physics professor at the Norwegian University of Science and Technology and senior author of the paper.

“This paper lays the groundwork for future devices in several areas,” Gibson said, because the germanium in the silicon core allows researchers to locally alter its physical attributes.

The article, “Laser recrystallization and inscription of compositional microstructures in crystalline SiGe-core fibres,” was published in Nature Communications on October 24.

Melting and recrystallizing

To understand what the researchers did, you need to recognize that silicon and germanium have different melting points. When the two substances are combined in a glass fiber, flecks of germanium-rich material are scattered throughout the fiber in a disorderly way because the silicon has a higher melting point and solidifies, or “freezes” first. These germanium flecks limit the fiber’s ability to transmit light or information. “When they are first made, these fibers don’t look very good,” Gibson said.

But rapidly heating the fiber by moving it through a laser beam allowed the researchers to melt the semiconductors in the core in a controlled fashion. Using the difference in the solidification behavior, the researchers were able to control the local concentration of the germanium inside the fiber depending upon where they focused the laser beam and for how long.

“If we take a fibre and melt the core without moving it, we can accumulate small germanium-rich droplets into a melt zone, which is then the last thing to crystalize when we remove the laser slowly,” Gibson said. “We can make stripes, dots… you could use this to make a series of structures that would allow you to detect and manipulate light.”

An interesting structure was produced when the researchers periodically interrupted the laser beam as it moved along their silicon-germanium fibre. This created a series of germanium-rich stripes across the width of the 150-micrometer diameter core. That kind of pattern creates something called a Bragg grating, which could help expand the capability of long wavelength light-guiding devices. “That is of interest to the medical imaging industry,” Gibson said.

Rapid heating, cooling key

Another key aspect of the geometry and laser heating of the silicon-germanium fibre is that once the fibre is heated, it can also be cooled very quickly as the fibre is carried away from the laser on a moving stage.

Controlled rapid cooling allows the mixture to solidify into a single uniform crystal the length of the fibre — which makes it ideal for optical transmission.

Previously, people working with bulk silicon-germanium alloys have had problems creating a uniform crystal that is a perfect mix, because they have not had sufficient control of the temperature profile of the sample.

“When you perform overall heating and cooling, you get uneven composition through the structure, because the last part to freeze concentrates excess germanium,” Gibson said. “We have shown we can create single crystalline silicon-germanium at high production rates when we have a large temperature gradient and a controlled growth direction.”

Transistors that switch faster

Gibson says the laser heating process could also be used to simplify the incorporation of silicon-germanium alloys into transistor circuits.

“You could adapt the laser treatment to thin films of the alloy in integrated circuits,” she said.

Traditionally, Gibson said, electronics researchers have looked at other materials, such as gallium arsenide, in their quest to build ever-faster transistors. However, the mix of silicon and germanium, often called SiGe, allows electrons to move through the material more quickly than they move through pure silicon, and is compatible with standard integrated circuit processing.

“SiGe allows you to make transistors that switch faster” than today’s silicon-based transistors, she said, “and our results could impact their production.”

A new design for solar cells that uses inexpensive, commonly available materials could rival and even outperform conventional cells made of silicon.

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

A tandem perovskite solar cell boosts efficiency by absorbing high- and low-energy photons from the sun. Credit: Rongrong Cheacharoen/Stanford University

Writing in the Oct. 21 edition of Science, researchers from Stanford and Oxford describe using tin and other abundant elements to create novel forms of perovskite – a photovoltaic crystalline material that’s thinner, more flexible and easier to manufacture than silicon crystals.

“Perovskite semiconductors have shown great promise for making high-efficiency solar cells at low cost,” said study co-author Michael McGehee, a professor of materials science and engineering at Stanford. “We have designed a robust, all-perovskite device that converts sunlight into electricity with an efficiency of 20.3 percent, a rate comparable to silicon solar cells on the market today.”

The new device consists of two perovskite solar cells stacked in tandem. Each cell is printed on glass, but the same technology could be used to print the cells on plastic, McGehee added.

“The all-perovskite tandem cells we have demonstrated clearly outline a roadmap for thin-film solar cells to deliver over 30 percent efficiency,” said co-author Henry Snaith, a professor of physics at Oxford. “This is just the beginning.”

Tandem technology

Previous studies showed that adding a layer of perovskite can improve the efficiency of silicon solar cells. But a tandem device consisting of two all-perovskite cells would be cheaper and less energy-intensive to build, the authors said.

“A silicon solar panel begins by converting silica rock into silicon crystals through a process that involves temperatures above 3,000 degrees Fahrenheit (1,600 degrees Celsius),” said co-lead author Tomas Leijtens, a postdoctoral scholar at Stanford. “Perovskite cells can be processed in a laboratory from common materials like lead, tin and bromine, then printed on glass at room temperature.”

But building an all-perovskite tandem device has been a difficult challenge. The main problem is creating stable perovskite materials capable of capturing enough energy from the sun to produce a decent voltage.

A typical perovskite cell harvests photons from the visible part of the solar spectrum. Higher-energy photons can cause electrons in the perovskite crystal to jump across an “energy gap” and create an electric current.

A solar cell with a small energy gap can absorb most photons but produces a very low voltage. A cell with a larger energy gap generates a higher voltage, but lower-energy photons pass right through it.

An efficient tandem device would consist of two ideally matched cells, said co-lead author Giles Eperon, an Oxford postdoctoral scholar currently at the University of Washington.

“The cell with the larger energy gap would absorb higher-energy photons and generate an additional voltage,” Eperon said. “The cell with the smaller energy gap can harvest photons that aren’t collected by the first cell and still produce a voltage.”

The smaller gap has proven to be the bigger challenge for scientists. Working together, Eperon and Leijtens used a unique combination of tin, lead, cesium, iodine and organic materials to create an efficient cell with a small energy gap.

“We developed a novel perovskite that absorbs lower-energy infrared light and delivers a 14.8 percent conversion efficiency,” Eperon said. “We then combined it with a perovskite cell composed of similar materials but with a larger energy gap.”

The result: A tandem device consisting of two perovskite cells with a combined efficiency of 20.3 percent.

“There are thousands of possible compounds for perovskites,” Leijtens added, “but this one works very well, quite a bit better than anything before it.”

Seeking stability

One concern with perovskites is stability. Rooftop solar panels made of silicon typically last 25 years or more. But some perovskites degrade quickly when exposed to moisture or light. In previous experiments, perovskites made with tin were found to be particularly unstable.

To assess stability, the research team subjected both experimental cells to temperatures of 212 degrees Fahrenheit (100 degrees Celsius) for four days.

“Crucially, we found that our cells exhibit excellent thermal and atmospheric stability, unprecedented for tin-based perovskites,” the authors wrote.

“The efficiency of our tandem device is already far in excess of the best tandem solar cells made with other low-cost semiconductors, such as organic small molecules and microcrystalline silicon,” McGehee said. “Those who see the potential realize that these results are amazing.”

The next step is to optimize the composition of the materials to absorb more light and generate an even higher current, Snaith said.

“The versatility of perovskites, the low cost of materials and manufacturing, now coupled with the potential to achieve very high efficiencies, will be transformative to the photovoltaic industry once manufacturability and acceptable stability are also proven,” he said.

Researchers have found an unexpected way to control the thermal conductivity of two-dimensional (2-D) materials, which will allow electronics designers to dissipate heat in electronic devices that use these materials.

2-D materials have a layered structure, with each layer having strong bonds horizontally, or “in plane,” and weak bonds between the layers, or “out of plane.” These materials have unique electronic and chemical properties, and hold promise for use in creating flexible, thin, lightweight electronic devices.

For many of these potential applications, it’s important to be able to dissipate heat efficiently. And this can be tricky. In 2-D materials, heat is conducted differently in plane than it is out of plane.

For example, in one class of 2-D materials, called TMDs, heat is conducted at 100 watts per meter per Kelvin (W/mK) in plane, but at only 2 W/mK out of plane. That gives it a “thermal anisotropy ratio” of about 50.

To better understand the thermal conduction properties of 2-D materials, a team of researchers from North Carolina State University, the University of Illinois at Urbana-Champaign (UI) and the Toyota Research Institute of North America (TRINA) began experimenting with molybdenum disulfide (MoS2), which is a TMD.

The researchers found that, by introducing disorder to the MoS2, they could significantly alter the thermal anisotropy ratio.

The researchers created this disorder by introducing lithium ions between the layers of MoS2. The presence of the lithium ions does two things simultaneously: it puts the layers of the 2-D material out of alignment with each other, and it forces the MoS2 to rearrange the structure of its component atoms.

When the ratio of lithium ions to MoS2 reached 0.34, the in-plane thermal conductivity was 45 W/mK, and the out-of-plane thermal conductivity dropped to 0.4 W/mK- increasing the material’s thermal anisotropy ratio from 50 to more than 100. In other words, heat became more than twice as likely to travel in plane — along the layer, rather than between the layers.

And that was as good as it got. Adding fewer lithium ions made the thermal anisotropy ratio lower. Adding more ions also made it lower. But in both cases, the ratio was affected in a predictable way, meaning that the researchers could tune the material’s thermal conductivity and thermal anisotropy ratio.

“This finding was very counter-intuitive,” says Jun Liu, an assistant professor of mechanical and aerospace engineering at NC State and co-corresponding author of a paper describing the work. “The conventional wisdom has been that introducing disorder to any material would decrease the thermal anisotropy ratio.

“But based on our observations, we feel that this approach to controlling thermal conductivity would apply not only to other TMDs, but to 2-D materials more broadly,” Liu says.

“We set out to advance our fundamental understanding of 2-D materials, and we have,” Liu adds. “But we also learned something that is likely to be of practical use for the development of technologies that make use of 2-D materials.”

Researchers at the Center for Multidimensional Carbon Materials (CMCM), within the Institute for Basic Science (IBS) have demonstrated graphene coating protects glass from corrosion. Their research, published in ACS Nano, can contribute to solving problems related to glass corrosion in several industries. Glass has a high degree of both corrosion and chemical resistance. For this reason it is the primary packaging material to preserve medicines and chemicals. However, over time at high humidity and pH, some glass types corrode. Corroded glass loses its transparency and its strength is reduced. As a result, the corrosion of silicate glass, the most common and oldest form of glass, by water is a serious problem especially for the pharmaceutical, environmental and optical industries, and in particular in hot and humid climates.

Although there are different types of glass, ordinary glazing and containers are made of silicon dioxide (SiO2), sodium oxide (Na2O) along with minor additives. Glass corrosion begins with the adsorption of water on the glass surface. Hydrogen ions from water then diffuse into the glass and exchange with the sodium ions present on the glass surface. The pH of the water near the glass surface increases, allowing the silicate structure to dissolve.

Scientists have been looking at how to coat glass to protect it from damage. An ideal protective coating should be thin, transparent, and provide a good diffusion barrier to chemical attack. Graphene with its chemical inertness, thinness, and high transparency makes it very promising as a coating material. Moreover, owing to its excellent chemical barrier properties it blocks helium atoms from penetrating through it. The use of graphene coating is being explored as a protective layer for other materials requiring resistance to corrosion, oxidation, friction, bacterial infection, electromagnetic radiation, etc.

IBS scientists grew graphene on copper using a technique previously invented by Prof. Rodney S. Ruoff and collaborators, and transferred either one or two atom-thick layers of graphene onto both sides of rectangular pieces of glass. The effectiveness of the graphene coating was evaluated by water immersion testing and observing the differences between uncoated and coated glass. After 120 days of immersion in water at 60°C, uncoated glass samples had significantly increased in surface roughness and defects, and reduced in fracture strength. In contrast, both the single and double layer graphene-coated glasses had essentially no change in both fracture strength and surface roughness.

“The purpose of the study was to determine whether graphene grown by chemical vapor deposition on copper foils, a now established method, could be transferred onto glass, and protect the glass from corrosion. Our study shows that even one atom-thick layer of graphene does the trick,” explains Prof. Ruoff, director of the CMCM and Professor at the Ulsan National Institute of Science and Technology (UNIST). “In the future, when it is possible to produce larger and yet higher-quality graphene sheets and to optimize the transfer on glass, it seems reasonably likely that graphene coating on glass will be used on an industrial scale.”

By Paula Doe, SEMI

As the rate of traditional scaling slows, the chip sector looks increasingly to materials and design to move forward on multiple paths for multiple applications. Figuring out more effective ways to collaborate across silos will be crucial.

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

  1. Paradigm shift requires co-optimization

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“Scaling has hit a wall, and there is no longer any single path forward,” noted Larry Clevenger, BEOL Architect and Technology Definition, IBM Research, at the SEMI Strategic Materials Conference 2016 (September 20-21). “The materials set we use in the middle and back end of line is running out of steam. We need new materials and design co-optimization.”  He noted EUV would much improve the critical tight pitch areas for the memory and BEOL for 7nm-5nm logic. But reducing the parasitics in the metal interconnect in middle of the line and BEOL will also be critical, with good results demonstrated from new materials like Si:P and Ge:Ga meta-stable alloys, cobalt instead of tungsten, self-forming encapsulation of copper by cobalt, and airgaps, all of which would require optimization of an ecosystem of appropriate cleaning, deposition and wet process technologies for integration. Changing the design to route the critical paths directly up to higher wiring levels where the wires are larger would also help reduce resistance.

“It’s a paradigm shift that what was once a process deviation is now an excursion,” said Archita Sengupta, Intel senior technologist, noting the need for new specialized tools to measure, monitor and control the process to detect ever tinier defects sooner. “We need more proactive cooperation across the supply chain for bottom up control of quality from suppliers.”

Showing impressive examples of imaging and computation enabling doctors to reduce errors in breast cancer detection by 85 percent, and even to operate on a beating heart, using Nvidia GPUs and artificial intelligence, Nvidia’s director of Advanced Technology John Hu noted, “We are at a real inflection point for demand for more compute power, and we can’t get there by just process scaling any more. We are going to have to rely on new architectures to rescue us from the increasingly imperfect reality of materials and processes.”

While almost every speaker stressed the increasing need for the different segments of the supply chain from materials to design to work more closely together to move technology forward along many new paths, the materials suppliers in the audience felt that progress could be better to make this happen. Some audience members talked among themselves of now being invited more often into the fabs to discuss material development, but still not being told much detail about the key target parameters. Material suppliers in the audience raised the issues of the time and expense needed to qualify their second sources for raw materials and precursors, to get the needed environmental certifications, and to find access to the expensive exotic multi-technology metrology tools capable of finding contaminates too small to see with conventional methods, before they could even bring in any potential material to be evaluated for use several years in the future.

Although speakers kept referring to the past Golden Age of Moore’s Law of regular two-year dimensional scaling, before the proliferation of alternatives, Tim Hendry, retiring Intel VP, Fab Materials, pointed out that it hadn’t really seemed like a Golden Age at the time. “As I remember, we thought it was pretty hard back then too.”

  1. Look to self-aligned and selective processes as scaling boosters

As lithography scaling slows down, new approaches will make creative use of deposition and etch to keep improving pattern resolution. “14nm is a real sweet spot technically for lithography that will be with us for a long time,” noted Anton DeVilliers, Tokyo Electron America director of Patterning Technology, suggesting a toolkit of assorted self-alignment and selective deposition and etch processes likely to see increasing use as resolution boosters as an alternative to pushing the lithography, such as collars at key points to protect the pattern, or self aligned patterning by selective etching.

Adding a protective ALD collar holds a key region open during etch to widen the process window and prevent shorts from process variation in tight pattern areas.

SMC-Image3

ALD snap collar holds the critical part of M1 pattern open to widen window in LELELE process…

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So that overlay variation that would typically create a short…

SMC-Image5

Instead creates the desired pattern. Source: TEL

Using materials with different etch selectivity for different parts of a pattern, such as for alternate lines, enables the creation of a self aligned pattern at higher resolution than the lithography.  Different etch selectivity in alternate metal tracks could also reduce the number of exposure passes and improve overlay tolerance. “For 5nm nanowires, we’ll have to use selective ALD and ALE, controlled by self assembling monolayers,” noted DeVilliers. “We’ve done each of these steps on a tool, but now the challenge is to put them all together.”

  1. Progress on 3D alternatives

“To maintain the pace of progress we’ll have to change everything—we can’t do it with Moore’s Law,” said Bill Bottoms, chairman and CEO, Third Millennium Test Solutions, updating on the international effort to create a Heterogeneous Integration Roadmap. “Future progress will come from bringing active elements closer together through integration at the system level, with interconnect with photonics and plasmonics.” The aim is to map future needs to better enable precompetitive collaboration. The first edition of the roadmap is now slated to come out in March.

SMC-Image6

CEA-Leti researchers meanwhile are reporting good progress on lowering the temperatures of the various processes needed to build a second chip directly on top of a first, for monolithic 3D CMOS-on-CMOS integration.  Performance of the bottom chip degrades if the process temperatures for the top chip are >500°C, mainly because the NiPt silicide deteriorates, but replacing the NiPt with a more stable NiCo and adding an Si cap looks promising to increase stability. The 8nm active active layer for the top device is bonded atop the bottom device at room temperature and annealed 300C. Nanosecond laser thermal annealing and low temperature solid phase epitaxy regrowth help bring down temperatures for dopant activation. Cycles of deposition and etch replace selective epitaxy for the source and drain, while different precursors reduce process temperatures to 500-550C. “Later this year at IEDM we’ll demonstrate top CMOS made at 500°C with these developments,” said Philippe Rodriguez, CEA-Leti research engineer.

  1. Get used to the slow growth world 

The semiconductor industry will see silicon demand (MSI) pick up from this year’s 0.6 percent increase to  ~3.8 percent growth in 2017, and ~6.3 percent in 2018, as some uncertainty about interest rates and government policy in major countries resolves, according to the econometric semiconductor forecast from Hilltop Economics and LINX Consulting. “We got comfortable with 3 percent GDP growth in the world that we sell chips into, but since the 2009 recession we are only seeing about 2.4 percent growth,” said Duncan Meldrum, chief economist, Hilltop Economics. He noted that economists keep saying the world will get back to its regular 3 percent growth next quarter or year, but it hasn’t happened, probably because high government debt levels in most major economies tends to reduce growth by about reduces it. Silicon demand grows a little faster than GDP, but its trends generally track that global growth number more than in the past as the electronics industry matures.

  1. Wafer level fan out will shake up package materials sector

Now that it appears the 40 to 50 percent improvement in performance in the newest Apple A10 processor is largely from its wafer-level fan out packaging from TSMC, demand for the packaging approach is ramping fast. “This is one of the fastest ramps we’ve seem for a package in a long time,” said TechSearch International president Jan Vardaman. “It’s a very disruptive technology that will have a big impact on the industry.” The thinner, lower-cost packaging approach is also showing up in RF and audio codec chips in mobile phones, with  ~2 billion units just in Samsung and Apple phones, potentially bringing big changes to the packaging materials market. Laminate substrate suppliers will see demand plunge, copper post suppliers will see little change, and makers of wafer-level dielectrics could potentially see 3X growth in volume. “But don’t think you’ll see that in revenue, since customers will really beat the prices down.”

And in a final note, the gathered materials sector paused in a moment of silence for Dan Rose, who passed away on September 19.  Dan was a well-known market researcher and founder of Rose Associates with a focus on materials market data.

Originally published on the SEMI blog.

The bill of materials (BOM) for an iPhone 7 equipped with 32 gigabytes (GB) of NAND flash memory carries $219.80 in bill of materials costs, according to a preliminary estimate from IHS Markit (Nasdaq: INFO), a source in critical information, analytics and solutions.

After $5 in basic manufacturing costs are added, Apple’s total cost to manufacture the iPhone 7 rises to $224.80. The unsubsidized price for a 32GB iPhone 7 is $649. IHS Markit has not yet performed a teardown analysis on the larger iPhone 7 Plus. This preliminary estimated total is $36.89 higher than the final analysis of the iPhone 6S published by IHS in December 2015.

“Total BOM costs for the iPhone 7 are more in line with what we have seen in teardowns of recent flagship phones from Apple’s main competitor, Samsung, in that the costs are higher than in previous iPhone teardown analyses,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “All other things being equal, Apple still makes more margin from hardware than Samsung, but materials costs are higher than in the past.”

Same shape. No jack.

While the overall shape and physical design of the iPhone 7 is similar to the iPhone 6S that preceded it, the new display has wider color gamut, including DCI-P3 as well as traditional sRGB, which improves the rendering of photos and videos. The device’s haptic engine, which provides the “click” feel for users, has also been improved for longer-duty cycles and better dynamic response. The home button is now static and mimics the MacBook in terms of a solid-state button design.

Apple has also eliminated the 3.5 millimeter headphone jack, allowing a larger battery and haptic motor. “Where there was an audio jack in the previous design, Apple replaced it with a symmetrical grill — not for speakers, but for the waterproof microphone, leaving more room for the larger battery and Taptic Engine,” Rassweiler said.

Increased base-model storage

Apple has increased the iPhone 7’s storage density. For the first time, the base model starts at 32 gigabytes (GB) – which is only the second time Apple has upgraded the base storage in the iPhone. From a cost perspective, the shift from 16GB/64GB/128GB iPhones to 32GB/128GB/256GB is a big jump. “Despite significant cost erosion in NAND flash over the last year, this increase in the overall memory cost definitely puts pressure on the bill of materials costs — and therefore margins — from Apple’s perspective,” Rassweiler said.

Intel returns

The Intel design win, and six years of absence that Intel had from the iPhone, is important to note. Even so, Intel still shares the processor business with Qualcomm. “Whereas Apple strives to have ‘one iPhone model for all carriers and markets,’ there are a number of different hardware permutations supporting various countries and carriers,” Rassweiler said. “Apple will likely look for ways to simplify the design moving forward, which means one supplier – whether Intel or Qualcomm – will likely dominate, as part of supplier and SKU streamlining.”

According to Wayne Lam, principal analyst of smartphone electronics, IHS Markit, “Largely left behind in the 4G LTE market, Intel has finally worked itself back into the iPhone, which is a huge win, but not one that is going to be financially significant in the near term for Intel.”

RF paths

Apple has also eliminated segmented antenna bands, which means the company is pushing all radio-frequency (RF) paths to the very ends of the phone – both on the top and bottom. The aluminum uni-body construction and design forces all RF paths into those two locations. Whereas other smartphones use a glass back and RF components with antennas mounted on the ample back spaces, Apple is restricted to just two physical antennas.  “This design limitation may force Apple to go back to an all-glass design again so that they can fit in 4x4MIMO LTE antennas and more features like wireless charging in the next iPhone iteration,” Lam said.

Modem moved

The baseband thin modem has been moved next to the A10 processor. Prior to the iPhone 7, the thin modem was always on the other side of the SIM card receptacle. “This is a subtle change but likely shows us where Apple wants to take this,” Lam said, “eventually putting the thin modem right on the apps processor package or even integrating it into the A-series processor.”

Officially water resistant

iPhone 7 is now officially rated as water resistant. “We also saw evidence of this water proofing design evolution in the earlier iPhone 6S, which included additional gasketing around critical connectors, as well as the use of WiFi antenna at the end of the primary speaker box,”Lam said. “Doing so pushes the antennas near the only other opening, for better reception and transmission.”

Jet-black polished case

Jet black polish is a new option on 128GB and 256GB models. “This is a new feature that produces a whole new look for the iPhone,” Lam said. “It is a lower yielding, time-intensive manufacturing step that adds cost, as well as considerable value, pushing the retail price higher for those requesting this option.”

Antenna speaker design

The antenna speaker design on the iPhone 7 came from the WiFi antenna packed into the speakers of Apple’s MacBook.  “Apple likes to reuse these unique designs throughout their product lines,” Lam said. In a first for the iPhone series, the headset speaker now doubles as a stereo speaker.

Upgraded camera

While not as groundbreaking as the two optical paths in the iPhone 7 Plus, the iPhone 7 camera has now been upgraded to optical image stabilization (OIS), for better low light performance.

Improved battery life

The battery has been increased to 1960mAhr capacity from 1715mAh in the previous iPhone 6s.  This change is consistent with Apple’s claims of improved battery life.

Materials with large dielectric constants — aka “high-K materials” — have recently garnered attention for their potential use within future generations of reduced-dimension semiconductor devices.

Barium strontium titanate, one such material, possesses an inherently large dielectric constant that can be altered significantly by an applied electrical field — by as much as a factor of 10. While this property has been known to exist for more than half a century and many researchers have attempted to exploit it, the technology has been limited by the low quality of the material. By semiconductor industry standards, the material is considered to be defective.

But researchers at University of California, Santa Barbara, who began exploring thin-film tunable dielectrics using sputtered material nearly two decades ago, are now trying to leverage advanced and scalable materials deposition techniques like molecular beam epitaxy (MBE) to create tunable, high-frequency integrated circuits and devices with high-quality materials that are comparable to modern semiconductor technology.

As the group reports this week in Applied Physics Letters, from AIP Publishing, by using extremely high-quality epitaxial materials they were able to greatly reduce the dielectric loss in ferroelectric tunable radio-frequency (RF) capacitors. Advances at the fundamental level, such as this one, open the door to future RF materials and devices that can be electrically reconfigured or “tuned” to adapt to changing environments.

The catch is that the deposition of complex oxides, such as barium strontium titanate, is problematic because of the high temperatures and oxygen-rich environment involved.

“Our work was made possible by recent advances in a hybrid form of MBE at UCSB that uses metal organic precursors,” explained Susanne Stemmer, a professor at the Materials Research Laboratory at UCSB.

The material’s large dielectric constants “present fabrication challenges because the inherently high capacitance density of the films requires smaller electrode dimensions and finer lithography than many typical integrated capacitor structures,” said Robert York, a professor in the Electrical & Computer Engineering department at UCSB. “Low-loss reactive devices also pose significant measurement challenges at microwave frequencies. The close collaboration of materials scientists and electrical engineers, and years of experience in device processing, was integral to the success of our work.”

Significantly, the team’s work clarifies that early work within the field that reported disappointing performances of BST-based devices was limited primarily by deposition and processing methods — not by intrinsic limitations of the underlying material itself.

“Our work also demonstrates that with suitable modifications, MBE systems — a proven technology for large-scale manufacturing of compound semiconductor materials — can be used to deposit a wide variety of high-quality materials,” Stemmer noted.

Another key discovery for the team was “exposing the susceptibility of the material to contamination by other organic materials commonly used in photolithography processes, which required some changes in the fabrication process that, in retrospect, may have factored into the low quality factors reported in the past,” York pointed out.

In terms of applications, materials capable of being altered electronically show enormous potential for adaptive or reconfigurable electronic systems — particularly high-frequency communications.

“For example, tunable capacitors using barium strontium titanate can be used to create tunable antennas for cellular communications, which allows a small antenna to be tuned over a wide frequency range or enables a phone to adapt to different surroundings for improved efficiency and battery life,” York said.

Barium strontium titanate devices can also be used to create low-cost phase-shifter devices for phased-array antennas in mobile satellite communication systems.

“In fact, some barium strontium titanate devices are already used for commercial RF electronics and the infrastructure for deposition and fabrication already exists within most semiconductor foundries, so the timeline for exploiting this advance could be relatively short compared to the typical timeline for a materials advance,” York added.

While numerous research avenues exist for further exploring the materials involved, and improving the processing and device design, one immediate next step for the team is to “demonstrate high-performance integrated circuits with films deposited directly on metal electrodes,” Stemmer said. “Integration with other commercially viable substrate materials is also of interest.”

For decades, scientists have tried to harness the unique properties of carbon nanotubes to create high-performance electronics that are faster or consume less power — resulting in longer battery life, faster wireless communication and faster processing speeds for devices like smartphones and laptops.

But a number of challenges have impeded the development of high-performance transistors made of carbon nanotubes, tiny cylinders made of carbon just one atom thick. Consequently, their performance has lagged far behind semiconductors such as silicon and gallium arsenide used in computer chips and personal electronics.

Now, for the first time, University of Wisconsin-Madison materials engineers have created carbon nanotube transistors that outperform state-of-the-art silicon transistors.

The UW-Madison engineers use a solution process to deposit aligned arrays of carbon nanotubes onto 1 inch by 1 inch substrates. The researchers used their scalable and rapid deposition process to coat the entire surface of this substrate with aligned carbon nanotubes in less than 5 minutes. The team's breakthrough could pave the way for carbon nanotube transistors to replace silicon transistors, and is particularly promising for wireless communications technologies. Credit: Stephanie Precourt

The UW-Madison engineers use a solution process to deposit aligned arrays of carbon nanotubes onto 1 inch by 1 inch substrates. The researchers used their scalable and rapid deposition process to coat the entire surface of this substrate with aligned carbon nanotubes in less than 5 minutes. The team’s breakthrough could pave the way for carbon nanotube transistors to replace silicon transistors, and is particularly promising for wireless communications technologies. Credit: Stephanie Precourt

Led by Michael Arnold and Padma Gopalan, UW-Madison professors of materials science and engineering, the team’s carbon nanotube transistors achieved current that’s 1.9 times higher than silicon transistors. The researchers reported their advance in a paper published Friday (Sept. 2) in the journal Science Advances.

“This achievement has been a dream of nanotechnology for the last 20 years,” says Arnold. “Making carbon nanotube transistors that are better than silicon transistors is a big milestone. This breakthrough in carbon nanotube transistor performance is a critical advance toward exploiting carbon nanotubes in logic, high-speed communications, and other semiconductor electronics technologies.”

This advance could pave the way for carbon nanotube transistors to replace silicon transistors and continue delivering the performance gains the computer industry relies on and that consumers demand. The new transistors are particularly promising for wireless communications technologies that require a lot of current flowing across a relatively small area.

As some of the best electrical conductors ever discovered, carbon nanotubes have long been recognized as a promising material for next-generation transistors.

Carbon nanotube transistors should be able to perform five times faster or use five times less energy than silicon transistors, according to extrapolations from single nanotube measurements. The nanotube’s ultra-small dimension makes it possible to rapidly change a current signal traveling across it, which could lead to substantial gains in the bandwidth of wireless communications devices.

But researchers have struggled to isolate purely carbon nanotubes, which are crucial, because metallic nanotube impurities act like copper wires and disrupt their semiconducting properties — like a short in an electronic device.

The UW-Madison team used polymers to selectively sort out the semiconducting nanotubes, achieving a solution of ultra-high-purity semiconducting carbon nanotubes.

“We’ve identified specific conditions in which you can get rid of nearly all metallic nanotubes, where we have less than 0.01 percent metallic nanotubes,” says Arnold.

Placement and alignment of the nanotubes is also difficult to control.

To make a good transistor, the nanotubes need to be aligned in just the right order, with just the right spacing, when assembled on a wafer. In 2014, the UW-Madison researchers overcame that challenge when they announced a technique, called “floating evaporative self-assembly,” that gives them this control.

The nanotubes must make good electrical contacts with the metal electrodes of the transistor. Because the polymer the UW-Madison researchers use to isolate the semiconducting nanotubes also acts like an insulating layer between the nanotubes and the electrodes, the team “baked” the nanotube arrays in a vacuum oven to remove the insulating layer. The result: excellent electrical contacts to the nanotubes.

The researchers also developed a treatment that removes residues from the nanotubes after they’re processed in solution.

“In our research, we’ve shown that we can simultaneously overcome all of these challenges of working with nanotubes, and that has allowed us to create these groundbreaking carbon nanotube transistors that surpass silicon and gallium arsenide transistors,” says Arnold.

The researchers benchmarked their carbon nanotube transistor against a silicon transistor of the same size, geometry and leakage current in order to make an apples-to-apples comparison.

They are continuing to work on adapting their device to match the geometry used in silicon transistors, which get smaller with each new generation. Work is also underway to develop high-performance radio frequency amplifiers that may be able to boost a cellphone signal. While the researchers have already scaled their alignment and deposition process to 1 inch by 1 inch wafers, they’re working on scaling the process up for commercial production.

Arnold says it’s exciting to finally reach the point where researchers can exploit the nanotubes to attain performance gains in actual technologies.

“There has been a lot of hype about carbon nanotubes that hasn’t been realized, and that has kind of soured many people’s outlook,” he says. “But we think the hype is deserved. It has just taken decades of work for the materials science to catch up and allow us to effectively harness these materials.”

The researchers have patented their technology through the Wisconsin Alumni Research Foundation.

Problems frequently arise as a result of an incomplete or absent formal risk assessment when processes are modified or new materials introduced.

BY ALAN IFOULD and ANDREW CHAMBERS, Edwards, North Somerset, UK

The sub-fab is home to the many pumps and abatement systems that not only help to create the pristine environments required in the process chambers of the numerous tools in the cleanroom, but also handle the exhaust gases and by-products generated by the manufacturing process. In this respect, the efficiency and efficacy of sub-fab operations directly affect the availability, productivity, total operating cost and yield of the manufacturing fab above. Perhaps more importantly, in addition to supporting the process vacuum, equipment in the sub-fab is designed to render cleanroom process wastes harmless and ready for safe disposal or, if appropriate, release into the environment. As such, they are vital to protecting the safety of the people working in the fab as well as those living and working in the surrounding community, and ultimately, all of us who share that environment. The very nature of the process materials and reaction byproducts handled in the sub fab, which may be variously corrosive, toxic, pyrophoric, flammable or environmentally damaging, creates significant risks, especially for those who must operate and maintain the equipment located there. Moreover, as device manufacturing becomes more complex, with the introduction of new materials, new precursors and new processes, the risk of mistakes with potentially catastrophic consequences in both human and financial terms will only increase.

While ultimate responsibility for personnel safety in the sub-fab lies with the fab operator, equipment manufac- turers have a part to play by optimizing their products not only for efficient, effective and reliable operation, but also by ensuring any risks associated with operation, maintenance and repair are assessed and minimised to the greatest extent possible.

There is often a strong focus on technical performance and cost attributes when selecting sub-fab equipment. However, processes and procedures to ensure optimum operation and continuous mitigation of risks to service personnel are equally critical; these demand the devel- opment of clear and effective operating procedures and guidelines – in industry jargon “best known methods” or BKMs – to ensure the equipment achieves its full performance potential and safety integrity maintained. The manufacturers of sub-fab equipment are perhaps in the best position to define these guidelines since they will typically have acquired an understanding of the risks posed by hazardous materials on a case-by-case basis during the course of system optimization. Frequent development of BKMs is undertaken in collaboration with the process tool manufacturer or early adopters of the process. However, defining operating and maintenance methods and procedures that are truly the best known requires a commitment to doing so at the highest levels of corporate management, and a formal process of reporting, analysis, synthesis and dissemination throughout the equipment support community.

A key component of any BKM program is the active participation of the equipment manufacturer’s service personnel who are responsible for installing, commissioning and maintaining the equipment and are also likely to have first- hand knowledge and experience of the potential hazards. Since service personnel are invariably in the front-line when safety incidents occur, they are well motivated to contribute since they themselves are often at greatest risk, and it is essential that their contribution is incorporated into product development programs to complement the technical performance with assured safety and reliability.

Even a cursory search of the internet will quickly reveal numerous examples of fab and sub-fab incidents. Amongst the lessons that can be taken from these events is that the risk management process and the resulting controls have to cover every foreseeable circumstance across the equipment lifecycle: installation, commissioning, operation, servicing and maintenance. Notable recent serious accidents include:

– March 2014 – A fab worker dies after a carbon dioxide leak

– January 2013 – One worker dies and four others are hospitalized after a hydrofluoric acid leak at a manufacturing facility

– September 2013 – A fire at major memory fab results in the closure of the facility with losses estimated in the range of $1 billion and a measurable impact on global DRAM pricing

– August 2012 – A security guard and 3 firefighters are hospitalized when a fire occurs in the exhaust ducts of a photovoltaic manufacturing laboratory in Singapore. The entire facility is shut down for weeks and 35 workers are laid off

These were events with consequences visible and far-reaching enough to make the national and international news. However, experience indicates that smaller events, often with narrowly-averted disastrous consequences, occur on a much more frequent basis with adverse impacts on fab productivity. These events are typically not widely broadcast, thereby limiting the community learning that might otherwise take place.

In respect of process exhausts, three types of hazard recur repeatedly as manufacturing processes evolve and new process materials are introduced: condensation of reactive chemical precursors or reaction products, corrosion due to condensation of acidic materials, and pipe blockage due to accumulation of condensate in significant volume. The images in FIGURES 1-3 show a few examples.

FIGURE 1. (left) Condensed explosive polysiloxane material in an epitaxial deposition system process foreline, (middle and right) CVD exhaust pipe destroyed by explosion of condensed process by-product.

FIGURE 1. (left) Condensed explosive polysiloxane material in an epitaxial deposition system process foreline, (middle and right) CVD exhaust pipe destroyed by explosion of condensed process by-product.

FIGURE 2. (left) Acidic TEOS-based polymer with a pH of approximately 1, (middle) Condensed corrosive Br2-based liquid, (right) Exhaust pipe damaged by exposure to condensed acidic material.

FIGURE 2. (left) Acidic TEOS-based polymer with a pH of approximately 1, (middle) Condensed corrosive Br2-based liquid, (right) Exhaust pipe damaged by exposure to condensed acidic material.

FIGURE 3. Exhaust blockage caused by various materials (left) AlCl3 from a metal etch process, (middle) NH4Cl from an LPCVD process, (right) Unknown material deposited in the exhaust of a metal carbide CVD process.

FIGURE 3. Exhaust blockage caused by various materials (left) AlCl3 from a metal etch process, (middle) NH4Cl from an LPCVD process, (right) Unknown material deposited in the exhaust of a metal carbide CVD process.

In many cases, the cause of the risk is understood and solutions exist, but problems frequently arise as a result of an incomplete or absent formal risk assessment when processes are modified or new materials introduced. For example, condensation of potentially dangerous or explosive materials can usually be prevented by carefully controlling the temperature of the exhaust gas through the pipework and pumps. Pipe heating systems are widely available for forelines and exhaust pipes, and pumps can be designed with internal thermal management, but if the risk is not properly assessed, the appropriate controls will not be put in place. Furthermore, while a risk analysis may conclude that exhaust pipe heating is required in a specific case, it should also recognize that key to its effective implementation is the avoidance of cool spots, particularly at bends and junctions. Even a small local drop in temperature can create a hazardous situation despite the application of what is widely perceived as an effective protective measure – a subtle effect, but one with which field service personnel have become familiar through hard-won experience. At a practical level, if each process exhaust is designed in isolation, such considerations make their design and implementation a time-consuming and labor-intensive process. However, as noted in a previous publication [1] the ability to maintain effective thermal control throughout the exhaust stream can be enhanced by integrating the vacuum pumping and point- of-use abatement functions together with the interconnecting exhaust pipes into a single unified system. In this way the pipe routing can be standardized to permit optimization of the exhaust pipe heating installation for each specific process and to avoid the need for customization in the field. Integration and standardization also permits careful optimization of pump capacities and pipe diameters and routing to minimize power consumption and maximize destruction or removal efficiency (DRE). Finally, whether consid- ering an integrated system or not, secondary enclosures for pumps, abatement and exhaust pipes provide an additional layer of protection by permitting hazardous materials to be routed away from personnel in the event of an unintended release.

In some cases, it is not possible to prevent the accumu- lation of hazardous materials. It then becomes essential to monitor the deposition and remove it through periodic maintenance procedures. For example, blockage can be monitored by measuring the pressure drop over the length of the exhaust pipe – as material accumulates in the pipe the pressure drop increases. By monitoring for blockage, operators can ensure that the system is cleaned before its performance impacts production and at the same time avoid cleaning more frequently than required. Integrated vacuum and abatement systems often combine monitoring capabilities with automated software to alert operators of the need for maintenance.

While problems associated with accumulation of materials in process exhausts is arguably the most frequently encountered hazard faced by sub-fab maintenance personnel, another widely applied risk mitigation strategy, particularly for flammable process materials, is dilution below their lower flammability limit (LFL) with an inert gas such as nitrogen. However, it is important to understand the nature of the chemical processes occurring in the deposition chamber and to base the dilution calculation on the composition and volume of the effluent gas rather than the precursor. For example, TEOS is a precursor gas widely used in the chemical vapor deposition of silicon oxide films. The lower temperature needed for the CVD process and the absence of aggressive reaction products are the main advan- tages of using TEOS compared with traditional precursors such as silane and the mechanical and electrical properties of Si02 films deposited from TEOS are also very good. The decomposition products of TEOS in the gas phase in the absence of oxygen include organic fragments (ethanol, ethanal, ethene, methane, carbon monoxide), and in the presence of oxygen include water vapour, carbon dioxide, ethanal and methanol [2], many of which are flammable. A dilution calculation based on the amount of TEOS entering the chamber rather than the volume of decompo- sition products exiting the chamber could easily lead to an underestimate of the required volume of diluent and the presence of a flammable mixture in the exhaust pipe in some circumstances. Once again, a rigorous risk assessment is required to identify such potential hazards and put corrective measures in place where needed.

Risk assessment and communication

It should be clear from the preceding discussion that a detailed technical understanding of semiconductor manufacturing processes and materials and their impact on sub-fab equipment is a prerequisite for safe and efficient pumping and abatement of process exhaust. In particular, ensuring the safety of sub fab operations requires a formal process for risk assessment. Once determined, safe operating proce- dures must be codified and effectively communicated to field personnel, and a mechanism must exist to update procedures based on feed-back from the field. FIGURE 4 is taken from the Risk Assessment Procedure [3] used at Edwards (adapted from Semi S10) and illustrates the Risk Rating Table, a matrix by which risks are evaluated and appropriate responses determined.

Once risks are assessed the information must be effec- tively communicated to users and field service personnel. To ensure appropriate dissemination of required information, Edwards publishes Application Notes for equipment users and Safety Application Procedures (SAP) for service engineers.

Conclusion

The hazardous nature of many of the materials present in the semiconductor manufacturing process creates significant safety risks for fab personnel and others living or working near the fab, and financial risks for manufacturers and investors. Managing those risks takes more than good intentions and common sense precautions. It requires a detailed and continuously updated technical understanding of the processes and materials based on broad experience across many different types of applications, and ideally, partnership with process tool manufacturers during development and optimization of new processes. As in other high risk industries – nuclear, aviation, automotive, healthcare, oil, rail and military – best practice safety and risk management is heavily influ- enced by equipment manufacturers, who are in the best position to understand the capabil-
ities of their products across a wide range of applications.

Ultimately the fab management team own the responsibility for managing risk and safety with the highest levels of corporate respon- sibility. Semiconductor equipment manufacturers, and in particular, manufacturers of pumping and abatement systems that handle and safely dispose of hazardous materials, have an invaluable supporting role to play with their continuous accumulation of know-how and formal processes for risk assessment, including a mechanism for distributing safety information to, and incorporating feedback from, the field.

References

1. Andrew Chambers, Managing hazardous process exhausts in high volume manufacturing, Solid State Technology, 2016 Issue 2
2. Van der Vis, M.G.M., et al, The thermodynamic properties of tetrae- thoxysilane (TEOS) and an infrared study of its thermal decomposition, Colloque C3, supplement au Journal de Physique 11, Volume 3, aofit 1993, http://dx.doi.org/10.1051/jp4:1993309
3. Adapted from Semiconductor Equipment and Materials International (SEMI) standard S-10, http://www. semi.org

Recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are making it possible to extend W use to next-generation devices.

BY JONATHAN BAKKE, Applied Materials, Santa Clara, CA

Tungsten (W), with its low resistivity and minimal electro-migration, has long been used for a variety of applications in fabricating semiconductor devices. For instance, it is used for logic contact, local interconnect (LIC), and metal gate (MG) fill as well as DRAM buried word line and contact and 3D NAND MG and contact. Sustained scaling, however, is posing challenges to its continued use with conventional process flows. Interconnect dimensions have shrunk to the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance; fill integrity degrades as aspect ratios and the degree of re-entrance increase, making it difficult to ensure high-quality metallization.

At earlier nodes, larger dimensions made W fill possible using conformal CVD deposition. Now, overhang around the tops of ultra-small openings or bowing from the interconnect etch open preclude the conformal process from completely filling features without voids, while center seams are an inevitable result of conformal deposition, even in the absence of voids. These attributes render extremely small features vulnerable to breach during CMP, causing high resistance or complete failure of an inter- connect. High feature densities and lack of via redundancy in advanced chip designs mean that a single void can cause complete device failure and significant yield loss.

Fortunately, recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are overcoming these limitations and making it possible to extend W use to next-generation devices. The former lower resistance by simplifying fill film requirements and enlarging the volume available for W fill; the latter eliminates undesirable seams to create more robust structures.

Low-resistance liners

To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10 nm node and beyond, the maximum critical dimension (CD) of the LIC willbe

Metal-organic deposition of thin W-based films offers an ideal solution, because it can eliminate high-resistance liners and nucle- ation layers while maintaining adhesion and fluorine-barrier properties equiv- alent to those of the current process flow. A new W liner has been developed that lowers line resistance for further device scaling: plasma-enhanced (PE) CVD W that nucleates on metal and oxides.

The PECVD W film is produced using a specialized chemical in the presence of reactive plasma that breaks down the ligands. The film composition is primarily W, and the atoms from the decomposed ligands are bonded to the W. The amorphous character of the film and the dopants in it from the ligand lead to good adhesion to dielec- trics and fluorine barrier properties in the 20-30Å range.

FIGURE 1 shows a simulation of a contact plug in the 4-30nm range. The model contains parallel and series resistors for the plug and through resistance. Features are assumed to be straight wall trenches. Resistance of 12 μΩ*cm is used for W at all thicknesses, which under-estimates the benefit of PECVD W. Scattering at film interfaces is not taken into account. The inflections in the curves (from right to left) occur when a film is removed due to volume constraints. It is clear that the benefit of PECVD W increases exponentially as CDs decrease, especially without the nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

SiO2 trench structures with CDs ranging from 10nm to 150nm and a depth of 100nm were used to investigate W line resistance and evaluate gap-fill performance. As shown in FIGURE 2, line resistance in a ~10 nm CD dropped by nearly 90% compared with the conventional stack.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

Seam-suppressed gap fill

Until now, feature dimensions have made W fill integration possible using nucleation followed by conformal CVD deposition – which always leaves a seam in features. At CDs

A new approach employs a unique, “selective” suppression mechanism that results in a bottom-up fill free of seams or voids. Pre-treating the nucleation layer creates preferred W growth from the bottom of the structure upwards and less on the field, minimizing the likelihood of void-creating pinch-off and seams (FIGURE 3). Experiments showed the process to be successful on structures with CDs ranging from 10nm to 150nm.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

Electrical tests confirmed that SSW lowered line resistance compared to that of conventional CVD W (FIGURE 4). Post-CMP defect analysis by top-down view SEM revealed a narrow seam in conventional CVD W after W CMP (FIGURE 5a), while none is visible after SSW fill (FIGURE 5b).

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

Tungsten 5-1

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

Conclusion

For the next several nodes of logic and memory fabrication, W will remain an important material in interconnect and gate metallization. However, as scaling continues, transi- tions in process flows will be necessary to achieve low contact and line resistance while maintaining gap-fill integrity. A new W-based barrier/liner has been produced through precision materials engineering that improves device performance and integration while simplifying process flows. Similarly, a new SSW gap-fill process increases the volume of W (potentially lowering resistance), creates more robust features for post-fill integration, and relaxes requirements on CMP and dielectric etch steps, thus delivering performance, device design, and yield benefits.

For further detail on the processes presented in this article, see Bakke, J., et al., “Fluorine-Free Tungsten Films as Low Resistance liners for Tungsten Fill Applications” and Kai,W.,etal.,“ImprovingTungstenGap-FillforAdvance Contact Metallization,” presented at the 2016 IEEE Inter- national Interconnect Technology Conference.