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Soft materials are great at damping energy — that’s why rubber tires are so good at absorbing the shock of bumps and potholes. But if researchers are going to build autonomous soft systems, like soft robots, they’ll need a way to transmit energy through soft materials.

Now, researchers at the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS), in collaboration with colleagues at the California Institute of Technology, have developed a way to send mechanical signals through soft materials.

The research is described in the Proceedings of the National Academy of Sciences.

“Soft autonomous systems have received a lot of attention because, just like the human body or other biological systems, they can be adaptive and perform delicate movements. However, the highly dissipative nature of soft materials limits or altogether prevents certain functions,” said Jordan Raney, postdoctoral fellow at SEAS and first author of the paper. “By storing energy in the architecture itself we can make up for the energy losses due to dissipation, allowing the propagation of mechanical signals across long distances.”

The system uses the centuries-old concept of bistable beams — structures stable in two distinct state — to store and release elastic energy along the path of a wave. The system consists of a chain of bistable elastomeric beams connected by elastomeric linear springs. When those beams are deformed, they snap and store energy in the form of elastic deformation. As the signal moves down the elastomer, it snaps the beams back into place, releasing the stored energy and sending the signal downstream like a line of dominos. The bistable system prevents the signal from dissipating downstream.

“This design solves two fundamental problems in transmitting information through materials,” said Katia Bertoldi, the John L. Loeb Associate Professor of the Natural Sciences at SEAS and senior author of the paper.  “It not only overcomes dissipation, but it also eliminates dispersive effects, so that the signal propagates without distortion.  As such, we maintain signal strength and clarity from start to end.”

The beam geometry requires precise fabrication techniques. If the angle or thickness of one beam is off by one degree or millimeter, the whole system fails.

The team used advanced 3D printing techniques to fabricate the system.

“We’re developing new materials and printing methods that enable the fabrication of soft materials with programmable bistable elements,” said Jennifer A. Lewis, the Hansjorg Wyss Professor of Biologically Inspired Engineering and coauthor of the paper.

The team designed and printed a soft logic gate using this system. The gate, which looks like a tuning fork, can be controlled to act as either as an AND or as an OR gate.

“It’s amazing what you can do using simple beams — a building block that’s been around hundreds of years,” said Bertoldi. “You can do new stuff with a very old, well studied and very simple component.”

This research was supported by the National Science Foundation and the Harvard University Materials Research Science and Engineering Center (MRSEC).

To continue advancing, next-generation electronic devices must fully exploit the nanoscale, where materials span just billionths of a meter. But balancing complexity, precision, and manufacturing scalability on such fantastically small scales is inevitably difficult. Fortunately, some nanomaterials can be coaxed into snapping themselves into desired formations-a process called self-assembly.

Scientists at the U.S. Department of Energy’s (DOE) Brookhaven National Laboratory have just developed a way to direct the self-assembly of multiple molecular patterns within a single material, producing new nanoscale architectures. The results were published in the journal Nature Communications.

“This is a significant conceptual leap in self-assembly,” said Brookhaven Lab physicist Aaron Stein, lead author on the study. “In the past, we were limited to a single emergent pattern, but this technique breaks that barrier with relative ease. This is significant for basic research, certainly, but it could also change the way we design and manufacture electronics.”

Microchips, for example, use meticulously patterned templates to produce the nanoscale structures that process and store information. Through self-assembly, however, these structures can spontaneously form without that exhaustive preliminary patterning. And now, self-assembly can generate multiple distinct patterns-greatly increasing the complexity of nanostructures that can be formed in a single step.

“This technique fits quite easily into existing microchip fabrication workflows,” said study coauthor Kevin Yager, also a Brookhaven physicist. “It’s exciting to make a fundamental discovery that could one day find its way into our computers.”

The experimental work was conducted entirely at Brookhaven Lab’s Center for Functional Nanomaterials (CFN), a DOE Office of Science User Facility, leveraging in-house expertise and instrumentation.

Cooking up organized complexity

The collaboration used block copolymers-chains of two distinct molecules linked together-because of their intrinsic ability to self-assemble.

“As powerful as self-assembly is, we suspected that guiding the process would enhance it to create truly ‘responsive’ self-assembly,” said study coauthor Greg Doerk of Brookhaven. “That’s exactly where we pushed it.”

To guide self-assembly, scientists create precise but simple substrate templates. Using a method called electron beam lithography-Stein’s specialty-they etch patterns thousands of times thinner than a human hair on the template surface. They then add a solution containing a set of block copolymers onto the template, spin the substrate to create a thin coating, and “bake” it all in an oven to kick the molecules into formation. Thermal energy drives interaction between the block copolymers and the template, setting the final configuration-in this instance, parallel lines or dots in a grid.

“In conventional self-assembly, the final nanostructures follow the template’s guiding lines, but are of a single pattern type,” Stein said. “But that all just changed.”

Lines and dots, living together

The collaboration had previously discovered that mixing together different block copolymers allowed multiple, co-existing line and dot nanostructures to form.

“We had discovered an exciting phenomenon, but couldn’t select which morphology would emerge,” Yager said. But then the team found that tweaking the substrate changed the structures that emerged. By simply adjusting the spacing and thickness of the lithographic line patterns-easy to fabricate using modern tools-the self-assembling blocks can be locally converted into ultra-thin lines, or high-density arrays of nano-dots.

“We realized that combining our self-assembling materials with nanofabricated guides gave us that elusive control. And, of course, these new geometries are achieved on an incredibly small scale,” said Yager.

“In essence,” said Stein, “we’ve created ‘smart’ templates for nanomaterial self-assembly. How far we can push the technique remains to be seen, but it opens some very promising pathways.”

Gwen Wright, another CFN coauthor, added, “Many nano-fabrication labs should be able to do this tomorrow with their in-house tools-the trick was discovering it was even possible.”

The scientists plan to increase the sophistication of the process, using more complex materials in order to move toward more device-like architectures.

“The ongoing and open collaboration within the CFN made this possible,” said Charles Black, director of the CFN. “We had experts in self-assembly, electron beam lithography, and even electron microscopy to characterize the materials, all under one roof, all pushing the limits of nanoscience.”

Engineers from the University of Utah and the University of Minnesota have discovered that interfacing two particular oxide-based materials makes them highly conductive, a boon for future electronics that could result in much more power-efficient laptops, electric cars and home appliances that also don’t need cumbersome power supplies.

Their findings were published this month in the scientific journal, APL Materials, from the American Institute of Physics.

The team led by University of Utah electrical and computer engineering assistant professor Berardi Sensale-Rodriguez and University of Minnesota chemical engineering and materials science assistant professor Bharat Jalan revealed that when two oxide compounds — strontium titanate (STO) and neodymium titanate (NTO) — interact with each other, the bonds between the atoms are arranged in a way that produces many free electrons, the particles that can carry electrical current. STO and NTO are by themselves known as insulators — materials like glass — that are not conductive at all.

But when they interface, the amount of electrons produced is a hundred times larger than what is possible in semiconductors. “It is also about five times more conductive than silicon [the material most used in electronics],” Sensale-Rodriguez says.

This innovation could greatly improve power transistors — devices in electronics that regulate the electrical current –by making power supplies much more efficient for items ranging from televisions and refrigerators to handheld devices, Sensale-Rodriguez says. Today, electronics manufacturers use a material called gallium nitride for transistors in power supplies and other electronics that carry large electrical currents. But that material has been explored and optimized for many years and likely cannot be made more efficient. In this discovery made by the Utah and Minnesota team, the interface between STO and NTO can be at the very least as conductive as gallium nitride and likely will be much more in the future.

“When I look at the future, I see that we can perhaps improve conductivity by an order of magnitude through optimizing of the materials growth,” Jalan says. “We are bringing the possibility of high power, low energy oxide electronics closer to reality.”

Power transistors that use this combination of materials could lead to smaller devices and appliances because their power supplies would be more energy efficient. Laptop computers, for example, could ditch the bulky external power supplies — the big black boxes attached to the power cords — in favor of smaller supplies that are instead built inside the computer. Large appliances that consume a lot of electricity such as air conditioners could be more power efficient. And because there is less power wasted (wasted electricity usually dissipates into heat), these devices will not run as hot as before, says Sensale-Rodriguez. He also believes that if more electronics use these materials for transistors, collectively it could save significant amounts of electricity for the country.

“It’s fundamentally a different road toward power electronics, and the results are very exciting” he says. “But we still need to do more research.”

Researchers from North Carolina State University and the U.S. Army Research Office have developed a way to integrate novel functional materials onto a computer chip, allowing the creation of new smart devices and systems.

The novel functional materials are oxides, including several types of materials that, until now, could not be integrated onto silicon chips: multiferroic materials, which have both ferroelectric and ferromagnetic properties; topological insulators, which act as insulators in bulk but have conductive properties on their surface; and novel ferroelectric materials. These materials are thought to hold promise for applications including sensors, non-volatile computer memory and microelectromechanical systems, which are better known as MEMS.

“These novel oxides are normally grown on materials that are not compatible with computing devices,” says Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State and co-author of a paper describing the work. “We are now able to integrate these materials onto a silicon chip, allowing us to incorporate their functions into electronic devices.”

The approach developed by the researchers allows them to integrate the materials onto two platforms, both of which are compatible with silicon: a titanium nitride platform, for use with nitride-based electronics; and yttria-stabilized zirconia, for use with oxide-based electronics.

Specifically, the researchers developed a suite of thin films that serve as a buffer, connecting the silicon chip to the relevant novel materials. The exact combination of thin films varies, depending on which novel materials are being used.

For example, if using multiferroic materials, researchers use a combination of four different thin films: titanium nitride, magnesium oxide, strontium oxide and lanthanum strontium manganese oxide. But for topological insulators, they would use a combination of only two thin films: magnesium oxide and titanium nitride.

These thin film buffers align with the planes of the crystalline structure in the novel oxide materials, as well as with the planes of the underlying substrate – effectively serving as a communicating layer between the materials.

This approach, called thin film epitaxy, is based on the concept of domain-matching epitaxy, and was first proposed by Narayan in a 2003 paper.

“Integrating these novel materials onto silicon chips makes many things possible,” Narayan says. “For example, this allows us to sense or collect data; to manipulate that data; and to calculate a response – all on one compact chip. This makes for faster, more efficient, lighter devices.”

Another possible application, Narayan says, is the creation of LEDs on silicon chips, to make “smart lights.” Currently, LEDs are made using sapphire substrates, which aren’t directly compatible with computing devices.

“We’ve already patented this integration technology, and are currently looking for industry partners to license it,” Narayan says.

Just as many of us might be resigned to clogged salt shakers or rush-hour traffic, those working to exploit the special properties of carbon nanotubes have typically shrugged their shoulders when these tiniest of cylinders fill with water during processing. But for nanotube practitioners who have reached their Popeye threshold and “can’t stands no more,” the National Institute of Standards and Technology (NIST) has devised a cheap, quick and effective strategy that reliably enhances the quality and consistency of the materials–important for using them effectively in applications such as new computing technologies.

To prevent filling of the cores of single-wall carbon nanotubes with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes. In quantity and quality, the results are superior to water-filled nanotubes, especially for optical applications such as sensors and photodetectors.

To prevent cores of single-wall carbon nanotubes from filling with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes, especially important for optical applications. Credit: Fagan/NIST

To prevent cores of single-wall carbon nanotubes from filling with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes, especially important for optical applications. Credit: Fagan/NIST

The approach opens a straightforward route for engineering the properties of single-wall carbon nanotubes–rolled up sheets of carbon atoms arranged like chicken wire or honey combs–with improved or new properties.

“This approach is so easy, inexpensive and broadly useful that I can’t think of a reason not to use it,” said NIST chemical engineer Jeffrey Fagan.

In their proof-of-concept experiments, the NIST team inserted more than 20 different compounds into an assortment of single-wall carbon nanotubes with an interior diameter that ranged from more than 2 down to about 0.5 nanometers. Led by visiting researcher Jochen Campo, the scientists tested their strategy by using hydrocarbons called alkanes as fillers.

The alkanes, which include such familiar compounds as propane and butane, served to render the nanotube interiors unreactive. In other words, the alkane-filled nanotubes behaved almost as if they were empty–precisely the goal of Campo, Fagan and colleagues.

Compared with nanotubes filled with water and possibly ions, acids and other unwanted chemicals encountered during processing, empty nanotubes possess far superior properties. For example, when stimulated by light, empty carbon nanotubes fluoresce far brighter and with sharper signals.

Yet, “spontaneous ingestion” of water or other solvents by the nanotubes during processing is an “endemic but often neglected phenomenon with strong implications for the development of nanotube applications,” the NIST team wrote in a recent article in Nanoscale Horizons.

Perhaps because of the additional cost and effort required to filter out and gather nanotubes, researchers tend to tolerate mixed batches of unfilled (empty) and mostly filled single-wall carbon nanotubes. Separating unfilled nanotubes from these mixtures requires expensive ultracentrifuge equipment and, even then, the yield is only about 10 percent, Campo estimates.

“If your goal is to use nanotubes for electronic circuits, for example, or for fluorescent anti-cancer image contrast agents, then you require much greater quantities of materials of consistent composition and quality,” Campo explained, who was exploring these applications while doing postdoctoral research at the University of Antwerp. “This particular need inspired development of the new prefilling method by asking the question, can we put some passive chemical into the nanotube instead to keep the water out.”

From the very first simple experiments, the answer was yes. And the benefits can be significant. In fluorescence experiments, alkane-filled nanotubes emitted signals two to three times stronger than those emitted by water-filled nanotubes. Performance approached that of empty nanotubes–the gold standard for these comparisons.

As important, the NIST-developed prefilling strategy is controllable, versatile and easily incorporated into existing methods for processing single-wall carbon nanotubes, according to the researchers.

The 2015 market for semiconductor silicon wafers fell 5.3% to $7.2B on a record 10.4 BSI Si shipped, according to a new report, “Silicon Wafers Market & Supply Chain 2016, a TECHCET Critical Materials Report.” The silicon demand outlook for 2016 is expected to increase 6.8% to 11.1 BSI, largely due to the strength of the memory market. Issues with wafer supply will likely continue, as demand for 300mm polished wafers increases beyond capacity. Certain 200mm wafers are also in a tight supply situation given strong demand growth from the discrete device fabs coupled with limited supplier capacity, as explained in TECHCET’s report. Declining ASPs are expected as competition for China’s 200mm wafer demand increases and the 300mm market continues its evolution toward polished wafer usage.

Although shipments of silicon by area recovered after 2009, prices have still not recov- ered to 2008 (pre-US housing / WW credit crisis) levels. TECHCET expects aggregate Si ASPs to fall slightly in 2016 before firming or modestly increasing in 2017.

SOI wafer price increases, which started in 2014 due to a temporary supply-demand im- balance, have stabilized as new capacity has come online. Some pricing pressure is anticipated in 2016 as new players vie for market share.

The timeline for 450mm wafer piloting has been pushed out to 2019 with a ramp in 2020. While Intel remains bullish, TSMC, Samsung and Global Foundries have not yet joined the 450mm investment track. As a result, only Shin Etsu Handotai (S.E.H.) and SUMCO have invested in 450mm wafer development to date.

The top 5 silicon wafer producers account for roughly 97% of 300mm polished and epi- taxial wafers sales (by revenue). S.E.H. and SUMCO together account for over 55% of that 300mm revenue and more than 60% of the top 5’s total sales. China has no appreciable market share in the wafer market however, although acquisitions could change this in the future.

For more information on the wafer market, including details on the SOI market, please see TECHCET’s Critical Materials Report on Wafers, at https://techcet.com/product/silicon-wafers/.

The 2015 market for electronic gases totaled $3.65B, up 4.3% over the prior year, according to a new report from Techcet Group, “Critical Materials Report: Electronic Gases 2016.” The 2016 outlook is for 6.8% growth overall, with the electronic specialty gases segment leading the way with 8.9% growth to $2.53B and bulk gases increasing 4.3% to $1.37B. Single digit growth is expected to continue to be the norm, with looming shortages in neon and helium threatening to retard the pace.

In bulk gases, Air Liquide increased its share by 3% and now dominates the market at 31% share. In specialty gases, market shares underwent major shifts, including former leader Air Products slipping in position behind Air Liquide. Air Liquide has taken the lead position at 27%, with Air Products dropping to 17% after repositioning themselves as an independent entity, now recognized as Versum. Praxair, Linde and TNSC-Matheson, followed by SK Materials (formerly OCI) continue to round out the other global share leaders.

Concerns about the availability of Neon continue to plague the industry. Over 70% of the global supply of neon is sourced from Iceblick in Odessa, Ukraine, where the political unrest has resulted in a 60% reduction in output in 2015. New capacity is being installed in Texas, Indiana, Ukraine, China and Dubai, but takes two years to come online. The shortfall has sent DUV laser manufacturers scrambling to develop strategies for neon use reduction, but these are not yet considered to be adequate. Meanwhile, the shortage has contributed to the further delay of EUV implementation from 2016-17 to 2020.

The scramble for new commercial sources for helium is being driven by the decision of the US Bureau of Land Management to stop supplying to the merchant market by 2021. This represents 30-40% of the US supply and 15-20% of the global supply. A new source or He has just been discovered in Tanza- nia, but any extraction and purification plant will take 2+ years to come on line. While helium supply is not an immediate concern, pricing has continued inching upward. By 2021, new sources/expansions will need be in full production in order to compensate for the BLM exiting the commercial market. See TECHCET’s Gases Report for actual timelines and details.

TECHCET’s 2016 Gases Report and 2016 Neon Report provide strategic information to ensure business continuity and support category management of the specialty and bulk gas markets and their sup- ply chains. Included are supplier issues, raw material concerns and supplier profiles. Current issues sur- rounding helium, neon, nitrogen trifluoride, tungsten hexafluoride, krypton, xenon, and several more are provided in the Gases Report. High demand applications and forecast on supply vs demand are highlighted in the Neon Report. Global supply chain issues and regulatory changes that impact gases are also discussed in this year’s reports.

TECHCET CA LLC is an advisory service firm focused on Process Materials Supply Chains, Electronic Materials Technology, and Materials Market Analysis for the Semiconductor, Display, Solar/PV, and LED Industries. The Company has been responsible for producing the SEMATECH Critical Material Reports since 2000. For additional information about these reports or about CMC Fabs membership please contact Lita Shon-Roy or Jerry Yang at [email protected] +1-480-332-8336, or visit our websites at www.techcet.com and www.cmcfabs.org.

Other reports released this quarter include:

  •   ALD & High-κ Metal Precursors
  •   Silicon Wafers
  •   Photoresist
  •   Sputter Targets

For additional information about these reports, contact Lita Shon-Roy, [email protected], +1- 480-336-2160, or visit our website at www.techcet.com.

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at: http://cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

Intermolecular, Inc. today announced IMI Labs for Semiconductor, a materials innovation service to help semiconductor companies explore, discover and characterize new materials. With IMI Labs, semiconductor manufacturers now have broad access to Intermolecular’s experimentation platform, materials expertise and data to accelerate materials decisions that have the potential to unlock substantial innovations.

Early identification of new, suitable materials gives semiconductor companies a significant competitive advantage. The pace of materials exploration in the semiconductor industry has increased exponentially since the 1980s, when only a handful of materials were used. Since 2000, 50 new materials have been developed for semiconductor applications, often in complex compounds or stacks. At the same time, semiconductor manufacturers often conduct R&D on production lines, potentially incurring significant risks when introducing a new material.

“The industry is facing major challenges ranging from architecture choices to materials selection. The next wave of semiconductors will require inventing over 40 materials,” said Dr. Scott E. Thompson, IEEE fellow, U. Florida.

“The future of innovation in the semiconductor industry is highly dependent on the discovery and selection of new complex materials,” said Bruce McWilliams, president and chief executive officer, Intermolecular, Inc. “With IMI Labs, semiconductor manufacturers can experiment with various material combinations without bringing new materials into their production fabs. By leveraging our high-throughput platform, expertise and analytics, customers can reduce the time and risk of new materials research and accelerate the materials decision-making process.”

Services available today from IMI Labs for Semiconductor take their roots from work Intermolecular started for the fast growing $77 billion memory market, specifically DRAM and non-volatile memory (NVM). The company is also expanding its offering to address the global $229 billion digital integrated circuits market.  IMI Labs for Semiconductor provides the following benefits for semiconductor materials research:

  • Evaluate and experiment with new materials such as Chalcogenides
  • Experiment with combined stacks or new elements interfacing with multiple layers
  • Expanded empirical data
  • Ability to predict or validate experimental physical and electrical properties with simulation & empirical modeling
  • R&D equipment ready to perform experiments
  • Ability to test new materials before introducing them into production environments

Examples of IMI Labs for Semiconductor services include:

  • High-throughput site-isolated ALD and PVD deposition of multiple materials with in-situ anneal
  • Comprehensive PVD and ALD-based evaluation of several different dielectric, electrode, or interlayer materials in a MIM capacitor film stack
  • Comprehensive PVD-based evaluation of multinary materials (> 5 elements) and metal/metal nitride electrodes
  • Extensive physical and electrical characterization
  • In-depth evaluation of promising materials candidates with temperature dependent testing, stress testing, and Internal Photon Emission (IPE) testing

“Advanced materials are essential to economic security and human well being, with applications in industries aimed at addressing challenges in clean energy, national security, and human welfare, yet it can take 20 or more years to move a material after initial discovery to the market,” according to the Materials Genome Initiative website. “Accelerating the pace of discovery and deployment of advanced material systems will therefore be crucial to achieving global competitiveness in the 21st century.” 

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8nm. The devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices.

GAA devices architectures offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In addition, horizontal NWs are a natural extension of RMG finFETs, in contrast to vertical NWs which require more disruptive technology changes. Furthermore, stacking of NWs maximizes the drive current per footprint. Imec successfully combined these three aspects, and, for the first time, demonstrated vertically stacked horizontal Si NWs at scaled dimensions: 8-nm-diameter wires, 45-nm lateral pitch, and 20-nm vertical separation.

Compared to the conventional bulk FinFET flow, imec implemented two major differences in the process flow. First, shallow trench isolation (STI) densification at 750°C resulted to preserve sharp silicon-germanium (SiGe)/Si interfaces, which is essential for well-controlled Si NW release. Second, a low-complexity ground plane doping scheme was applied, suppressing the bottom parasitic channel.

“By demonstrating stacked nanowires with solid electrostatic control, at scaled dimensions, and using an industry-relevant RMG process on bulk silicon substrates, imec has achieved breakthrough results that can pave the way to realizing sub-10nm technology nodes,” stated Dan Mocuta, Director Logic Device and Integration at imec. “The upcoming research phase will focus on achieving even denser pitches and on leveraging this knowledge to develop gate-all-around lateral nanowire CMOS devices.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs