Tag Archives: letter-mems-tech

Transistors, as used in billions on every computer chip, are nowadays based on semiconductor-type materials, usually silicon. As the demands for computer chips in laptops, tablets and smartphones continue to rise, new possibilities are being sought out to fabricate them inexpensively, energy-saving and flexibly. The group led by Dr. Christian Klinke has now succeeded in producing transistors based on a completely different principle. They use metal nanoparticles which are so small that they no longer show their metallic character under current flow but exhibit an energy gap caused by the Coulomb repulsion of the electrons among one another. Via a controlling voltage, this gap can be shifted energetically and the current can thus be switched on and off as desired. In contrast to previous similar approaches, the nanoparticles are not deposited as individual structures, rendering the production very complex and the properties of the corresponding components unreliable, but, instead, they are deposited as thin films with a height of only one layer of nanoparticles. Employing this method, the electrical characteristics of the devices become adjustable and almost identical.

These Coulomb transistors have three main advantages that make them interesting for commercial applications: The synthesis of metal nanoparticles by colloidal chemistry is very well controllable and scalable. It provides very small nanocrystals that can be stored in solvents and are easy to process. The Langmuir-Blodgett deposition method provides high-quality monolayered films and can also be implemented on an industrial scale. Therefore, this approach enables the use of standard lithography methods for the design of the components and the integration into electrical circuits, which renders the devices inexpensive, flexible, and industry-compatible. The resulting transistors show a switching behavior of more than 90% and function up to room temperature. As a result, inexpensive transistors and computer chips with lower power consumption are possible in the future. The research results have now been published in the scientific journal “Science Advances“.

“Scientifically interesting is that the metal particles inherit semiconductor-like properties due to their small size. Of course, there is still a lot of research to be done, but our work shows that there are alternatives to traditional transistor concepts that can be used in the future in various fields of application”, says Christian Klinke. “The devices developed in our group can not only be used as transistors, but they are also very interesting as chemical sensors because the interstices between the nanoparticles, which act as so-called tunnel barriers, react highly sensitive to chemical deposits.”

How low can we go?


July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

The problem is a fundamental incompatibility in communication styles.

That conclusion might crop up during divorce proceedings, or describe a diplomatic row. But scientists designing polymers that can bridge the biological and electronic divide must also deal with incompatible messaging styles. Electronics rely on racing streams of electrons, but the same is not true for our brains.

“Most of our technology relies on electronic currents, but biology transduces signals with ions, which are charged atoms or molecules,” said David Ginger, professor of chemistry at the University of Washington and chief scientist at the UW’s Clean Energy Institute. “If you want to interface electronics and biology, you need a material that effectively communicates across those two realms.”

Lead author Rajiv Giridharagopal, left, and co-author Lucas Flagg, right, standing next to an atomic force microscope. Credit: Dane deQuilettes

Lead author Rajiv Giridharagopal, left, and co-author Lucas Flagg, right, standing next to an atomic force microscope. Credit: Dane deQuilettes

Ginger is lead author of a paper published online June 19 in Nature Materials in which UW researchers directly measured a thin film made of a single type of conjugated polymer — a conducting plastic — as it interacted with ions and electrons. They show how variations in the polymer layout yielded rigid and non-rigid regions of the film, and that these regions could accommodate electrons or ions – but not both equally. The softer, non-rigid areas were poor electron conductors but could subtly swell to take in ions, while the opposite was true for rigid regions.

Organic semiconducting polymers are complex matrices made from repeating units of a carbon-rich molecule. An organic polymer that can accommodate both types of conduction — ion and electrons — is the key to creating new biosensors, flexible bioelectronic implants and better batteries. But differences in size and behavior between tiny electrons and bulky ions have made this no easy task. Their results demonstrate how critical the polymer synthesis and layout process is to the film’s electronic and ionic conductance properties. Their findings may even point the way forward in creating polymer devices that can balance the demands of electronic transport and ion transport.

“We now understand the design principles to make polymers that can transport both ions and electrons more effectively,” said Ginger. “We even demonstrate by microscopy how to see the locations in these soft polymer films where the ions are transporting effectively and where they aren’t.”

Ginger’s team measured the physical and electrochemical properties of a film made out of poly(3-hexylthiophene), or P3HT, which is a relatively common organic semiconductor material. Lead author Rajiv Giridharagopal, a research scientist in the UW Department of Chemistry, probed the P3HT film’s electrochemical properties in part by borrowing a technique originally developed to measure electrodes in lithium-ion batteries.

The approach, electrochemical strain microscopy, uses a needle-like probe suspended by a mechanical arm to measure changes in the physical size of an object with atomic-level precision. Giridharagopal discovered that, when a P3HT film was placed in an ion solution, certain regions of the film could subtly swell to let ions flow into the film.

“This was an almost imperceptible swelling — just 1 percent of the film’s total thickness,” said Giridharagopal. “And using other methods, we discovered that the regions of the film that could swell to accommodate ion entry also had a less rigid structure and polymer arrangement.”

More rigid and crystalline regions of the film could not swell to let in ions. But the rigid areas were ideal patches for conducting electrons.

Ginger and his team wanted to confirm that structural variations in the polymer were the cause of these variations in electrochemical properties of the film. Co-author Christine Luscombe, a UW associate professor of materials science and engineering and member of the Clean Energy Institute, and her team made new P3HT films that had different levels of rigidity based on variations in polymer arrangement.

By subjecting these new films to the same array of tests, Giridharagopal showed a clear correlation between polymer arrangement and electrochemical properties. The less rigid and more amorphous polymer layouts yielded films that could swell to let in ions, but were poor conductors of electrons. More crystalline polymer arrangements yielded more rigid films that could easily conduct electrons. These measurements demonstrate for the first time that small structural differences in how organic polymers are processed and assembled can have major consequences for how the film accommodates ions or electrons. It may also mean that this tradeoff between the needs of ion and electrons is unavoidable. But these results give Ginger hope that another solution is possible.

“The implication of these findings is that you could conceivably embed a crystalline material — which could transport electrons — within a material that is more amorphous and could transport ions,” said Ginger. “Imagine that you could harness the best of both worlds, so that you could have a material that is able to effectively transport electrons and swell with ion uptake — and then couple the two with one another.”

Researchers from MIPT’s Center of Shared Research Facilities have found a way to control oxygen concentration in tantalum oxide films produced by atomic layer deposition. These thin films could be the basis for creating new forms of nonvolatile memory. The paper was published in the journal ACS Applied Materials & Interfaces, which has an impact factor of 7.14.

Want nonvolatile memory that’s fast as RAM and has the capacity of flash?

Because data storage and processing solutions are so central to modern technology, many research teams and companies are pursuing new types of computer memory. One of their major goals is to develop universal memory — a storage medium that would combine the high speed of RAM with nonvolatility of a flash drive.

A promising technology for creating such a device is resistive switching memory, or ReRAM. It works by changing the resistance across a memory cell as a result of applied voltage. Since each cell has a high- and a low-resistance state, it can be used to store information, e.g., in the form of zeros and ones.

A ReRAM cell can be realized as a metal-dielectric-metal structure. Oxides of transition metals such as hafnium and tantalum have proved useful as the dielectric component of this layered structure. Applying voltage to a memory cell that is based on these materials causes oxygen migration, changing its resistance. This makes the distribution of oxygen concentration in the oxide film a crucial parameter determining the functional properties of the memory cell.

However, despite significant advances in ReRAM development, flash memory shows no sign of losing ground. The reason for this is that flash memory allows for three-dimensional memory cell stacking, which enables a much greater storage density. In contrast to this, oxygen-deficient film deposition techniques normally used in ReRAM design are not applicable to functional 3-D architectures.

That’s where atomic layer deposition comes in

In a bid to find an alternative technique, MIPT researchers turned to atomic layer deposition, a chemical process by which thin films can be produced on the surface of a material. During the last decade, ALD has become increasingly widespread, with numerous applications in nanoelectronics, optics, and the biomedical industry. There are two major advantages to atomic layer deposition. The first one is the unprecedented control over film thickness: It is possible to deposit films that are several nanometers thick with an error of a fraction of a nanometer. The other advantage is that ALD enables conformal coating of 3-D structures, which is problematic for most of the currently used nanofilm deposition techniques.

In an ALD process, a substrate is sequentially exposed to two chemicals that are known as the precursor and the reactant. It is the chemical reaction between these two substances that produces a coating layer. In addition to the element used in the coating, precursors contain other compounds — e.g., of carbon or chlorine — called ligands. They facilitate the reaction but, in an ideal ALD process, have to be completely removed from the resulting film once the interaction with the other chemical (reactant) has occurred. It is vital to choose the right substances for use in atomic layer deposition. Although it proves difficult to deposit oxide films with variable oxygen concentration by ALD, they are essential for ReRAM.

“The hardest part in depositing oxygen-deficient films was finding the right reactants that would make it possible to both eliminate the ligands contained in the metallic precursor and control oxygen content in the resulting coating,” says Andrey Markeev, who holds a PhD in physics and mathematics and is a leading researcher at MIPT. “We achieved this by using a tantalum precursor, which by itself contains oxygen, and a reactant in the form of plasma-activated hydrogen.” Confirming the experimental findings turned out to be a challenge in itself. As soon as the experimental sample is removed from the vacuum chamber, which houses it during ALD, and exposed to the atmosphere, this causes modifications in the top layer of the dielectric, making it impossible to detect oxygen deficiency using analytic techniques such as electron spectroscopy, which target the surface of the sample.

“In this study, we needed not just to obtain the films containing different amounts of oxygen but also to confirm this experimentally,” says Konstantin Egorov, a PhD student at MIPT. “To do this, our team worked with a unique experimental cluster, which allowed us to grow films and study them without breaking the vacuum.”

Queen’s University Belfast researchers have discovered a new way to create extremely thin electrically conducting sheets, which could revolutionise the tiny electronic devices that control everything from smart phones to banking and medical technology.

Through nanotechnology, physicists Dr Raymond McQuaid, Dr Amit Kumar and Professor Marty Gregg from Queen’s University’s School of Mathematics and Physics, have created unique 2D sheets, called domain walls, which exist within crystalline materials.

The sheets are almost as thin as the wonder-material graphene, at just a few atomic layers. However, they can do something that graphene can’t – they can appear, disappear or move around within the crystal, without permanently altering the crystal itself.

This means that in future, even smaller electronic devices could be created, as electronic circuits could constantly reconfigure themselves to perform a number of tasks, rather than just having a sole function.

Professor Marty Gregg explains: “Almost all aspects of modern life such as communication, healthcare, finance and entertainment rely on microelectronic devices. The demand for more powerful, smaller technology keeps growing, meaning that the tiniest devices are now composed of just a few atoms – a tiny fraction of the width of human hair.”

“As things currently stand, it will become impossible to make these devices any smaller – we will simply run out of space. This is a huge problem for the computing industry and new, radical, disruptive technologies are needed. One solution is to make electronic circuits more ‘flexible’ so that they can exist at one moment for one purpose, but can be completely reconfigured the next moment for another purpose.”

The team’s findings, which have been published in Nature Communications, pave the way for a completely new way of data processing.

Professor Gregg says: “Our research suggests the possibility to “etch-a-sketch” nanoscale electrical connections, where patterns of electrically conducting wires can be drawn and then wiped away again as often as required.

“In this way, complete electronic circuits could be created and then dynamically reconfigured when needed to carry out a different role, overturning the paradigm that electronic circuits need be fixed components of hardware, typically designed with a dedicated purpose in mind.”

There are two key hurdles to overcome when creating these 2D sheets, long straight walls need to be created. These need to effectively conduct electricity and mimic the behavior of real metallic wires. It is also essential to be able to choose exactly where and when the domain walls appear and to reposition or delete them.

Through the research, the Queen’s researchers have discovered some solutions to the hurdles. Their research proves that long conducting sheets can be created by squeezing the crystal at precisely the location they are required, using a targeted acupuncture-like approach with a sharp needle. The sheets can then be moved around within the crystal using applied electric fields to position them.

Dr Raymond McQuaid, a recently appointed lecturer in the School of Mathematics and Physics at Queen’s University, added: “Our team has demonstrated for the first time that copper-chlorine boracite crystals can have straight conducting walls that are hundreds of microns in length and yet only nanometres thick. The key is that, when a needle is pressed into the crystal surface, a jigsaw puzzle-like pattern of structural variants, called “domains”, develops around the contact point. The different pieces of the pattern fit together in a unique way with the result that the conducting walls are found along certain boundaries where they meet.

“We have also shown that these walls can then be moved using applied electric fields, therefore suggesting compatibility with more conventional voltage operated devices. Taken together, these two results are a promising sign for the potential use of conducting walls in reconfigurable nano-electronics.”

The State University of New York ranked 38th in the “Top 100 Worldwide Universities Granted U.S. Utility Patents for 2016,” according to the National Academy of Inventors (NAI) and Intellectual Property Owners Association (IPO), which publishes the ranking annually based on U.S. Patent and Trademark Office data.

SUNY campuses were awarded 57 U.S. utility patents for advances in biotechnology, cancer research, manufacturing, renewable energy, and much more.

“Across SUNY, our faculty and students partner to make groundbreaking discoveries in a broad spectrum of areas,” said SUNY Chancellor Nancy L. Zimpher. “Through more than 1,300 U.S. patents earned to date, SUNY research has led to hundreds of new technologies and advances that address society’s greatest challenges and have a positive impact on quality of life in New York and beyond. Congratulations to all those at SUNY whose important work has elevated us to this prominent world ranking.”

“This recognition marks a terrific accomplishment for our growing number of SUNY research faculty, who work tirelessly to mentor students while engaging them in research opportunities that advance the frontiers of knowledge and address state and global challenges,” said SUNY Provost and Executive Vice Chancellor, and NAI Fellow, Alexander N. Cartwright. “Our faculty, a number of whom are NAI members, are a tremendous source of pride for SUNY.”

“From energy, to medicine, to consumer technologies and more, innovation is at an all-time high throughout New York State, and SUNY is at the center of it,” said SUNY Vice Chancellor for Research and Economic Development Grace Wang. “With a multitude of influential research institutions, supported by the largest, most comprehensive university-connected research foundation in the country, SUNY is driving positive change across the globe.”

Research at SUNY produces more than 100 new technologies every year. SUNY inventors have contributed to some of the most transformative technologies in history, including the heart-lung machine, bar code scanner, MRI, and several FDA-approved therapeutics. Some recent SUNY innovations include:

University at Albany is helping law enforcement fight crime by using scattered light to perform microscopic analysis of biological and chemical samples, an approach that allows investigators to immediately confirm the source of biological stains found at crime scenes.

Binghamton University may one day cut air conditioning costs dramatically by creating light-filtering dyes that, when applied to glass, block heat while letting light pass through.

University at Buffalo is testing a reengineered hormonal treatment for diabetes and obesity. Telemedicine will be used to link children and their families to treatment they would otherwise only have access to in a local office or school.

SUNY Downstate Medical Center is working toward a lower-power, more stable alternative to implantable cardioverter defibrillators to re-start the heart. The technology re-purposes a nerve stimulator to use the body’s own nervous system to control the heart.

SUNY-ESF researchers have developed a “Trojan Horse” to attack cancer cells using special polymers that trick cancer cells into directly ingesting chemotherapeutic drugs so they are destroyed from the inside out, thus reducing damage to normal cells.

Upstate Medical University is advancing concussion assessment through a new set of cognitive tests that will help doctors and clinicians properly diagnose and manage concussions.

SUNY College at Optometry researchers have suggested that targeting a cell’s communication channels or gap junction could slow the progress of glaucoma.

SUNY Polytechnic Institute researchers invented a nanoscale scaffold that mimics the human eye which can help test possible glaucoma drugs and other therapeutics.

Stony Brook University redesigned a catheter that incorporates LED lights to reduce the likelihood of infection after the device is inserted into a patient’s body.

Some problems are so challenging to solve that even the most advanced computers need weeks, not seconds, to process them.

Now a team of researchers at Georgia Institute of Technology and University of Notre Dame has created a new computing system that aims to tackle one of computing’s hardest problems in a fraction of the time.

“We wanted to find a way to solve a problem without using the normal binary representations that have been the backbone of computing for decades,” said Arijit Raychowdhury, an associate professor in Georgia Tech’s School of Electrical and Computer Engineering.

Their new system employs a network of electronic oscillators to solve graph coloring tasks – a type of problem that tends to choke modern computers.

Details of the study were published April 19 in the journal Scientific Reports.  The research was conducted with support from the National Science Foundation, the Office of Naval Research, the Semiconductor Research Corporation and the Center for Low Energy Systems Technology.

“Applications today are demanding faster and faster computers to help solve challenges like resource allocation, machine learning and protein structure analysis – problems which at their core are closely related to graph coloring,” Raychowdhury said. “But for the most part, we’ve reached the limitations of modern digital computer processors. Some of these problems that are so computationally difficult to perform, it could take a computer several weeks to solve.”

A graph coloring problem starts with a graph – a visual representation of a set of objects connected in some way. To solve the problem, each object must be assigned a color, but two objects directly connected cannot share the same color. Typically, the goal is to color all objects in the graph using the smallest number of different colors.

In designing a system different from traditional transistor-based computing, the researchers took their cues from the human brain, where processing is handled collectively, such as a neural oscillatory network, rather than with a central processor.

“It’s the notion that there is tremendous power in collective computing,” said Suman Datta, Chang Family professor in Notre Dame’s College of Engineering and one of the study’s co-authors. “In natural forms of computing, dynamical systems with complex interdependencies evolve rapidly and solve complex sets of equations in a massively parallel fashion.”

The electronic oscillators, fabricated from vanadium dioxide, were found to have a natural ability that could be harnessed for graph coloring problems. When a group of oscillators were electrically connected via capacitive links, they automatically synchronized to the same frequency – oscillating at the same rate. Meanwhile, oscillators directly connected to one another would operate at different phases within the same frequency, and oscillators in the same group but not directly connected would sync in both frequency and phase.

“If you suppose that each phase represents a different color, this system was essentially mimicking naturally the solution to a graph coloring problem,” said Raychowdhury, who is also the ON Semiconductor Junior Professor at Georgia Tech.

The researchers were able to create a small network of oscillators to solve graph coloring problems with the same number of objects, which are also referred to as nodes or vertices. But even more significant, the new system theoretically proved that a connection existed between graph coloring and the natural dynamics of coupled oscillatory systems.

“This is a critical step because we can prove why this is happening and that it covers all possible instances of graphs,” Raychowdhury said. “This opens up a new way of performative computation and constructing novel computational models. This is novel in that it’s a physics-based computing approach, but it also presents tantalizing opportunities for building other customized analog systems for solving hard problems efficiently.”

That could be valuable to a range of companies looking for computers to help optimize their resources, such as a power utility wanting to maximize efficiency and usage of a vast electrical grid under certain constraints.

“This work provides one of the first constructive ways to build continuous time dynamical system solvers for a combinatorial optimization problem with a working demonstration using compact scalable post-CMOS devices,” said Abhinav Parihar, a Georgia Tech student who worked on the project.

The next step would be building a larger network of oscillators that could handle graph coloring problems with more objects at play.

“Our goal is to reach a system with hundreds of oscillators, which would put us in striking distance of developing a computing substrate that could solve graph coloring problems whose optimal solutions are not yet known to mankind,” Datta said.

CITATION: Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta and Arijit Raychowdhury, “Vertex coloring of graphs via phase dynamics of coupled oscillatory networks,” (Scientific Reports, April 2017). http://dx.doi.org/10.1038/s41598-017-00825-1

 SiTime Corporation, a developer of MEMS-based timing solutions and a wholly owned subsidiary of MegaChips Corporation (Tokyo Stock Exchange: 6875), today introduced the SiT1569 oscillator and SiT1576 Super-TCXO with expanded frequency range. These timing solutions, available in a tiny CSP (chip-scale package), enable coin-cell battery operated IoT sensors to run up to 10 years. By using SiTime’s revolutionary TempFlat MEMS and mixed-signal technology, these devices deliver increased timekeeping accuracy and system power savings. The ultra-reliable, low-jitter SiT1576 and SiT1569 reference clocks are designed to drive microcontrollers (MCUs) and analog front end (AFE) modules in a range of portable and IoT applications such as railroad activity sensors in harsh environments, seismic sensor interface applications, and personal medical diagnostics.

“SiTime’s unique timing solutions are solving the most difficult design challenges. Smaller size, long battery life, and timing accuracy are becoming increasingly important with the rapid growth of IoT,” said Piyush Sevalia, executive vice president of marketing at SiTime. “The SiT1569 oscillator and SiT1576 Super-TCXO offer the best size, power, and accuracy to enable new IoT applications.”

About the SiT1569 Oscillator and SiT1576 Super-TCXO
These MEMS timing solutions enable unprecedented size reduction and battery life by replacing bulky quartz oscillators that have limited frequency options, or internally-generated (MCU) power-hungry frequencies that lack accuracy and consume I/O pins.

Key specifications:

  • Smallest package, CSP-4, up to 80% smaller than quartz solutions
    • 1.5 mm x 0.8 mm (1.2mm2 footprint)
    • 0.60 mm height for lower profile
  • Power supply current
    • 2.5 µA (100 kHz, SiT1569)
    • 5.5 µA (100 kHz, SiT1576)
  • Frequency range (factory programmed for fast delivery)
    • 1 Hz to 2 MHz (SiT1576)
    • 1 Hz to 462 kHz (SiT1569)
  • All-inclusive frequency stability includes initial offset and variations over industrial temperature (-40 to +85°C); a more accurate clock enables better timekeeping and extends battery life
    • ±5 ppm (SiT1576)
    • ±50 ppm (SiT1569)
  • Excellent jitter performance
    • 2.2 ns RMS period jitter (100 kHz, SiT1576)
    • 4.0 ns RMS period jitter (100 kHz, SiT1569)
  • Up to 65% faster startup time
    • 300 milliseconds (max.)
  • Highest reliability and resilience; MEMS resonator mass is 500 to 1000 times smaller than quartz
    • 30 times higher shock and vibration resistance
    • 30 times higher reliability, at 1 billion hours MTBF

Samples of the SiT1576 Super-TCXO and SiT1569 oscillator are available now from SiTime for qualified customers. Production volume is planned for Q3 2017.

At this week’s 2017 Symposia on VLSI Technology and Circuits, imec, a research and innovation hub in nano-electronics and digital technology, reported record breaking values below 10^-9 Ohm.cm² for PMOS source/drain contact resistivity. These results were obtained through shallow Gallium implantation on p-SiliconGermanium (p-SiGe) source/drain contacts with subsequent pulsed nanosecond laser anneal.

In future N7/N5 nodes, the source/drain contact area of the transistors becomes so small that the contact resistance threatens to become the dominating parasitic factor, resulting in suboptimal transistor functioning. Researchers have therefore been working on techniques to reduce the contact resistance on highly doped n-Si and p-SiGe source/drain contacts, aiming for values below 10^-9 Ohm.cm². Together with colleagues from the KU Leuven (Belgium), Fudan University (Shanghai, China), and Applied Materials (Sunnyvale, USA), imec’s specialists concentrated on p-SiGe contacts, comparing the effects of high-dose Boron and Gallium doping.

For the comparison, the researchers implanted SiGe separate wafers with a high dose of Gallium or Boron and applied various anneal processes. They then fabricated multi-ring circular transmission line model structures, which are highly sensitive to contact resistance. Subsequent measurements revealed the lowest contact resistance for the Gallium-implanted structures annealed with Applied Material’s nanosecond laser anneal. This process uniquely causes a Ge/Ga surface segregation, which is responsible for the ultralow sub-10^-9 Ohm.cm² contact resistivity. This result show a possible way to process next-generation technology nodes.

Naoto Horiguchi, distinguished member of the technical staff at imec indicated: “This breakthrough achievement in our search to develop solutions for next generation deeply-scaled CMOS provides a possible path for further performance improvement using the current source/drain schemes in N7/N5 nodes.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

imec tin