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University of Colorado researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductor technologies, have developed new microscopic imaging techniques to help advance next-generation nanotechnology in applications ranging from data storage to medicine.

The research focuses on leveraging powerful tabletop microscopes equipped with coherent beams of extreme-ultraviolet (EUV) light. Traditional scanning electron and atomic force microscopy techniques can damage a sample. The University of Colorado’s approach promises quantitative full-field imaging with as much as a 20x improvement in spatial resolution, ultimately resulting in smarter, more energy-efficient nanocircuit designs.

“Better imaging techniques are critical for all areas of science and advanced technology, and current imaging techniques have not reached their fundamental limits in terms of spatial and temporal resolutions, dose, speed or chemical sensitivity,” said Margaret Murnane, professor of Physics and Electrical and Computer Engineering at the University of Colorado, Boulder. “Tabletop microscopes are needed for iterative design and optimization across a broad range of nanoscience and nanotechnology applications, as we work as an industry to continue to advance Moore’s Law.”

Until recently, the resolution of X-ray microscopes was severely limited by diffractive optics. Although 10 nanometer (nm) spatial resolution was demonstrated, 25nm is typical – nowhere near the wavelength limit, according to the research team. Electron microscopies cannot simultaneously achieve high spatial and temporal resolution.

Opaque, disordered or scattering samples that are common in chemistry, materials and biology present a formidable challenge using any imaging modality. Notable demonstrations aside, current X-ray, electron and optical microscopies are simply too cumbersome and slow to routinely image functioning systems in real space and time, severely limiting progress.

Murnane explains that new coherent, short wavelength light sources fill the critical need for metrology to bridge this gap. As an example, although the Ruby laser was first demonstrated 55 years ago (which emitted coherent beams in the red region of the spectrum at 694nm), the shortest wavelength laser in widespread use is the excimer laser around 193nm. This means that in 55 years, the wavelength of widely accessible lasers has been reduced by less than a factor of 4.

The University of Colorado’s work employs coherent, or laser-like, beams of EUV light with wavelength at 30nm nearly an order of magnitude shorter that the excimer, achieving very high contrast images with a resolution of 40nm laterally and 5 angstrom (Å) vertically, representing a technology poised to change the industry.

Further leveraging advantages of the tabletop model, the University of Colorado team plans to demonstrate in the next two to five years coherent EUV and X- ray microscopes that produce real-time movies of functioning materials with less than 5nm lateral resolution and 1 Å vertical resolution in 3D.

The team’s deep-ultraviolet and EUV laser-like source technology could be used for defect detection or other nanometrology applications — either as a stand-alone solution or as an inline tool. The EUV microscope could also provide high-contrast, low-damage, full-field, real-time imaging of functioning circuits and nanosystems, among other fabrication application usages.

“Many industries that harness nanotechnologies can benefit from better microscopes for iterative and smart designs,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC. “The resolution will only continue to improve as the illumination wavelengths decrease.”

Nanoengineers at the University of California, San Diego used an innovative 3D printing technology they developed to manufacture multipurpose fish-shaped microrobots — called microfish — that swim around efficiently in liquids, are chemically powered by hydrogen peroxide and magnetically controlled. These proof-of-concept synthetic microfish will inspire a new generation of “smart” microrobots that have diverse capabilities such as detoxification, sensing and directed drug delivery, researchers said.

3-D-printed microfish contain functional nanoparticles that enable them to be self-propelled, chemically powered and magnetically steered. The microfish are also capable of removing and sensing toxins. Credit: J. Warner, UC San Diego Jacobs School of Engineering.

3-D-printed microfish contain functional nanoparticles that enable them to be self-propelled, chemically powered and magnetically steered. The microfish are also capable of removing and sensing toxins. Credit: J. Warner, UC San Diego Jacobs School of Engineering.

The technique used to fabricate the microfish provides numerous improvements over other methods traditionally employed to create microrobots with various locomotion mechanisms, such as microjet engines, microdrillers and microrockets. Most of these microrobots are incapable of performing more sophisticated tasks because they feature simple designs — such as spherical or cylindrical structures — and are made of homogeneous inorganic materials. In this new study, researchers demonstrated a simple way to create more complex microrobots.

The research, led by Professors Shaochen Chen and Joseph Wang of the NanoEngineering Department at the UC San Diego, was published in the Aug. 12 issue of the journal Advanced Materials.

By combining Chen’s 3D printing technology with Wang’s expertise in microrobots, the team was able to custom-build microfish that can do more than simply swim around when placed in a solution containing hydrogen peroxide. Nanoengineers were able to easily add functional nanoparticles into certain parts of the microfish bodies. They installed platinum nanoparticles in the tails, which react with hydrogen peroxide to propel the microfish forward, and magnetic iron oxide nanoparticles in the heads, which allowed them to be steered with magnets.

“We have developed an entirely new method to engineer nature-inspired microscopic swimmers that have complex geometric structures and are smaller than the width of a human hair. With this method, we can easily integrate different functions inside these tiny robotic swimmers for a broad spectrum of applications,” said the co-first author Wei Zhu, a nanoengineering Ph.D. student in Chen’s research group at the Jacobs School of Engineering at UC San Diego.

As a proof-of-concept demonstration, the researchers incorporated toxin-neutralizing nanoparticles throughout the bodies of the microfish. Specifically, the researchers mixed in polydiacetylene (PDA) nanoparticles, which capture harmful pore-forming toxins such as the ones found in bee venom. The researchers noted that the powerful swimming of the microfish in solution greatly enhanced their ability to clean up toxins. When the PDA nanoparticles bind with toxin molecules, they become fluorescent and emit red-colored light. The team was able to monitor the detoxification ability of the microfish by the intensity of their red glow.

“The neat thing about this experiment is that it shows how the microfish can doubly serve as detoxification systems and as toxin sensors,” said Zhu.

“Another exciting possibility we could explore is to encapsulate medicines inside the microfish and use them for directed drug delivery,” said Jinxing Li, the other co-first author of the study and a nanoengineering Ph.D. student in Wang’s research group.

How this new 3D printing technology works

The new microfish fabrication method is based on a rapid, high-resolution 3D printing technology called microscale continuous optical printing (μCOP), which was developed in Chen’s lab. Some of the benefits of the μCOP technology are speed, scalability, precision and flexibility. Within seconds, the researchers can print an array containing hundreds of microfish, each measuring 120 microns long and 30 microns thick. This process also does not require the use of harsh chemicals. Because the μCOP technology is digitized, the researchers could easily experiment with different designs for their microfish, including shark and manta ray shapes.

“With our 3D printing technology, we are not limited to just fish shapes. We can rapidly build microrobots inspired by other biological organisms such as birds,” said Zhu.

The key component of the μCOP technology is a digital micromirror array device (DMD) chip, which contains approximately two million micromirrors. Each micromirror is individually controlled to project UV light in the desired pattern (in this case, a fish shape) onto a photosensitive material, which solidifies upon exposure to UV light. The microfish are built using a photosensitive material and are constructed one layer at a time, allowing each set of functional nanoparticles to be “printed” into specific parts of the fish bodies.

“This method has made it easier for us to test different designs for these microrobots and to test different nanoparticles to insert new functional elements into these tiny structures. It’s my personal hope to further this research to eventually develop surgical microrobots that operate safer and with more precision,” said Li.

Today, imec, a nanoelectronics research center, Holst Centre (set up by imec and The Netherlands Organization for Applied Scientific Research, TNO), and the Industrial Design Engineering (IDE) faculty of Delft University of Technology (TU Delft), announced the introduction of a new wireless electroencephalogram (EEG) headset that can be worn comfortably and achieves a high-quality EEG signal. The headset enables effective brain-computer interfacing and can monitor emotions and mood in daily life situations using a smartphone application.

Wireless technology that measures body parameters has become increasingly popular in lifestyle applications. Imec and Holst Centre aim to extend the functionality of consumer applications and true healthcare monitoring wearables. To realize this, they develop headsets that combine medical-grade data acquisition with increased comfort. Imec’s wireless EEG headsets with dry electrodes are easy to apply and support long-term daily life monitoring. Such headsets can be used in consumer applications such as games that monitor relaxation, engagement and concentration. Wireless headsets can also be used for attention training, sleep training and treatment of Attention Deficit Hyperactivity Disorder (ADHD).

“Leveraging imec’s strong background in EEG sensing, dry polymer and active electrodes, miniaturized and low-power data acquisition, and low-power wireless interfaces to smartphones, we were able to focus on the ergonomics of this project. In doing so, we have successfully realized this unique combination of comfort and effectiveness at the lowest possible cost to the future user,” stated Bernard Grundlehner, EEG system architect at imec.

Designing a wireless EEG headset with dry electrodes presents several technical challenges, such as finding a balance between comfort and signal quality. To ensure good signal quality, the dry electrodes must be applied to the head with sufficient pressure. This becomes especially critical when the measurement is done over longer periods of time. It is also very important to retain this balance to accommodate a variety of people with different head sizes and shapes. However, increasing the pressure can cause user discomfort as evidenced by previous product iterations.

Imec and Holst Centre’s new headset manages to strike a harmonious balance between comfort and signal quality. This was achieved by a design procedure that optimizes shape and stiffness by prototyping and testing repeatedly in very short loops. A team of six master students from the faculty IDE of TU Delft worked on this challenge in their Advanced Embodiment Design (AED) project. After an analysis of the technology that was developed by imec and Holst Centre, design research was carried out among potential users and applications. This research led to the development of a concept which minimizes intrusiveness, making comfort possible for a large segment of the targeted population outside of a controlled research environment.

The EEG headset is manufactured in one piece using 3-D printing techniques, after which the electronic components are applied and covered by a 3-D-printed rubber inlay. The sensors that acquire the EEG signal are situated at the front of the headset in order to allow for optimal EEG signal acquisition related to emotion and mood variations. The mobile app relates the user’s emotional state to environmental information such as agenda, location, proximity to others and time of day, in order to provide feedback about the unconscious effects of the environment on the user’s emotions, thus creating awareness and actionable new insights.

Cypress Semiconductor Corp. today announced a new family of Energy Harvesting Power Management Integrated Circuits (PMICs) that enable tiny, solar-powered wireless sensors for Internet of Things (IoT) applications. The new devices are the world’s lowest-power, single-chip Energy Harvesting PMICs, and can be used with solar cells as small as 1 cm(2). The new PMIC devices are fully integrated, making them ideal for batteryless Wireless Sensor Nodes (WSNs) that monitor physical and environmental conditions for smart homes, commercial buildings, factories, infrastructure and agriculture.  Cypress offers a complete, battery-free Energy Harvesting solution that pairs the S6AE101A PMIC, the first device in the new family, with the EZ-BLE PRoC module for Bluetooth Low Energy connectivity, along with supporting software, in a $49 kit.

The WSN IoT device market is expected to grow to more than 5 billion units by 2020, putting a premium on battery-free implementations to reduce cost and maintenance problems. The placement of a WSN may limit its size and the amount of light available, thereby limiting the size and power output of the solar module and the startup power available for the Energy Harvesting PMIC. The new Cypress Energy Harvesting PMIC devices address these challenges with startup power of 1.2uW–4x lower than the nearest competitor–and consumption current as low as 250nA, maximizing the power available for the sensing, processing and communications functions of a target application. The fully-certified, small-form-factor EZ-BLE PRoC module, which is based on Cypress’s PRoC BLE Programmable Radio-on-Chip solution, works with the PMIC devices to contribute to the low power and ease-of-use of an energy harvesting system solution.

“The most compelling new Wireless Sensor Nodes that will drive IoT growth are self-powered, can be deployed anywhere for more than 10 years, and require minimal deployment and maintenance costs,” said Kiyoe Nagaya, vice president of the Analog Business Unit at Cypress. “Using our new Energy Harvesting PMIC and EZ-BLE PRoC Bluetooth Smart module, Cypress offers a complete solution that enables developers to create solar-powered WSNs for batteryless IoT devices.”

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, and the Singh Center for Nanotechnology at the University of Pennsylvania (Penn) are announcing a cooperation agreement in the field of nanoimprint technologies. As part of this cooperation, Penn has recently received the equipment set and the technology know-how for Substrate Conformal Imprint Lithography (SCIL), that will expand the capabilities of the recently installed MA/BA6 Gen3 Mask Aligner from SUSS MicroTec at Penn.

Substrate Conformal Imprint Lithography (SCIL) is a nanoimprint technique combining the advantages of both soft and rigid stamps, allowing large-area patterning and sub-50nm resolution to be achieved at the same time. SCIL is applied in diverse fields, ranging from HB LEDs, Photovoltaics, MEMS, NEMS and mass production of optical gratings for gas sensing and telecommunications.

The Singh Center for Nanotechnology will implement SCIL for use in plasmonic devices, semiconductor nanowires, flexible nanocrystal electronics, biodegradable sensors and MEMS batteries.  In addition, Lithography Manager Dr. Gerald Lopez will lead the Center’s efforts in qualifying new nanoimprint materials and related process technology development in close cooperation with SUSS MicroTec.

As a further important part of the cooperation, SUSS MicroTec`s customers will gain direct access to the cleanroom facilities and the equipment set installed at Penn, serving as a demonstration center for North American customers. The experience and high technology level of Penn allows the customer to see the entire process flow, the imprinting process itself and the subsequent steps up to a finished device.

“We are pleased to collaborate with SUSS MicroTec for developing applications with SCIL. By combining our strengths in micro- and nanofabrication, we are able to provide superior nanoimprint capabilities to our researchers,” stated Professor Mark Allen, Scientific Director of the Singh Center for Nanotechnology and Alfred Fitler Moore, Professor of Electrical and Systems Engineering. “This industrial partnership enhances our ability to demonstrate how nanoimprint technology serves as a catalyst in research and its translation into the commercial sector.”

“We are very happy about the cooperation with the Singh Center for Nanotechnology. Their work will contribute strongly to further commercialize this large area nano-patterning technique in order to accelerate the adoption for volume production. In addition, our customers do not just benefit from the possibility to use Penn’s facilities and get insights to the entire imprinting process, but also from Penn´s knowledge, by having an experienced partner at hand”, says Ralph Zoberbier, General Manager Exposure and Laser Processing of SUSS MicroTec.“

By Jeongdong Choe, PhD., TechInsights

A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm or sub-20nm generation. Do we still think the 2D NAND Flash technologies have hit the scaling wall? According to TechInsights’ deep-dive analysis on current and future NAND Flash technologies, although 3D V-NAND architecture could help with the scaling limit, we believe the 2D MLC and TLC NAND Flash technologies remain strong and cost effective for 14nm, 12nm and even for single-digit nanometer node.

When it comes to 3D NAND technology, Samsung has been developing and mass-producing 32-tier V-NAND architecture (for technical analysis related to the Samsung 3D V-NAND click here) with MLC and TLC for their 850 PRO and 850 EVO since 2014, although, this is not the final goal for Samsung due to a relatively low yield, process complexity and bit-cost viewpoints. More 3D Flash products may appear at the end of this year, or early in 2016, as major NAND players such as Toshiba, SanDisk, Micron, Intel, and SK-Hynix bring out their 3D products with 24-tier, 32-tier or 48-tier FG (floating gate)/CTF (charge-trap-flash) architecture (Figure 1).

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

However, the ultimate target for 3D NAND is 128-tier or at least 64-tier structure from the bit-cost viewpoints. In that case, the aspect ratio of Si-channel and common source contacts would be over 80:1, which is a strong burden for process integration engineers. In addition, the uniformity of the 64-tier or 128-tier NAND cell characteristics in a NAND string and their endurance/retention/reliability properties during program/erase operation would be another big challenge for the vertical NAND string architecture.

The scaling limits for 10 nm-class and sub-10 nm 2D planar NAND structures include patterning technology including QPT (Quadruple Patterning Technology), cell-to-cell interference such as cross-talk, poly-Si gap-filling process for control gate (CG), self-aligned STI (SA-STI) for isolation patterning, self-aligned process (SAP) for CG/FG, interconnection methodology including pad layout/design, inter-poly dielectric (IPD) layer engineering, and cell transistor channel/source-drain (S/D) engineering. According to TechInsights’ detailed structural analysis and comparison of 15nm and 16nm NAND flash devices (so called 1Y NAND technology node) such as Samsung 16nm, Toshiba 15nm, Micron 16nm and SK-Hynix 16nm products, we may expect that at least two more next generation 2D planar NAND products having 12nm and less than 12 nm technology would be developed and released from major players near future. As for NAND memory density and die size, Toshiba/SanDisk 15nm TLC products have 1.28 Gb/mm2 which is double from other MLC products although Samsung 32-tier 3D V-NAND TLC products have 1.87 Gb/mm2 (Figure 2).

Fig 2

Figure 2. Comparison of NAND memory density for each product (Source: TechInsights)

For patterning the three finest lines of the NAND cell structure such as active/STI, gate/wordline (CG/FG) and bitline (usually, metal-2 lines), a quadruple patterning technology (QPT) seems to be very mature for each of the major NAND players. They use their own QPT integration on three critical layers with three or four masks, SOH etching and two-step self-align reverse patterning (SARP) process. Although the critical dimensions have a little skew on every four patterns, they have successfully developed QPT integration with less than 1nm CD (Critical Dimension) and it could be extended into 10nm and even single-digit nanometer NAND products. Fortunately and thanks to state-of-the-art anisotropic plasma etching and ALD/CVD technology, uniformly repeated 8nm patterns would be possible for NAND cell array. Figure 3 shows a comparison of DPT/QPT patterns for each product.

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Micron uses a 3.3nm thin-FG poly-Si storage node to decrease cell-to-cell interference, while other manufacturers introduce an air-gap process for active, gate wordline (FG/CG) and bitline (metal-2) for thick-FG structure. Especially, the air-gap process has been developed and applied on the channel region of active patterns and FG/CG pillars help decrease the cross-talk.

For an IPD (Inter-Poly Dielectric) or a barrier layer between CG and FG, a multi-layer stacked with thin oxide (O) and nitride (N) layers such as ONO or NONON structure has been used for mid-10 nm class NAND devices, while Micron uses a high-k dielectrics such as HfO/SiO/HfO/Nitrided-SiO which is the same as their 20 nm NAND products. Micron successfully integrated IPD/FG/Tunnel-oxide and decreased FG thickness from 5 nm to 3.3 nm with high-k IPD. It might be further reduced to 10ish nm NAND products by optimizing IPD/FG quantum well structure for their unique thin-FG architecture. A 6 nm tunnel oxide (SiO) is used on Micron, Toshiba/SanDisk and SK-Hynix, while Samsung uses nitrogen-doped oxide in its top and bottom portion.

Triple-row staggered bitline contacts (BC) are used on Toshiba/SanDisk for the first time which is an excellent choice to make things smooth for cell layout and process integration although NAND string overhead is increased from 13% to 19%. Other players still use double-row staggered BC layouts on their 15nm/16nm NAND products (Figure 4).

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Other barriers to extend 2D planar NAND to 10nm such as CG poly fill-ability, anisotropic etching for SA-FG/STI and CG/FG, cell transistor S/D engineering and leaning effect during the process integration are still there. Nevertheless, major players and their equipment vendors will successfully develop and integrate the 10 nm 2D NAND architecture in a few years.

I believe most of the major NAND players have their own matured process integration capability with assistance from ECC and circuit/layout optimization. 2D NAND technology will be further scaled down to 12nm, 10nm, or even 8ish nm which is more cost-effective than 3D V-NAND for near future NAND products.

HeadshotJeongdong Choe has more than 20 years of experience on semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a consulting engineer especially focusing on memory and logic process integration.

Nano-electronics research center imec announced today that it is extending its Gallium Nitride-on-Silicon (GaN-on-Si) R&D program, and is now offering joint research on GaN-on-Si 200mm epitaxy and enhancement mode device technology. The extended R&D initiative includes exploration of novel substrates to improve the quality of the epitaxial layers, new isolation modules to increase the level of integration, and the development of advanced vertical devices. Imec welcomes new partners interested in next generation GaN technologies and companies looking for low-volume manufacturing of GaN-on-Si devices to enable the next generation of more efficient and compact power converters.

next gen GaN imec

GaN technology offers faster switching power devices with higher breakdown voltage and lower on-resistance than silicon, making it an outstanding material for advanced power electronic components. Imec’s R&D program on GaN-on-Si was launched to develop a GaN-on-Si process and bring GaN technology towards industrialization. Building on imec’s excellent track record in GaN epi-layer growth, new device concepts and CMOS device integration, imec has now developed a complete 200mm CMOS-compatible GaN process line. Imec’s GaN-on-Si technology is reaching maturity, and companies can gain access to the platform by joining imec’s GaN-on-Si industrial affiliation program (IIAP). The process line is also open to fabless companies interested in low-volume production of GaN-on-Si devices tailored to their specific needs, through dedicated development projects.

Imec’s portfolio includes three types of buffers optimized for breakdown voltage and low traps-related phenomena (i.e. current dispersion): a step graded AlGaN buffer, a super lattice buffer, and a buffer with low-temperature AlN interlayers. Imec explored side-by-side enhancement mode power devices of the MISHEMT and p-GaN HEMT type, as well as a gate-edge terminated Schottky power diode featuring low reverse leakage and low turn-on voltage.

The latest generation of imec enhancement mode power devices shows a threshold voltage beyond +2V, an on-resistance below 10 ohm mm and output current beyond 450 mA/mm. These devices represents the state of the art of enhancement mode power devices.

In this next phase of the GaN program, imec is focusing on further improving the performance and reliability of its current power devices, while in parallel pushing the boundaries of the technology through innovation in substrate technology, higher levels of integration and exploration of novel device architectures.

“Since the program’s launch in July 2009, we have benefited from strong industry engagement, including participation from IDMs, epi-vendors and equipment and material suppliers. This underscores the industrial relevance of our offering,” stated Rudi Cartuyvels, executive vice president of smart systems at imec. “Interested companies are invited to become a partner and actively participate in our program. Imec’s open innovation model allows companies to have early access to next-generation devices and power electronics processes, equipment and technologies and speed up innovation at shared cost.”

By encoding information in photons via their spin, “photonic” computers could be orders of magnitude faster and efficient than their current-day counterparts. Likewise, encoding information in the spin of electrons, rather than just their quantity, could make “spintronic” computers with similar advantages.

University of Pennsylvania engineers and physicists have now discovered a property of silicon that combines aspects of all of these desirable qualities.

In a study published in Science, they have demonstrated a silicon-based photonic device that is sensitive to the spin of the photons in a laser shined on one of its electrodes. Light that is polarized clockwise causes current to flow in one direction, while counter-clockwise polarized light makes it flow in the other direction.

This property was hiding in plain sight; it is a function of the geometric relationship between the pattern of atoms on the surface of silicon nanowires and how electrodes placed on those wires intersect them. The interaction between the semiconducting silicon and the metallic electrodes produces an electric field at an angle that breaks the mirror symmetry that silicon typically exhibits. This chiral property is what sends electrons in one direction or the other down the nanowire depending on the polarity of the light that hits the electrodes.

The study was led by Ritesh Agarwal, a professor in the Department of Materials Science and Engineering in Penn’s School of Engineering and Applied Science, and Sajal Dhara, a postdoctoral researcher in Agarwal’s lab. They collaborated with Eugene Mele, a professor in the Department of Physics and Astronomy in Penn’s School of Arts & Sciences.

“Whenever you change a symmetry, you can do new things,” said Agarwal. “In this case, we have demonstrated how to make a photodetector sensitive to a photon’s spin. All photonic computers need photodetectors, but they currently only use the quantity of photons to encode information. This sensitivity to photon spin would be an extra degree of freedom, meaning you could encode additional information on each photon.

“Typically, materials with heavy elements show this property due to their spins strongly interacting with electron’s orbital motion, but we have demonstrated this effect on the surface of silicon, originating only from the electron’s orbital motion”

Agarwal and Dhara reached out to Mele due to his work on topological insulators. He, along with fellow Penn physicist Charles Kane, laid the foundation for this new a class of materials, which are electrical insulators on their interiors but conduct electricity on their surfaces.

Agarwal’s group was working on various materials that exhibit topological effects, but as a check on their methods, Mele suggested trying their experiments with silicon as well. As a light, highly symmetric material, silicon was not thought to be able to exhibit these properties.

“We expected the control experiment to give a null result, instead we discovered something new about nanomaterials,” Mele said.

Silicon is the heart of computer industry, so finding ways of producing these types of effects in that element is preferable to learning how to work with the heavier, rarer elements that naturally exhibit them.

Once it was clear that silicon was capable of having chiral properties, the researchers set out to find out the atomic mechanisms behind it.

“The effect was coming from the surface of the nanowire,” Dhara said. “The way most silicon nanowires are grown, the atoms are bound in zigzag chains that go along the surface, not down into the wire.”

These zigzag patterns are such that placing a mirror on top of them would produce an image that could be superimposed on the original. This is why silicon is not intrinsically chiral. However, when metal electrodes are placed on the wire in the typical perpendicular fashion, they intersect the direction of the chains at a slight angle.

“When you have any metal and any semiconductor in contact, you’ll get an electric field at the interface, and it’s this field that is breaking the mirror symmetry in the silicon chains,” Dhara said.

Because the direction of the electric field does not exactly match the direction of the zigzag chains, there are angles where the silicon is asymmetric. This means it can exhibit chiral properties. Shining a circularly polarized laser at the point on the nanowire where metal and semiconductor meet produces a current, and the spin of the photons in that laser determines the direction of the current’s flow.

Dhara and Agarwal are currently working on ways to get planar silicon to exhibit these properties using the same mechanism.

Ben-Gurion University of the Negev (BGU) and University of Western Australia researchers have developed a new process to develop few-layer graphene for use in energy storage and other material applications that is faster, potentially scalable and surmounts some of the current graphene production limitations.

Graphene is a thin atomic layer of graphite (used in pencils) with numerous properties that could be valuable in a variety of applications, including medicine, electronics and energy. Discovered only 11 years ago, graphene is one of the strongest materials in the world, highly conductive, flexible, and transparent. However, current methods for production currently require toxic chemicals and lengthy and cumbersome processes that result in low yield that is not scalable for commercial applications.

The new revolutionary one-step, high-yield generation process is detailed in the latest issue of Carbon, published by a collaborative team that includes BGU Prof. Jeffrey Gordon of the Alexandre Yersin Department of Solar Energy and Environmental Physics at the Jacob Blaustein Institutes for Desert Research and Prof. H.T. Chua’s group at the University of Western Australia (UWA, Perth).

Their ultra-bright lamp-ablation method surmounts the shortcomings and has succeeded in synthesizing few-layer (4-5) graphene in higher yields. It involves a novel optical system (originally invented by BGU Profs. Daniel Feuermann and Jeffrey Gordon) that reconstitutes the immense brightness within the plasma of high-power xenon discharge lamps at a remote reactor, where a transparent tube filled with simple, inexpensive graphite is irradiated.

The process is relatively faster, safer and green — devoid of any toxic substances (just graphite plus concentrated light).

Following this proof of concept, the BGU-UWA team is now planning an experimental program to scale up this initial success toward markedly improving the volume and rate at which few-layer (and eventually single-layer) graphene can be synthesized.

Researchers at Chalmers University of Technology have developed a method for efficiently cooling electronics using graphene-based film. The film has a thermal conductivity capacity that is four times that of copper. Moreover, the graphene film is attachable to electronic components made of silicon, which favors the film’s performance compared to typical graphene characteristics shown in previous, similar experiments.

Electronic systems available today accumulate a great deal of heat, mostly due to the ever-increasing demand on functionality. Getting rid of excess heat in efficient ways is imperative to prolonging electronic lifespan, and would also lead to a considerable reduction in energy usage. According to an American study, approximately half the energy required to run computer servers, is used for cooling purposes alone.

A couple of years ago, a research team led by Johan Liu, professor at Chalmers University of Technology, were the first to show that graphene can have a cooling effect on silicon-based electronics. That was the starting point for researchers conducting research on the cooling of silicon-based electronics using graphene.

“But the methods that have been in place so far have presented the researchers with problems,” Johan Liu said. “It has become evident that those methods cannot be used to rid electronic devices off great amounts of heat, because they have consisted only of a few layers of thermal conductive atoms. When you try to add more layers of graphene, another problem arises, a problem with adhesiveness. After having increased the amount of layers, the graphene no longer will adhere to the surface, since the adhesion is held together only by weak van der Waals bonds.”

“We have now solved this problem by managing to create strong covalent bonds between the graphene film and the surface, which is an electronic component made of silicon,” he continues.

The stronger bonds result from so-called functionalization of the graphene, i.e. the addition of a property-altering molecule. Having tested several different additives, the Chalmers researchers concluded that an addition of (3-Aminopropyl) triethoxysilane (APTES) molecules has the most desired effect. When heated and put through hydrolysis, it creates so-called silane bonds between the graphene and the electronic component.

Moreover, functionalization using silane coupling doubles the thermal conductivity of the graphene. The researchers have shown that the in-plane thermal conductivity of the graphene-based film, with 20 micrometer thickness, can reach a thermal conductivity value of 1600 W/mK, which is four times that of copper.

“Increased thermal capacity could lead to several new applications for graphene,” says Johan Liu. “One example is the integration of graphene-based film into microelectronic devices and systems, such as highly efficient Light Emitting Diodes (LEDs), lasers and radio frequency components for cooling purposes. Graphene-based film could also pave the way for faster, smaller, more energy efficient, sustainable high power electronics.”