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Engineers at Oregon State University have invented a way to fabricate silver, a highly conductive metal, for printed electronics that are produced at room temperature.

There may be broad applications in microelectronics, sensors, energy devices, low emissivity coatings and even transparent displays.

A patent has been applied for on the technology, which is now available for further commercial development. The findings were reported in Journal of Materials Chemistry C.

Silver has long been considered for the advantages it offers in electronic devices. Because of its conductive properties, it is efficient and also stays cool. But manufacturers have often needed high temperatures in the processes they use to make the devices, adding to their cost and complexity, and making them unsuitable for use on some substrates, such as plastics that might melt or papers that might burn.

This advance may open the door to much wider use of silver and other conductors in electronics applications, researchers said.

“There’s a great deal of interest in printed electronics, because they’re fast, cheap, can be done in small volumes and changed easily,” said Chih-hung Chang, a professor in the OSU College of Engineering. “But the heat needed for most applications of silver nanoparticles has limited their use.”

OSU scientists have solved that problem by using a microreactor to create silver nanoparticles at room temperatures without any protective coating, and then immediately printing them onto almost any substrate with a continuous flow process.

“Because we could now use different substrates such as plastics, glass or even paper, these electronics could be flexible, very inexpensive and stable,” Chang said. “This could be quite important and allow us to use silver in many more types of electronic applications.”

Among those, he said, could be solar cells, printed circuit boards, low-emissivity coatings, or transparent electronics. A microchannel applicator used in the system will allow the creation of smaller, more complex electronics features.

Flexing graphene may be the most basic way to control its electrical properties, according to calculations by theoretical physicists at Rice University and in Russia.

The Rice lab of Boris Yakobson in collaboration with researchers in Moscow found the effect is pronounced and predictable in nanocones and should apply equally to other forms of graphene.

The researchers discovered it may be possible to access what they call an electronic flexoelectric effect in which the electronic properties of a sheet of graphene can be manipulated simply by twisting it a certain way.

The work will be of interest to those considering graphene elements in flexible touchscreens or memories that store bits by controlling electric dipole moments of carbon atoms, the researchers said.

Perfect graphene – an atom-thick sheet of carbon – is a conductor, as its atoms’ electrical charges balance each other out across the plane. But curvature in graphene compresses the electron clouds of the bonds on the concave side and stretches them on the convex side, thus altering their electric dipole moments, the characteristic that controls how polarized atoms interact with external electric fields.

The researchers who published their results this month in the American Chemical Society’s Journal of Physical Chemistry Letters discovered they could calculate the flexoelectric effect of graphene rolled into a cone of any size and length.

The researchers used density functional theory to compute dipole moments for individual atoms in a graphene lattice and then figure out their cumulative effect. They suggested their technique could be used to calculate the effect for graphene in other more complex shapes, like wrinkled sheets or distorted fullerenes, several of which they also analyzed.

“While the dipole moment is zero for flat graphene or cylindrical nanotubes, in between there is a family of cones, actually produced in laboratories, whose dipole moments are significant and scale linearly with cone length,” Yakobson said.

Carbon nanotubes, seamless cylinders of graphene, do not display a total dipole moment, he said. While not zero, the vector-induced moments cancel each other out.

That’s not so with a cone, in which the balance of positive and negative charges differ from one atom to the next, due to slightly different stresses on the bonds as the diameter changes. The researchers noted atoms along the edge also contribute electrically, but analyzing two cones docked edge-to-edge allowed them to cancel out, simplifying the calculations.

Yakobson sees potential uses for the newly found characteristic. “One possibly far-reaching characteristic is in the voltage drop across a curved sheet,” he said. “It can permit one to locally vary the work function and to engineer the band-structure stacking in bilayers or multiple layers by their bending. It may also allow the creation of partitions and cavities with varying electrochemical potential, more ‘acidic’ or ‘basic,’ depending on the curvature in the 3-D carbon architecture.”

A new route to ultrahigh density, ultracompact integrated photonic circuitry has been discovered by researchers with the Lawrence Berkeley National Laboratory (Berkeley Lab) and the University of California (UC) Berkeley. The team has developed a technique for effectively controlling pulses of light in closely packed nanoscale waveguides, an essential requirement for high-performance optical communications and chip-scale quantum computing.

Xiang Zhang, director of Berkeley Lab’s Materials Sciences Division, led a study in which a mathematical concept called “adiabatic elimination” is applied to optical nanowaveguides, the photonic versions of electronic circuits. Through the combination of coupled systems — a standard technique for controlling the movement of light through a pair of waveguides — and adiabatic elimination, Zhang and his research team are able to eliminate an inherent and vexing “crosstalk” problem for nanowaveguides that are too densely packed.

Integrated electronic circuitry is approaching its limits because of heat dissipation and power consumption issues. Photonics, in which electrical signals moving through copper wires and cables are replaced by pulses of light carrying data over optical fibers, is a highly touted alternative, able to carry greater volumes of data at faster speeds, while giving off much less heat and using far less power. However, the crosstalk problem in coupled optical nanowaveguides has been a major technological roadblock.

“When nanowaveguides in close proximity are coupled, the light in one waveguide impacts the other. This coupling becomes particularly severe when the separation is below the diffraction limit, placing a restriction on how close together the waveguides can be placed,” Zhang says. “We have experimentally demonstrated an adiabatic elimination scheme that effectively cuts off the cross-talk between them, enabling on-demand dynamical control of the coupling between two closely packed waveguides. Our approach offers an attractive route for the control of optical information in integrated nanophotonics, and provides a new way to design densely packed, power-efficient nanoscale photonic components, such as compact modulators, ultrafast optical signal routers and interconnects.”

Zhang, who also holds an appointment with the Kavli Energy NanoSciences Institute (ENSI) at Berkeley, is the corresponding author of a paper describing this research in Nature Communications. The paper is titled “Adiabatic elimination based coupling control in densely packed subwavelength waveguides.” Michael Mrejen, Haim Suchowski and Taiki Hatakeyama are the lead authors. Other authors are Chih-hui Wu, Liang Feng, Kevin O’Brien and Yuan Wang.

“A general approach to achieving active control in coupled waveguide systems is to exploit optical nonlinearities enabled by a strong control pulse,” Zhang says. “However this approach suffers from the nonlinear absorption induced by the intense control pulse as the signal and its control propagate in the same waveguide.”

Zhang and his group turned to the adiabatic elimination concept, which has a proven track record in atomic physics and other research fields. The idea behind adiabatic elimination is to decompose large dynamical systems into smaller ones by using slow versus fast dynamics.

“Picture three buckets side-by-side with the first being filled with water from a tap, the middle being fed from the first bucket though a hole while feeding the third bucket through another hole,” says co-lead author Mrejen. “If the flow rate into the middle bucket is equal to the flow rate out of it, the second bucket will not accumulate water. This, in a basic manner, is adiabatic elimination. The middle bucket allows for some indirect control on the dynamics compared to the case in which water goes directly from the first bucket to the third bucket.”

Zhang and his research group apply this concept to a coupled system of optical nanowaveguides by inserting a third waveguide in the middle of the coupled pair. Only about 200 nanometers separate each of the three waveguides, a proximity that would normally generate too much cross-talk to allow for any control over the coupled system. However, the middle waveguide operates in a “dark” mode, in the sense that it doesn’t seem to participate in the exchange of light between the two outer waveguides since it does not accumulate any light.

“Even though the dark waveguide in the middle doesn’t seem to be involved, it nonetheless influences the dynamics of the coupled system,” says co-lead author Suchowski, who is now with the Tel Aviv University. “By judiciously selecting the relative geometries of the outer and intermediate waveguides, we achieve adiabatic elimination, which in turn enables us to control the movement of light through densely packed nanowaveguides. Until now, this has been almost impossible to do.”

This research was supported by the Office of Naval Research.

The latest manufacturing, materials and production developments in semiconductor and related technologies will be featured at SEMICON West 2015 on July 14-16 at Moscone Center in San Francisco, Calif.  Semiconductor processing is at a crossroads and is changing how companies operate to be competitive. Learning about breakthrough technology and networking is essential to remain ahead of the curve.  

More than 25,000 professionals are expected, and over 600 companies will exhibit the latest in semiconductor manufacturing.  Major semiconductor manufacturers, foundry, fabless companies, equipment and materials suppliers — plus leading companies in MEMS, displays, printed/flexible electronics, PV, and other emerging technologies — attend SEMICON West.

SEMICON West will feature valuable on-exhibition floor technical sessions and programs that are included in the  $100 registration “expo pass” (registration fee increases on July 11).  Keynote events include: 

·         “Scaling the Walls of Sub-14nm Manufacturing” with panelists from Qualcomm, Stanford University, ASE and IBM, moderated by imec’s Jo de Boeck, senior VP of Corporate Technology (July 14, 9:00-10:00am)

·         “The Internet of Things and the Next Fifty Years of Moore’s Law“ by Intel’s Doug Davis, senior VP and GM of loT (July 15, 9:00am-9:45am)

TechXPOTs will provide updates in areas including test, advanced materials and processes, advanced packaging, productivity and emerging markets and technologies. TechXPOTs include:

·      What’s Next for MEMS? With speakers from ASE, CEA-Leti, EV Group, MEMS Industry Group, Silicon Valley Band of Angels, Teledyne DALSA, and Yole Developpement (July 14, 10:30am-12:30pm)

·      Automating Semiconductor Test Productivity with speakers from ASE, Optimal+, Texas Instruments, and Xcerra (July 14, 10:30am-12:30pm)

·      Materials Session: Contamination Control in the Sub-20nm Era with speakers from Entegris, Intel, JSR Micro, Matheson, and Nanometrics; moderated by Mike Corbett, Linx (July 14, 1:30pm-3:30pm)

·      Emerging Generation Memory Technology: Update on 3DNAND, MRAM, and RRAM (July 14, 1:30pm-3:40pm).

·      The Evolution of the New 200mm Fab for the Internet of Everything with speakers from Entrepix, Genmark Automation, Lam Research, Qorvo, and Surplus Global (July 15, 2:00pm-4:00pm)

·      Monetizing the IoT: Opportunities and Challenges for the Semiconductor Sector with Amkor, Cadence Design Systems, Ernst & Young, Freescale Semiconductor, and Gartner; moderated by Edward Sperling, Semiconductor Engineering (July 16, 10:30am-12:30pm)

·      The Factory of the (Near) Future: Using Industrial IoT and 3D Printing  with speakers from AirLiquide, Applied Materials, Lawrence Livermore National Laboratory, Oak Ridge National Laboratory, and Proto Cafe (July 16, 1:00pm-3:00pm) 

The Silicon Innovation Forum will be held on July 14-15.  A special exposition segment, this area will include exhibits and two days of presentations.  The first day will be a forum where start-up companies seeking investment capital will present to a panel of investors.  Open to all attendees, this session will feature exciting new technologies.  The second day will be a forum on new research. Attendees can hear presentations on advanced research from SLAC National Accelerator Laboratory, International Consortium for Advanced Manufacturing Research, SUNY Network of Excellence – Materials & Advanced Manufacturing, Novati Technologies, MIST Center, Micro/Nano Electronics Metrology at NIST, Texas State University and Georgia Tech Heat Lab. 

On July 16, University Day welcomes students and faculty to learn about the microelectronics industry, connect with industry representatives, and explore career opportunities. University Day is on the Keynote Stage (North Hall E). The agenda includes career networking, exploration forum, expo and SEMICON West tours.

For the eighth year, SEMICON West will be co-located with Intersolar North America, the leading solar technology conference and exhibition in the U.S.  Premier sponsors of SEMICON West 2015 include Applied Materials, KLA-Tencor, and Lam Research.  Register now at www.semiconwest.org.

The latest buzz in the information technology industry regards “the Internet of things” — the idea that vehicles, appliances, civil-engineering structures, manufacturing equipment, and even livestock would have their own embedded sensors that report information directly to networked servers, aiding with maintenance and the coordination of tasks.

Realizing that vision, however, will require extremely low-power sensors that can run for months without battery changes — or, even better, that can extract energy from the environment to recharge.

Last week, at the Symposia on VLSI Technology and Circuits, MIT researchers presented a new power converter chip that can harvest more than 80 percent of the energy trickling into it, even at the extremely low power levels characteristic of tiny solar cells. Previous experimental ultralow-power converters had efficiencies of only 40 or 50 percent.

Moreover, the researchers’ chip achieves those efficiency improvements while assuming additional responsibilities. Where its predecessors could use a solar cell to either charge a battery or directly power a device, this new chip can do both, and it can power the device directly from the battery.

All of those operations also share a single inductor — the chip’s main electrical component — which saves on circuit board space but increases the circuit complexity even further. Nonetheless, the chip’s power consumption remains low.

“We still want to have battery-charging capability, and we still want to provide a regulated output voltage,” says Dina Reda El-Damak, an MIT graduate student in electrical engineering and computer science and first author on the new paper. “We need to regulate the input to extract the maximum power, and we really want to do all these tasks with inductor sharing and see which operational mode is the best. And we want to do it without compromising the performance, at very limited input power levels — 10 nanowatts to 1 microwatt — for the Internet of things.”

Ups and downs

The circuit’s chief function is to regulate the voltages between the solar cell, the battery, and the device the cell is powering. If the battery operates for too long at a voltage that’s either too high or too low, for instance, its chemical reactants break down, and it loses the ability to hold a charge.

To control the current flow across their chip, El-Damak and her advisor, Anantha Chandrakasan, the Joseph F. and Nancy P. Keithley Professor in Electrical Engineering, use an inductor, which is a wire wound into a coil. When a current passes through an inductor, it generates a magnetic field, which in turn resists any change in the current.

Throwing switches in the inductor’s path causes it to alternately charge and discharge, so that the current flowing through it continuously ramps up and then drops back down to zero. Keeping a lid on the current improves the circuit’s efficiency, since the rate at which it dissipates energy as heat is proportional to the square of the current.

Once the current drops to zero, however, the switches in the inductor’s path need to be thrown immediately; otherwise, current could begin to flow through the circuit in the wrong direction, which would drastically diminish its efficiency. The complication is that the rate at which the current rises and falls depends on the voltage generated by the solar cell, which is highly variable. So the timing of the switch throws has to vary, too.

Electric hourglass

To control the switches’ timing, El-Damak and Chandrakasan use an electrical component called a capacitor, which can store electrical charge. The higher the current, the more rapidly the capacitor fills. When it’s full, the circuit stops charging the inductor.

The rate at which the current drops off, however, depends on the output voltage, whose regulation is the very purpose of the chip. Since that voltage is fixed, the variation in timing has to come from variation in capacitance. El-Damak and Chandrakasan thus equip their chip with a bank of capacitors of different sizes. As the current drops, it charges a subset of those capacitors, whose selection is determined by the solar cell’s voltage. Once again, when the capacitor fills, the switches in the inductor’s path are flipped.

National Institutes of Health (NIH) researchers and their colleagues have developed a “placenta-on-a-chip” to study the inner workings of the human placenta and its role in pregnancy. The device was designed to imitate, on a micro-level, the structure and function of the placenta and model the transfer of nutrients from mother to fetus. This prototype is one of the latest in a series of organ-on-a-chip technologies developed to accelerate biomedical advances.

The study, published online in the Journal of Maternal-Fetal & Neonatal Medicine, was conducted by an interdisciplinary team of researchers from the NIH’s Eunice Kennedy Shriver National Institute of Child Health and Human Development (NICHD), the University of Pennsylvania, Wayne State University/Detroit Medical Center, Seoul National University and Asan Medical Center in South Korea.

“We believe that this technology may be used to address questions that are difficult to answer with current placenta model systems and help enable research on pregnancy and its complications,” said Roberto Romero, M.D., chief of the NICHD’s Perinatology Research Branch and one of the study authors.

The placenta is a temporary organ that develops in pregnancy and is the major interface between mother and fetus. Among its many functions is to serve as a “crossing guard” for substances traveling between mother and fetus. The placenta helps nutrients and oxygen move to the fetus and helps waste products move away. At the same time, the placenta tries to stop harmful environmental exposures, like bacteria, viruses and certain medications, from reaching the fetus. When the placenta doesn’t function correctly, the health of both mom and baby suffers.

Researchers are trying to learn how the placenta manages all this traffic, transporting some substances and blocking others. This knowledge may one day help clinicians better assess placental health and ultimately improve pregnancy outcomes.

However, studying the placenta in humans is challenging: it is time-consuming, subject to a great deal of variability and potentially risky for the fetus. For those reasons, previous studies on placental transport have relied largely on animal models and on laboratory-grown human cells. These methods have yielded helpful information, but are limited as to how well they can mimic physiological processes in humans.

The researchers created the placenta-on-a-chip technology to address these challenges, using human cells in a structure that more closely resembles the placenta’s maternal-fetal barrier. The device consists of a semi-permeable membrane between two tiny chambers, one filled with maternal cells derived from a delivered placenta and the other filled with fetal cells derived from an umbilical cord.

After designing the structure of the model, the researchers tested its function by evaluating the transfer of glucose (a substance made by the body when converting carbohydrates to energy) from the maternal compartment to the fetal compartment. The successful transfer of glucose in the device mirrored what occurs in the body.

“The chip may allow us to do experiments more efficiently and at a lower cost than animal studies,” said Dr. Romero. “With further improvements, we hope this technology may lead to better understanding of normal placental processes and placental disorders.”

Related news: 

New ‘lab-on-a-chip’ could revolutionize early diagnosis of cancer

Single chip device to provide real-time 3-D images from inside the heart and blood vessels

Researchers from North Carolina State University have created stretchable, transparent conductors that work because of the structures’ “nano-accordion” design. The conductors could be used in a wide variety of applications, such as flexible electronics, stretchable displays or wearable sensors.

“There are no conductive, transparent and stretchable materials in nature, so we had to create one,” says Abhijeet Bagal, a Ph.D. student in mechanical and aerospace engineering at NC State and lead author of a paper describing the work.

“Our technique uses geometry to stretch brittle materials, which is inspired by springs that we see in everyday life,” Bagal says. “The only thing different is that we made it much smaller.”

The researchers begin by creating a three-dimensional polymer template on a silicon substrate. The template is shaped like a series of identical, evenly spaced rectangles. The template is coated with a layer of aluminum-doped zinc oxide, which is the conducting material, and an elastic polymer is applied to the zinc oxide. The researchers then flip the whole thing over and remove the silicon and the template.

What’s left behind is a series of symmetrical, zinc oxide ridges on an elastic substrate. Because both zinc oxide and the polymer are clear, the structure is transparent. And it is stretchable because the ridges of zinc oxide allow the structure to expand and contract, like the bellows of an accordion.

“We can also control the thickness of the zinc oxide layer, and have done extensive testing with layers ranging from 30 to 70 nanometers thick,” says Erinn Dandley, a Ph.D. student in chemical and biomolecular engineering at NC State and co-author of the paper. “This is important because the thickness of the zinc oxide affects the structure’s optical, electrical and mechanical properties.”

The 3-D templates used in the process are precisely engineered, using nanolithography, because the dimensions of each ridge directly affect the structure’s stretchability. The taller each ridge is, the more stretchable the structure. This is because the structure stretches by having the two sides of a ridge bend away from each other at the base – like a person doing a split.

The structure can be stretched repeatedly without breaking. And while there is some loss of conductivity the first time the nano-accordion is stretched, additional stretching does not affect conductivity.

“The most interesting thing for us is that this approach combines engineering with a touch of surface chemistry to precisely control the nano-accordion’s geometry, composition and, ultimately, its overall material properties,” says Chih-Hao Chang, an assistant professor of mechanical and aerospace engineering at NC State and corresponding author of the paper. “We’re now working on ways to improve the conductivity of the nano-accordion structures. And at some point we want to find a way to scale up the process.”

The researchers are also experimenting with the technique using other conductive materials to determine their usefulness in creating non-transparent, elastic conductors.

Plasma-Therm recently presented an advanced plasma processing workshop at Xidian University in Xi’an, China that was attended by researchers, students and industry representatives and featured a day-long series of presentations about plasma processing.

Workshop participants represented a range of academic disciplines and industrial concerns, with interests spanning fundamental to applied research. Attendees are actively investigating research and development in devices and structures for which plasma processing technology is often a critical step, including MEMS, waveguides, dielectric deposition, nanostructures, and many others.

Dr. Ma Xiaohua, head of the State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology and the workshop host, said, “I always believed that Plasma-Therm’s tools have good performance, and know that the company has deep experience in etching and deposition processes. I really appreciated Dr. Lishan’s presentations. Our professors and students who have studied plasma processing learned more about the technology from Dr. Lishan’s rich experience, and gained insights that will be useful in their research.

“I thought the workshop would be more of a product promotion in the beginning, but now want to say that it was not, and I highly recommend the workshop to researchers, professors, engineers, and students,” Dr. Xiaohua concluded.

Attendees commented that the workshop lectures and multimedia materials provided a thorough introduction to plasma fundamentals, as well as in-depth information about etch and deposition applications used for compound semiconductor devices such as high electron mobility transistors (HEMTs), MEMS devices, and photonic devices such as solid state lasers.

Dr. David Lishan, Principal Scientist and Director, Technical Marketing at Plasma-Therm, has presented in-depth plasma processing workshops at more than 20 institutions in the United States, Sweden, Israel, South Korea, Taiwan, Singapore, and other countries. This was the fourth workshop he has presented at institutions in China in recent months.

Dr. Lishan noted that students and industrial researchers throughout the world are eager for information about fundamental concepts as well as advanced techniques of plasma processing. “It is always interesting to see the enthusiasm for greater understanding of plasma processing across many fields of research.” He said. “Bringing researchers together to share experiences and foster collaboration through the workshop has been very rewarding.”

Phase change random access memory (PRAM) is one of the strongest candidates for next-generation nonvolatile memory for flexible and wearable electronics. In order to be used as a core memory for flexible devices, the most important issue is reducing high operating current. The effective solution is to decrease cell size in sub-micron region as in commercialized conventional PRAM. However, the scaling to nano-dimension on flexible substrates is extremely difficult due to soft nature and photolithographic limits on plastics, thus practical flexible PRAM has not been realized yet.

Low-power nonvolatile PRAM for flexible and wearable memories enabled by (a) self-assembled BCP silica nanostructures and (b) self-structured conductive filament nanoheater. CREDIT: KAIST

Low-power nonvolatile PRAM for flexible and wearable memories enabled by (a) self-assembled BCP silica nanostructures and (b) self-structured conductive filament nanoheater.
CREDIT: KAIST

Recently, a team led by Professors Keon Jae Lee and Yeon Sik Jung of the Department of Materials Science and Engineering at KAIST has developed the first flexible PRAM enabled by self-assembled block copolymer (BCP) silica nanostructures with an ultralow current operation (below one quarter of conventional PRAM without BCP) on plastic substrates. BCP is the mixture of two different polymer materials, which can easily create self-ordered arrays of sub-20nm features through simple spin-coating and plasma treatments. BCP silica nanostructures successfully lowered the contact area by localizing the volume change of phase-change materials and thus resulted in significant power reduction. Furthermore, the ultrathin silicon-based diodes were integrated with phase-change memories (PCM) to suppress the inter-cell interference, which demonstrated random access capability for flexible and wearable electronics. Their work was published in the March issue of ACS Nano: “Flexible One Diode-One Phase Change Memory Array Enabled by Block Copolymer Self-Assembly.”

Another way to achieve ultralow-powered PRAM is to utilize self-structured conductive filaments (CF) instead of the resistor-type conventional heater. The self-structured CF nanoheater originated from unipolar memristor can generate strong heat toward phase-change materials due to high current density through the nanofilament. This ground-breaking methodology shows that sub-10nm filament heater, without using expensive and non-compatible nanolithography, achieved nanoscale switching volume of phase change materials, resulted in the PCM writing current of below 20 uA, the lowest value among top-down PCM devices. This achievement was published in the June online issue of ACS Nano “Self-Structured Conductive Filament Nanoheater for Chalcogenide Phase Transition.” In addition, due to self-structured low-power technology compatible to plastics, the research team has recently succeeded in fabricating a flexible PRAM on wearable substrates.

Professor Lee said, “The demonstration of low power PRAM on plastics is one of the most important issues for next-generation wearable and flexible non-volatile memory. Our innovative and simple methodology represents the strong potential for commercializing flexible PRAM.”

In addition, he wrote a review paper regarding the nanotechnology-based electronic devices in the June online issue of Advanced Materials entitled “Performance Enhancement of Electronic and Energy Devices via Block Copolymer Self-Assembly.”

Led by Young Duck Kim, a postdoctoral research scientist in James Hone’s group at Columbia Engineering, a team of scientists from Columbia, Seoul National University (SNU), and Korea Research Institute of Standards and Science (KRISS) reported today that they have demonstrated — for the first time — an on-chip visible light source using graphene, an atomically thin and perfectly crystalline form of carbon, as a filament. They attached small strips of graphene to metal electrodes, suspended the strips above the substrate, and passed a current through the filaments to cause them to heat up. The study, “Bright visible light emission from graphene,” is published in the Advance Online Publication (AOP) on Nature Nanotechnology‘s website on June 15.

“We’ve created what is essentially the world’s thinnest light bulb,” says Hone, Wang Fon-Jen Professor of Mechanical Engineering at Columbia Engineering and co-author of the study. “This new type of ‘broadband’ light emitter can be integrated into chips and will pave the way towards the realization of atomically thin, flexible, and transparent displays, and graphene-based on-chip optical communications.”

Creating light in small structures on the surface of a chip is crucial for developing fully integrated “photonic” circuits that do with light what is now done with electric currents in semiconductor integrated circuits. Researchers have developed many approaches to do this, but have not yet been able to put the oldest and simplest artificial light source — the incandescent light bulb — onto a chip. This is primarily because light bulb filaments must be extremely hot — thousands of degrees Celsius — in order to glow in the visible range and micro-scale metal wires cannot withstand such temperatures. In addition, heat transfer from the hot filament to its surroundings is extremely efficient at the microscale, making such structures impractical and leading to damage of the surrounding chip.

By measuring the spectrum of the light emitted from the graphene, the team was able to show that the graphene was reaching temperatures of above 2500 degrees Celsius, hot enough to glow brightly.

“The visible light from atomically thin graphene is so intense that it is visible even to the naked eye, without any additional magnification,” explains Young Duck Kim, first and co-lead author on the paper and postdoctoral research scientist who works in Hone’s group at Columbia Engineering.

Interestingly, the spectrum of the emitted light showed peaks at specific wavelengths, which the team discovered was due to interference between the light emitted directly from the graphene and light reflecting off the silicon substrate and passing back through the graphene. Kim notes, “This is only possible because graphene is transparent, unlike any conventional filament, and allows us to tune the emission spectrum by changing the distance to the substrate.”

The ability of graphene to achieve such high temperatures without melting the substrate or the metal electrodes is due to another interesting property: as it heats up, graphene becomes a much poorer conductor of heat. This means that the high temperatures stay confined to a small ‘hot spot’ in the center.

“At the highest temperatures, the electron temperature is much higher than that of acoustic vibrational modes of the graphene lattice, so that less energy is needed to attain temperatures needed for visible light emission,” Myung-Ho Bae, a senior researcher at KRISS and co-lead author, observes. “These unique thermal properties allow us to heat the suspended graphene up to half of temperature of the sun, and improve efficiency 1000 times, as compared to graphene on a solid substrate.”

The team also demonstrated the scalability of their technique by realizing large-scale of arrays of chemical-vapor-deposited (CVD) graphene light emitters.

Yun Daniel Park, professor in the department of physics and astronomy at Seoul National University and co-lead author, notes that they are working with the same material that Thomas Edison used when he invented the incandescent light bulb: “Edison originally used carbon as a filament for his light bulb and here we are going back to the same element, but using it in its pure form — graphene — and at its ultimate size limit — one atom thick.”

The group is currently working to further characterize the performance of these devices — for example, how fast they can be turned on and off to create “bits” for optical communications — and to develop techniques for integrating them into flexible substrates.

Hone adds, “We are just starting to dream about other uses for these structures — for example, as micro-hotplates that can be heated to thousands of degrees in a fraction of a second to study high-temperature chemical reactions or catalysis.”