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Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

Shipments this year for wireless semiconductors in health and fitness will reach a projected 61.2 million units, up 11 percent from 55.0 million in 2013. The expected strong expansion for this year continues the robust growth of 2012 and 2013. And the market shows little signs of slowing, with shipments in 2018 climbing to 95.78 million units, as shown in the attached figure.

Wireless_Semiconductor_Shipments_JPEG

The overall health and fitness market covered by the forecast includes the sports and fitness segment on the one hand, as well as the adjacent market for health and wellness on the other. While overlaps exist between the two segments, there are also subtle differences.

For instance, data and activity sharing by wireless means is more common in sports and fitness as consumers happily disclose the results of their improving fitness levels. In contrast, sharing is not as widespread in health and wellness, where disease management is largely private and carefully guarded by the affected individuals.

Bluetooth Smart is leader of the pack

Yet the fitness market as a whole is particularly receptive to wireless connectivity.

“Because most health and fitness devices are mobile, wireless connectivity is important,” said Lee Ratliff, principal analyst for connectivity at IHS. “And because these wireless mobile devices are in most cases also wearable and thus require a small form-factor, they cannot be power hogs and must support low-energy consumption to have the best chance of succeeding in the consumer market.”

Wireless connectivity mainly serves two purposes, Ratliff noted. Especially in sports and fitness applications, wireless connectivity is often used to provide a link to remote sensors when wired connectivity is too cumbersome. Examples here include linking heart-rate chest straps to wrist-worn heart-rate monitors, or linking wheel-speed sensors to cycling computers.

A second use is for data uploading, with wireless connectivity employed to upload fitness and performance data to PCs, smartphones, tablets or online communities for analysis and sharing.

Among the various wireless technologies now available on the market for health and fitness, Bluetooth Smart is the most successful. As a low-power technology, Bluetooth Smart enables even the smallest wearable products—such as foot pods, the size of one’s thumbnail—to operate for years on a battery the size of a coin cell. Bluetooth Smart also leverages its enviable position in mobile phones and tablets: It is the only major low-power wireless technology able to communicate with all the chief mobile platforms, including Apple iOs, Google Android, Microsoft Windows 8 and the BlackBerry operating system.

Moreover, the dongle-free connectivity of Bluetooth Smart gives it an edge over other rivals. No other technology features both low-power consumption as well as seamless connectivity, Ratliff said.

One wireless technology specifically designed for the health and fitness market and popular with heart-rate monitors, ANT/ANT+, is a low-power technology that, however, does not enjoy the same broad support in mobile platforms. A PC or dongle is also required for ANT/ANT+, unlike Bluetooth Smart. Still, ANT/ANT+ enjoys a significant market share and seems to have a defensible position, especially in products designed for serious fitness enthusiasts and in cycling electronics.

Keen consumers help spur market

A big driver of growth in health and fitness devices is the desire among consumers to track and analyze personal data, in pursuit of what is known in industry circles as “the quantified self.” Consumers can then share such data via social media and online communities, often via apps like RunKeeper of Runtastic.

Other drivers for the market include the increased use of wearable devices; decreasing component costs; an aging demographic concerned about preserving health; and the rising use of telehealth, or remote healthcare systems.

Shipments of consumer health and fitness devices with integrated wireless connectivity will grow to an estimated 75.7 million units in 2018, up from 23.0 million units in 2011.

These findings are available in the report, “Low-Power Wireless Market Tracker – Q2 2014,” from the Information Technology service of IHS.

New approaches to start-ups can unlock mega-trend opportunities.

BY MIKE NOONEN, Silicon Catalyst, San Jose, CA; SCOTT JONES and NORD SAMUELSON, AlixPartners, San Francisco, CA

The semiconductor industry returned growth and reached record revenues in 2013, breaking $300 billion for the first time after the industry had contracted in 2011 and 2012 (FIGURE 1).

FIGURE 1. Worldwide semiconductor revenue. Source: World Semiconductor Trade Statistics, February 2014.

FIGURE 1. Worldwide semiconductor revenue. Source: World Semiconductor Trade Statistics, February 2014.

However, even with that return to growth, underlying trends in the semiconductor industry are disturbing: The semiconductor cycle continues its gyrations, but overall growth is slowing. And despite 5% year-on-year revenue growth in 2013 (the highest since 2010), the expectation is that semiconductor growth will likely continue to be at a rate below its long-term trend of 8 to 10% for the next three to five years (FIGURE 2). An AlixPartners 2014 publication , Cashing In with Chips, showed that semiconductor industry growth had slowed to roughly half of its long-term growth average since the 2010 recovery—with no expectation that it will return to historical growth until at least 2017. Other studies have also shownthat semiconductor growth has slowed not only relative to its previous performance but also versus growth in other industries. And a study conducted by New York University’s Stern School of Business[1] found that the semiconductor industry’s revenue growth lagged the average revenue growth of all industries and ranked 60th out of 94 industries surveyed. Surprisingly, the industry’s net income growth of semiconductor companies lagged even further behind—ranking 84th out of 94 companies surveyed—and had actually been negative during the previous five years.

FIGURE 2. Semiconductor revenue growth. Sources: Semiconductor Industry Association and AlixPartners research.

FIGURE 2. Semiconductor revenue growth. Sources: Semiconductor Industry Association and AlixPartners research.

In another study released by AlixPartners that looked at a broader picture of the semiconductor value chain, including areas such as equipment suppliers and packaging and test companies, the research showed that outside of the top 5 companies, the remainder of the 186 companies surveyed had declining earnings before interest, taxes, depreciation, and amortization (FIGURE 3).

FIGURE 3. Spotlight on the top five (fiscal year 2012). Source: AlixPartners Research.

FIGURE 3. Spotlight on the top five (fiscal year 2012). Source: AlixPartners Research.

As revenue growth slows, costs increase at a rapid rate

As semiconductor technology advances, the cost of developing a system on chip (SoC) has risen dramatically for leading-edge process technologies. Semico Research has estimated that the total cost of an SoC development, design, intellectual property (IP) procurement, software, testing has tripled from 40/45 nanometers (nm) to 20 nm and could exceed $250 million for future 10-nm designs(FIGURE 4) [2]. This does not bode well for an economic progression of Moore’s law, and it means that very few applications will have the volume and pricing power to afford such outlandish investment. If we assume that a 28nm SoC can achieve a 20% market share and 50% gross margins, the end market would have to be worth over $1 billion to recoup R&D costs of $100 million. By 10 nm, end markets would have to result in more than $2.5 billion to recoup projected development costs. With few end markets capable of supporting that high a level of development costs, the number of companies willing to invest in SoCs on the leading edge will likely decline significantly each generation.

FIGURE 4. Development Costs are Skyrocketing. Source: Semico Research Corp.

FIGURE 4. Development Costs are Skyrocketing. Source: Semico Research Corp.

What happened to semiconductor start- ups?

The history of the semiconductor industry has been shaped by the semiconductor start-up. Going back to Fairchild, the start-up has been the driving force for growth and innovation. Start-ups helped shape the industry, and they are now some of the largest and most successful companies in the industry. But the environment that lasted from the 1960s until the early 2000s—and that made the success of those companies possible—has changed dramatically. The number of venture capital investments in new semiconductor start-ups in the United States has fallen dramatically, from 50 per year to the low single digits (FIGURE 5). And even though that drop is not as dramatic in other countries — such as China and Israel — it is indicative of an overall lack of investment in semiconductors.

FIGURE 5. Number of seed/series a deals. Source: Global Semiconductor Alliance.

FIGURE 5. Number of seed/series a deals. Source: Global Semiconductor Alliance.

The main reason for the decline is the attractiveness of other businesses for the same investment. In the fourth quarter of 2013, nearly 400 software start-ups received almost $3 billion of funding, whereas only 25 semiconductor start-ups received just $178 million (representing all stages) (FIGURE 6). It seems that (1) the lower cost of starting a software company, (2) the relatively short time frame to realize revenue, and (3) attractive initial-public-offering and acquisition markets possibly make the software start-up segment more interesting than semiconductors.

FIGURE 6. Funding of software and semiconductor start- ups. Source: PwC, US Investments by Industry/Q4 2013.

FIGURE 6. Funding of software and semiconductor start- ups. Source: PwC, US Investments by Industry/Q4 2013.

This situation is unfortunate and has conspired to create a vicious and downward cycle (FIGURE 7).

  • Lack of investment limits start-ups
  • Lack of start-ups limits innovation
  • Lack of innovation and fewer start-ups limits the number of potential acquisition targets for established companies.
  • Reduced potential acquisition targets in turn limit returns for companies and returns for those who would have invested in start-ups.
  • Limited returns make future investments less likely and continue the cycle of less innovation and lower investment [3]. 
FIGURE 7. A vicious cycle limits innovation.

FIGURE 7. A vicious cycle limits innovation.

Therefore, it is reasonable to conclude that the demise of semiconductor start-ups is a contributing cause to the lackluster results of the overall semiconductor industry. And that demise and those lackluster results are further exacerbated by the rise of activist shareholders who demand a more rapid return on their investment, which possibly reduces the potential for innovation in an industry that has lengthy development cycles.

What about other industries?

It is tempting to think that the semiconductor industry is alone in this predicament, but other industries face similar challenges and have figured out accretive paths forward. For example, biotechnology has some of the same issues:

  • An industry that grows by bringing innovation to market 
  • Similarly lengthy development cycles 
  • Potentially capital intensive at the research and production stages

In addition, the biotech industry faces a challenge the semiconductor world does not — namely, the need for government regulatory approval before moving to production and then volume sales. Gaining that regulatory approval is a go-to-market hurdle that can add years and uncertainty to a product cycle.

However, in spite of its similarities to the semiconductor business and the added regulatory hurdles, the biotech industry enjoys a very healthy venture-funding and start-up environment. In fact, in the fourth quarter of 2013 in the United States, biotech was the second-largest business sector for venture funding in both dollars and total number of deals (FIGURE 8).

FIGURE 8. Funding of software and semiconductor start- ups. Source: PwC, US Investments by Industry/Q4 2013.

FIGURE 8. Funding of software and semiconductor start- ups. Source: PwC, US Investments by Industry/Q4 2013.

Why is this? What do biotech executives, entre- preneurs, and investors know that the semiconductor industry can take advantage of? There are several lessons to be learned.

  • Big biotech companies have made investing, cultivating, and acquiring start-ups key parts of their innovation and product development processes. 
  • Biotech and venture investors identify interesting problems to solve and then match the problems to skilled and passionate entrepreneurs to solve them.
  • Those entrepreneurs are motivated to create and develop solutions much faster and usually more frugally than if they were working inside a large company.
  • The entrepreneurs and investors are creating businesses to be acquired versus creating businesses that will rival major industry players.
  • The acquiring companies apply their manufacturing economies of scale and well-estab- lished sales and marketing strategies to rapidly— and profitably—bring the newly acquired solutions to market.

For several reasons, certain megatrends are driving the high-technology sector and the economy as a whole, and all of them are enabled by semiconductor innovation (FIGURE 9). Among the major trends:

  • Mobile computing will likely continue to merge functions and drive computing power.
  • Security concerns appear to be increasing at all levels: government, enterprise, and personal.
  • Cloud computing will possibly cause an upheaval in information technology.
  • Personalization through technology and logistics appears to be on the rise.
  • Energy efficiency is likely need for sustainability and lower cost of ownership.
  • Next generation wireless will likely be driven by insatiable coverage and bandwidth needs.
  • The Internet of things will likely lead to mobile processing at low power with ubiquitous radio frequency.
FIGURE 9. Global internet device installed base forecast. Sources: Gartner, IDC, Strategy Analytics, Machina Research, company filings, BII estimates.

FIGURE 9. Global internet device installed base forecast. Sources: Gartner, IDC, Strategy Analytics, Machina Research, company filings, BII estimates.

The Internet of Things megatrend alone will result in a tremendous amount of new semiconductor innovation that in turn will likely lead to volume markets. Cisco Systems CEO John Chambers has predicted a $19-trillion market by 2020 resulting from Internet of Things applications [4].

Does it really cost $100 million to start a semiconductor company?

The prevailing conventional wisdom is that it takes $100 million to start a new semiconductor company, and in some cases that covers only the cost of a silicon development. It is true that recently, several companies have spent eight- or nine-figure sums of money to develop their products, but those are very much exceptions. The reality is that most semiconductor development is not at the bleeding edge, nor is the development of billion-transistor SoCs.

The majority of design starts in 2013 were in .13 μm, and this year, 65, 55, 45, and 40nm are all growing (FIGURE 10). These technologies are becoming very affordable as they mature. And costs will likely continue to decrease as more capacity becomes available once new companies enter the foundry business and as former DRAM vendors in Taiwan and new fab in China come online.

FIGURE 10: .13um has the most design starts; 65nm and 45nm have yet to peak.

FIGURE 10: .13um has the most design starts; 65nm and 45nm have yet to peak.

Another thing to consider is whether a new company would sell solutions that use existing technology or platforms (i.e., a chipless start-up) or whether a company would choose to originate IP that enables functionality for incorporation into another integrated circuit.

A chipless start-up would add value to an existing architecture or platform. It could be an algorithm or an application-specific solution on, say, a field-programmable gate array, a microcontroller unit or an application-specific standard product. It could also be service based on an existing hardware platform.

A company developing innovative new functionality for inclusion into another SoC paves a path to getting to revenue quickly. Such IP solution providers would supply functionality for integration not only into a larger SoC but also into the emerging market for 2.5-D and 3-D applications.

In both situations (the chipless start-up and the IP provider), significant cost may be avoided by the use of existing technology or the absence of the need to build infrastructure or capabilities already provided by partners. In addition, those paths have much faster times to revenue as well as inherently lower burn rates, which are conducive to higher returns for investors.

Even for start-ups that intend to develop leading-edge multicore SoCs, a $100-million investment is not inevitable. Take, for example, Adapteva, an innovative start-up in Lexington, Massachusetts. Founded by Andreas Olofsson, Adapteva has developed a 64-core parallel processing solution in 28 nm. The processor is the highest gigaflops/watt solution available today, beating solutions from much larger and more-established companies. However, Adapteva has raised only about $5 million to date, a good portion of which funding was crowd sourced on the Kickstarter Web site. This just shows that even a leading-edge multicore SoC can be developed cost-effectively—and effectively—through the use of multiproject wafers and other frugal methods.

Several conclusions can be drawn at this point.

  • Even though the semiconductor industry is growing again, the underlying trends for profitability and growth are not encouraging. 
  • Cost development is increasingly rapid on leading-edge SoCs. 
  • Historically, start-ups have been engines of innovation of growth and innovation for semiconductors. 
  • In recent years, venture funding for new semiconductor companies has almost completely dried up. 
  • That lack of investment of semiconductor start-ups has contributed to a downward and vicious cycle that will further erode the economics of semiconductor companies. 
  • The biotechnology industry has many parallels to the semiconductor. Interestingly, biotechnology has a relatively thriving venture funding and start-up environment, and we can apply that industry’s successful approach to semiconductors. 
  • Despite the state of start-ups, it is now one of the most exciting times to be in semiconductors because most of the megatrends driving the economy are either enabled by or dependent on semiconductor innovation. 
  • It does not need to take $100 million to start the typical semiconductor company, because a great deal of innovation will use very affordable technologies, and come from chipless start-ups or IP providers that have much lower burn rates and ties to revenue.
  • Even leading-edge multicore SoCs can be developed frugally (for single-digit millions of dollars) and profitably. 

References

1. http://people.stern.nyu.edu/adamodar/New_Home_ Page/datafile/histgr.html

2. SoC Silicon and Software Design Cost Analysis: Costs for Higher Complexity Continue to Rise SC102-13 May 2013.

3. AlixPartners and Silicon Catalyst analysis and experi- ence.

4. Cisco Systems public statements.

IBM announced it is investing $3 billion over the next 5 years in two broad research and early stage development programs to push the limits of chip technology needed to meet the emerging demands of cloud computing and Big Data systems. These investments will push IBM’s semiconductor innovations from today’s breakthroughs into the advanced technology leadership required for the future.

The first research program is aimed at so-called “7 nanometer and beyond” silicon technology that will address serious physical challenges that are threatening current semiconductor scaling techniques and will impede the ability to manufacture such chips. The second is focused on developing alternative technologies for post-silicon era chips using entirely different approaches, which IBM scientists and other experts say are required because of the physical limitations of silicon based semiconductors.

Cloud and big data applications are placing new challenges on systems, just as the underlying chip technology is facing numerous significant physical scaling limits.  Bandwidth to memory, high speed communication and device power consumption are becoming increasingly challenging and critical.

The teams will comprise IBM Research scientists and engineers from Albany and Yorktown, New York; Almaden, California; and Europe. In particular, IBM will be investing significantly in emerging areas of research that are already underway at IBM such as carbon nanoelectronics, silicon photonics, new memory technologies, and architectures that support quantum and cognitive computing.

These teams will focus on providing orders of magnitude improvement in system level performance and energy efficient computing. In addition, IBM will continue to invest in the nanosciences and quantum computing–two areas of fundamental science where IBM has remained a pioneer for over three decades.

7 nanometer technology and beyond
IBM Researchers and other semiconductor experts predict that while challenging, semiconductors show promise to scale from today’s 22 nanometers down to 14 and then 10 nanometers in the next several years.  However, scaling to 7 nanometers and perhaps below, by the end of the decade will require significant investment and innovation in semiconductor architectures as well as invention of new tools and techniques for manufacturing.

“The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?” said John Kelly, senior vice president, IBM Research. “IBM engineers and scientists, along with our partners, are well suited for this challenge and are already working on the materials science and device engineering required to meet the demands of the emerging system requirements for cloud, big data, and cognitive systems. This new investment will ensure that we produce the necessary innovations to meet these challenges.”

“Scaling to 7nm and below is a terrific challenge, calling for deep physics competencies in processing nano materials affinities and characteristics. IBM is one of a very few companies who has repeatedly demonstrated this level of science and engineering expertise,” said Richard Doherty, technology research director, The Envisioneering Group.

Bridge to a “Post-Silicon” Era
Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. Their increasingly small dimensions, now reaching the nanoscale, will prohibit any gains in performance due to the nature of silicon and the laws of physics. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost and higher speed processors that the industry has become accustomed to.

With virtually all electronic equipment today built on complementary metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scalability limits of the silicon transistor.

Beyond 7 nanometers, the challenges dramatically increase, requiring a new kind of material to power systems of the future, and new computing platforms to solve problems that are unsolvable or difficult to solve today. Potential alternatives include new materials such as carbon nanotubes, and non-traditional computational approaches such as neuromorphic computing, cognitive computing, machine learning techniques, and the science behind quantum computing.

As the leader in advanced schemes that point beyond traditional silicon-based computing, IBM holds over 500 patents for technologies that will drive advancements at 7nm and beyond silicon — more than twice the nearest competitor. These continued investments will accelerate the invention and introduction into product development for IBM’s highly differentiated computing systems for cloud, and big data analytics.

Several exploratory research breakthroughs that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips, include quantum computing, neurosynaptic computing, silicon photonics, carbon nanotubes, III-V technologies, low power transistors and graphene:

Quantum Computing
The most basic piece of information that a typical computer understands is a bit. Much like a light that can be switched on or off, a bit can have only one of two values: “1” or “0.” Described as superposition, this special property of qubits enables quantum computers to weed through millions of solutions all at once, while desktop PCs would have to consider them one at a time.

IBM is a world leader in superconducting qubit-based quantum computing science and is a pioneer in the field of experimental and theoretical quantum information, fields that are still in the category of fundamental science – but one that, in the long term, may allow the solution of problems that are today either impossible or impractical to solve using conventional machines. The team recently demonstrated the first experimental realization of parity check with three superconducting qubits, an essential building block for one type of quantum computer.

Neurosynaptic Computing
Bringing together nanoscience, neuroscience, and supercomputing, IBM and university partners have developed an end-to-end ecosystem including a novel non-von Neumann architecture, a new programming language, as well as applications. This novel technology allows for computing systems that emulate the brain’s computing efficiency, size and power usage. IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons and a hundred trillion synapses, all while consuming only one kilowatt of power and occupying less than two liters of volume.

Silicon Photonics
IBM has been a pioneer in the area of CMOS integrated silicon photonics for over 12 years, a technology that integrates functions for optical communications on a silicon chip, and the IBM team has recently designed and fabricated the world’s first monolithic silicon photonics based transceiver with wavelength division multiplexing.  Such transceivers will use light to transmit data between different components in a computing system at high data rates, low cost, and in an energetically efficient manner.

Silicon nanophotonics takes advantage of pulses of light for communication rather than traditional copper wiring and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

Businesses are entering a new era of computing that requires systems to process and analyze, in real-time, huge volumes of information known as Big Data. Silicon nanophotonics technology provides answers to Big Data challenges by seamlessly connecting various parts of large systems, whether few centimeters or few kilometers apart from each other, and move terabytes of data via pulses of light through optical fibers.

III-V technologies
IBM researchers have demonstrated the world’s highest transconductance on a self-aligned III-V channel metal-oxide semiconductor (MOS) field-effect transistors (FETs) device structure that is compatible with CMOS scaling. These materials and structural innovation are expected to pave path for technology scaling at 7nm and beyond.  With more than an order of magnitude higher electron mobility than silicon, integrating III-V materials into CMOS enables higher performance at lower power density, allowing for an extension to power/performance scaling to meet the demands of cloud computing and big data systems.

Carbon Nanotubes
IBM Researchers are working in the area of carbon nanotube (CNT) electronics and exploring whether CNTs can replace silicon beyond the 7 nm node.  As part of its activities for developing carbon nanotube based CMOS VLSI circuits, IBM recently demonstrated — for the first time in the world — 2-way CMOS NAND gates using 50 nm gate length carbon nanotube transistors.

IBM also has demonstrated the capability for purifying carbon nanotubes to 99.99 percent, the highest (verified) purities demonstrated to date, and transistors at 10 nm channel length that show no degradation due to scaling–this is unmatched by any other material system to date.

Carbon nanotubes are single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device that will work in a fashion similar to the current silicon transistor, but will be better performing. They could be used to replace the transistors in chips that power data-crunching servers, high performing computers and ultra fast smart phones.

Carbon nanotube transistors can operate as excellent switches at molecular dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of the leading silicon technology. Comprehensive modeling of the electronic circuits suggests that about a five to ten times improvement in performance compared to silicon circuits is possible.

Graphene
Graphene is pure carbon in the form of a one atomic layer thick sheet.  It is an excellent conductor of heat and electricity, and it is also remarkably strong and flexible.  Electrons can move in graphene about ten times faster than in commonly used semiconductor materials such as silicon and silicon germanium. Its characteristics offer the possibility to build faster switching transistors than are possible with conventional semiconductors, particularly for applications in the handheld wireless communications business where it will be a more efficient switch than those currently used.

Recently in 2013, IBM demonstrated the world’s first graphene based integrated circuit receiver front end for wireless communications. The circuit consisted of a 2-stage amplifier and a down converter operating at 4.3 GHz.

Next Generation Low Power Transistors
In addition to new materials like CNTs, new architectures and innovative device concepts are required to boost future system performance. Power dissipation is a fundamental challenge for nanoelectronic circuits. To explain the challenge, consider a leaky water faucet — even after closing the valve as far as possible water continues to drip — this is similar to today’s transistor, in that energy is constantly “leaking” or being lost or wasted in the off-state.

A potential alternative to today’s power hungry silicon field effect transistors are so-called steep slope devices. They could operate at much lower voltage and thus dissipate significantly less power. IBM scientists are researching tunnel field effect transistors (TFETs). In this special type of transistors the quantum-mechanical effect of band-to-band tunneling is used to drive the current flow through the transistor. TFETs could achieve a 100-fold power reduction over complementary CMOS transistors, so integrating TFETs with CMOS technology could improve low-power integrated circuits.

Recently, IBM has developed a novel method to integrate III-V nanowires and heterostructures directly on standard silicon substrates and built the first ever InAs/Si tunnel diodes and TFETs using InAs as source and Si as channel with wrap-around gate as steep slope device for low power consumption applications.

“In the next ten years computing hardware systems will be fundamentally different as our scientists and engineers push the limits of semiconductor innovations to explore the post-silicon future,” said Tom Rosamilia, senior vice president, IBM Systems and Technology Group. “IBM Research and Development teams are creating breakthrough innovations that will fuel the next era of computing systems.”

IBM’s contributions to silicon and semiconductor innovation include the invention and/or first implementation of: the single cell DRAM, the “Dennard scaling laws” underpinning “Moore’s Law”, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed silicon germanium (SiGe), High-k gate dielectrics, embedded DRAM, 3D chip stacking, and Air gap insulators.

IBM researchers also are credited with initiating the era of nano devices following the Nobel prize winning invention of the scanning tunneling microscope which enabled nano and atomic scale invention and innovation.

IBM will also continue to fund and collaborate with university researchers to explore and develop the future technologies for the semiconductor industry. In particular, IBM will continue to support and fund university research through private-public partnerships such as the NanoElectornics Research Initiative (NRI), and the Semiconductor Advanced Research Network (STARnet), and the Global Research Consortium (GRC) of the Semiconductor Research Corporation.

Berger Pierre-DamienBy Pierre-Damien Berger, VP Business Development & Communication; CEA-Leti

Whatever forecast one uses for the future of the Internet of Things in terms of connected objects or business opportunities, the IoT will be big. Citing industry sources during of “The Internet of Things: from sensors to zero power,” the recent LetiDays conference in Grenoble, France, speakers offered projections venturing up to 50 billion connected objects by 2020.

Jacques Husser, COO of SIGFOX, said the IoT is the next major technological revolution, and that connecting billions or trillions of devices and enabling them to communicate with each other and will require more than high bandwidth. While increasing bandwidth is a key focus for multi-media and voice data network operators, for IoT companies reducing energy consumption and costs are key to handling the continuous volume of small messages from all those things.

SIGFOX, whose network is dedicated to the IoT, provides power-efficient, two-way wireless connectivity for IoT and machine-to-machine communications. Husser said the company’s technology is compatible with existing chipsets from vendors such as Texas Instruments, STMicroelectronics, Silicon Labs, Atmel, NXP and Semtech. Husser said that while SIGFOX’s technology complements 2G, 3G and 4G systems, it does not require a SIM card. Devices’ IP addresses are established during manufacturing.

The company, which has networks operating or in rollout with partners in several countries and major cities, is enabling applications for building and vehicle security, indoor climate monitoring, pet tracking, smart-city apps for parking and lighting management, asset management including billboard monitoring, water utility metering, and health-care apps like fall detection, distress signaling and medicine dispensing. Many more are expected.

Leti’s RF design and antenna expertise were used to help connect SIGFOX’s cellular networks. In addition, Leti is working with other startups and SMEs to develop and connect smart functions in a variety of products that will use the IoT to communicate. Primo1D was spun out of Leti in 2013 to produce E-Thread®, an innovative microelectronic packaging technology that embeds LEDs, RFIDs or sensors in fabric and materials for integration in textiles and plastics using standard production tools.

Leti startup BeSpoon recently launched SpoonPhone, a smartphone equipped with the capability to locate tagged items within a few centimeters’ accuracy. The capability is enabled by an impulse radio ultra-wideband (IR-UWB) integrated circuit developed by Leti and BeSpoon. Leti and Cityzen Sciences, the award-winning designer and developer of smart-sensing products, have begun a project to take the company’s technology to the next level by integrating micro-sensors in textiles during the weaving stage.

Leti and CORIMA, a leading supplier of carbon-composite wheels and frames for track and road-racing cyclists, are developing an integrated sensor system to measure the power output of riders as they pedal.

Citing research by Morgan Stanley Research, Leti’s telecommunications department head Dominique Noguet noted that worldwide shipments of smartphones and tablets exceeded shipments of desktop and notebook PCs for the first time in 2011. This signaled that the web has gone mobile, a fact underscored by a Cisco forecast that M2M mobile data traffic will increase 24x from 24 petabytes per month in 2012 to 563 petabytes in 2017.

Noguet said the IoT growth will present scaling challenges and require new communication protocols for sporadic, asynchronous, decentralized, low-power traffic. In addition to harvesting, or scavenging, energy to assure continuous connectivity, there will be demand for technologies that enable spectrum scavenging in unlicensed spectra, for example, and that use new bands, such as millimeter wave, white spaces and even light.

Leti has numerous ways to support development of the IoT, ranging from embedding antennas in specific materials through characterization and design, to implementing full-blown custom radio technologies. The inclusion of UHF RFID tags for the tire industry was cited as a first example where read/write range performances were a challenge. Leti’s ultra-wideband localization technology is another example where competence in signal processing, real-time design, antenna technology and mixed RF/digital ASIC design was combined to provide a complete solution where no off-the-shelf approach was available.

Noguet also noted potential threats to IoT security, and cited Leti’s involvement in the Santander, Spain, smart city project, which includes experimental advanced research on IoT technologies. Leti and CEA-List were in charge of securing access to the SmartSantander infrastructure and communications over a wireless sensor network. This included ensuring the security of the transactions and protecting users’ privacy.

By David Holden

Cars that can get along without drivers are coming, down the road, but they are a small part of the changes that the global transportation industries will undertake as microelectronics and the Internet of Things prompt major changes in infrastructure and logistics, as well as all type of vehicles.

Speakers at the opening session of “The Internet of Things: from sensors to zero power,” a LetiDays conference in Grenoble, France, shared their near-term forecasts for transport and the multiple opportunities that will stem from these changes.

Vincent Roger, transport business development manager at CEA-Leti explained that Leti-designed autonomous sensors allow monitoring of wear and tear on roads and train tracks, which enables their owners to predict when maintenance will be required. An emerging, potentially disruptive result of the IoT and sensors that monitor activity is a pay-per-use business model, in which owners pay manufacturers for the actual use of equipment rather than purchasing it.

 

Even automakers may move toward a service-based business model, and away from just car manufacturing, said Matt Hatton, director at Machina Research.

 

Presenters agreed that privacy concerns, based on devices tracking movement and activity of consumers, may be a barrier to rapid adoption of IoT applications. But Gilles Le Calvez of Valeo said that as they increasingly understand the benefits of connectivity, consumers will accept it more. He also showed a video of a driverless Valeo automated vehicle equipped with sensors and other microelectronics that is able locate and pull into open parking spaces.

 

Roger explained a new Leti “morpho” technology, using piezoelectric elements, that can be used for IoT applications that provide structural-health monitoring (SHM) for railways, bridges and pipes or cables buried or hidden inside tunnels.

 

Leti’s MEMS-based SHM systems enable real-time and remote monitoring, including tracking the infrastructure response to storms and other events, and the changes over time. These SHM systems include sensors networks, embedded signal processing and optimization of power consumption.

Several speakers emphasized the importance of controlling power consumption of the billions of devices that are projected to be connected to the IoT in the next decade. Leti CEO Laurent Malier said the power, performance and cost advantages of Fully Depleted Silicon-on-Insulator (FD-SOI) devices are well suited to power IoT applications because of the technology’s high-performance and low power consumption features. Leti and STMicroelectronics recently demonstrated an ultra-wide-voltage range (UWVR) digital signal processor (DSP) that provides up to 50 percent lower power consumption than competing technologies.

David Holden is Cooperative Programs Manager at CEA-Leti

By Pierre-Damien Berger, vice president of business development and communication

Industries ranging from chemicals to agri-food to bio-tech and pharmaceuticals are looking at new sensor technologies to streamline processes and improve quality control. By customizing sensors for specific applications, CEA-Leti designers are developing inline process-measurement systems that can dramatically improve both quality control and productivity, and meet regulatory requirements, particularly in the pharma industry.

Speaking at the annual LetiDays event last week in Grenoble, France, Claude Vauchier, Leti lab-on-chip program manager, said such process-control systems allow quality control of raw materials and final products, identify critical process parameters for product quality, offer a process-measurement system for in-line or on-line monitoring and include a control system that can adjust critical quality attributes.

Based on components from Leti’s toolbox, the systems can use enzymatic sensors, electro-chemical sensors for ionic species detection, conductivity sensors or various optical sensors.

Vauchier described a promising new market for process monitoring based on lensfree imaging, a unique opportunity for companies to implement a technological breakthrough in optical imaging.

Developed by Leti in 2009, the technique provides multi-scale observation capability across two orders of magnitude, allowing researchers to differentiate between tissues and cells, and bacteria and viruses. The lensfree optical imaging system is much smaller than standard microscopes, and less expensive because it is made of low-cost components.

The sensors in the system do not come in contact with the media, but nonetheless can control it, including measuring concentration, distribution or morphology of different biological objects. That is a unique and cost-saving feature of the technology, Vauchier said.

The technique generates holographic images of micro-particles, cells, viruses or bacteria by employing a light-emitting diode to illuminate objects, and a standard CMOS digital sensor to capture their image. Raw images are treated with specific algorithms, so results are available instantaneously on a computer. The process has an extremely large field of view (24mm2), allowing simultaneous observation of thousands of organisms.

Vauchier said Leti is collaborating with the startup Iprasense to develop a process-control system for cell cultures in bio-production. Bioproduction is used in the fields of biopharmaceuticals, food manufacturing, cosmetics, and biofuels, as well as in bio-industries that produce enzymes, flavors, organic acids, antibiotics, vitamins or organic polymers.

The company is targeting applications for monitoring, counting and characterizing cells cultivated in incubators and bioreactors as part of the bioproduction process.

Its first product, expected by year-end, will be a smart instrument for cell culture monitoring in a flask, a petri dish, or a microtiter plate, in bioreactors. It will not only capture every moment of the cell culture, but also will instantly analyze the live recording to give researchers real-time information on cell numbers and confluence, or how well the cells have generated an even layer across a cell-culture flask.

LetiDaysBLog

memsstar Limited, a provider of etch and deposition equipment and technology solutions to manufacturers of semiconductors and micro-electrical mechanical systems (MEMS), today announced that it has relocated to a new, larger facility. The move represents a strategic investment in its business, to ensure the company’s ability to meet growing demand for its proprietary MEMS equipment and fully remanufactured semiconductor etch and deposition equipment.

“This move positions memsstar extremely well to support the rapidly growing European semiconductor and global MEMS markets,” said Tony McKie, CEO of memsstar. “Our background in semiconductor etch and deposition processes positions us to deliver the most advanced MEMS platforms and best remanufactured equipment in the industry. With strong growth on the horizon, investing in our facilities and infrastructure ensures that we can continue to meet customer demand.”

Located in Livingston, Scotland, the new, dedicated 1600 sq m facility houses the company’s corporate headquarters, manufacturing, spare parts and customer training facilities. The facility has a 300 sq m Class 1000 cleanroom for manufacturing in addition to dedicated clean facilities and service areas. Representing a 40 percent increase in manufacturing capacity over the company’s prior location, cleanroom space will be dedicated to manufacturing memsstar’s advanced MEMS platforms for the global marketplace and remanufacturing etch and deposition equipment from Lam, Novellus and Applied Materials to serve its European semiconductor customers.

By Debra Vogler, SEMI

The introduction of new materials, such as III-Vs, into high-volume manufacturing of semiconductors, likely will occur sometime around the 7nm and/or 5nm nodes. III-V’s introduction, along with the potential transition to 450mm wafers, and the increasing expansion of global regulatory requirements, will heighten environmental, health and safety (EHS) concerns that must be addressed as the industry goes forward. The Sustainable Manufacturing Forum to be held in conjunction with SEMICON West 2014, will feature experts in the manufacture of semiconductors, microelectronics, nanoelectronics, photovoltaics, and other high-tech products.

One of the Sustainable Manufacturing Forum speakers, Richard Hill, Technology Infrastructure manager at SEMATECH, will discuss how the addition of III-V materials into the high-volume manufacture of semiconductors will bring sustainability issues to the forefront, primarily driven by the toxicity of arsenic that is used in much greater quantities in III-V production. Challenges include wastewater treatment, toxic gas detection control and abatement, and the need for robust protocols to ensure operator and maintenance personnel safety. Hill will speak at the Next Generation Eco Fab session on July 9 at SEMICON West.

SEMATECH recently completed a joint study of III-V EHS challenges with the College of Nanoscale Science and Engineering (SUNY CNSE). The assessment consisted of running 300mm wafers through a representative 5nm III-V process flow (Figure 1). (Many semiconductor industry experts agree that III-V materials will enter the process flows in high volumes at 5nm.) Among the processes that will pose the greatest challenges with respect to III-V materials are MOCVD, CMP, wet etch/clean, dry etch, and film deposition. The project was heavily focused on understanding the levels of arsenic that would be present in wastewater, as well as loading of other III-V materials. The impact of III-V outgassing that could occur during processing and the amounts of gases that could be released when a tool is opened for maintenance were of particular interest in the project.

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Among the high-level challenges associated with wet etch are the potential for arsine and phosphine outgassing (during processing).

“Wet etch tools are designed to have a controlled environment,” said Hill, “but they are not like high-vacuum systems that are designed to contain toxic gases.” Hill told SEMI that if the exhaust system fails during the processing of a wafer, it is critical to know the risks and ensure mitigation. The SEMATECH/CNSE project looked at a range of different chemistries and identified those that are low risk for arsine and phosphine generation (and therefore, a low risk of outgassing) and those that had a high risk of outgassing. The low risk chemistries are, naturally, the ones that the industry should try to design into a III-V flow.

The joint project also evaluated the III-V loading in wastewater from the wet etch process. “There were measurable quantities of arsenic in the waste stream,” said Hill. Though he added that while the levels weren’t significantly high, some treatment of the waste water would have to be done depending on what’s allowable within local discharge limits and permits. With the industry looking ahead to 5nm and already designing the fabs of the future, Hill believes that these results will be important for specifying wastewater treatment.

The joint SEMATECH/CNSE project also evaluated the wastewater stream from the burn wet scrubber when III-V materials are used in a contact etch (dry) process. The study found measurable arsenic in the wastewater. “Fabs of the future will need wet treatment facilities for arsenic and indium,” Hill told SEMI. “In recent years, concerns about indium have been elevated, and we believe that tighter restrictions on it will be introduced in the future.” Chamber clean is also critical when etching (dry) III-V materials. “If you don’t do the right type of cleaning regimen, you could have next-wafer contamination.” Additionally, without the proper protocol, maintenance personnel could be exposed to arsine or phosphine when the chamber is opened, depending on the process. The cleaning protocol is highly dependent on the type of etch being done, and each type could have different requirements.

For Hill, the key takeaway from the joint evaluation was that, while there are risks when processing III-V materials, there are no showstoppers — solutions can be engineered. “People should take these risks seriously, but they shouldn’t be scared off by them,” said Hill.

Sustainability and the Role of Collaboration and Standards

Steve Moffatt, CTO, Front-end Equipment at Applied Materials (also a speaker at the Next Generation Eco Fab session at the Sustainable Manufacturing Forum at SEMICON West), told SEMI that many established procedures for dealing with arsine and phosphine already exist. He views the efforts by the industry going forward as one of accurately quantifying the size and scope of the problem. “The methods are in place, but the absolute quantities of III-Vs will be substantially higher,” said Moffatt.

Additionally, other emissions (e.g., PFCs) that are well regulated and generally understood, will see an increase in the quantities as a result of more layers being processed for 3D chips. Even the potential transition to 450mm wafers will figure into the industry’s need for a more accurate scope of the EHS challenges involved. The increase in wafer size will naturally lead to larger manufacturing equipment noted Moffatt and that, in turn, will drive increases in energy, water, and process chemical consumption at both the tool and fab levels.

As regulatory pressure increases on a global scale, the situation also becomes more complex. Beyond the use of new materials such as III-Vs and nanomaterials, Moffatt commented that new methods of energetics (i.e., ways of putting energy into a processing system) will require very careful and close assessment of the risk control measures. Another sustainability issue arises from the basic fact that, as opposed to the highly prevalent element of silicon in the earth’s crust, many of the newer materials being used in higher quantities for semiconductor manufacturing (e.g.,Ga, As, etc.) are much less abundant. These exotic materials, of necessity, must be handled in the most efficient of ways.

Going forward, there will be increased regulatory pressure to reduce a fab’s carbon footprint and produce more sustainable products. Moffatt says the industry can expect more pressure to reduce greenhouse gas (GHG) emissions along with adhering to conflict minerals regulations and managing EHS concerns throughout the entire life-cycle of a product (Figure 2). “One company can’t do it on its own, it’s a life-cycle consideration,” said Moffatt. “If we have the right collaboration together, we have a greater probability with the right kinds of standards of bringing good, effective green chemistry solutions to high-value problems.”

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Regarding standards activities on energetics, Moffatt pointed to ongoing collaboration and hazard assessment between SEMI, SEMATECH and other industry groups.

“We will need to continually evaluate the need for additional standards activities — both new and updates — in addition to industry collaboration on “Green” chemistry,” said Moffatt.  “As a starting point, sustainability concerns could be built into the initial assessment of new chemicals and processes, which will begin the discussion and raise awareness of these issues.”

Hill (SEMATECH) and Moffatt (Applied Materials) will be joined by speakers from IMEC, Intel, Samsung, Air Products, and MW Group at the “Next Generation Eco Fab” session of the Sustainable Manufacturing Forum at SEMICON West 2014, July 7-10 in San Francisco, Calif.  For more information, visit: http://www.semiconwest.org.

InvenSense, Inc., the provider of MotionTracking system on chip (SoC) and sound devices, announced the world’s widest full scale range (FSR) 3-axis MEMS gyroscope for high impact wearable applications. The ITG-3701 also offers the smallest size, lowest profile and lowest power, ideal for wearable applications in sports and concussion analysis. Today’s wearable sports applications require higher than the common ±2000 dps (degrees per second) FSR so that critical data is not lost at the point of impact. The ±4000 dps range of the ITG-3701 enables precise analysis of a golf or tennis racquet swing, soccer ball and basketball applications providing continuous data before, during and after impact. The InvenSense ITG-3701 directly addresses the wearable sports market technology requirements with lowest power consumption of only 5.9mW (3.3mA at 1.8V), extending battery life and an industry first 0.75mm height.

“High-impact sports solutions saturate the gyroscope during the point of contact or very high rotation rate. The ITG-3701 solution with its unrivaled FSR will enable OEMs to collect data during the most critical juncture of a golf or tennis swing,” said Ali Foughi, Vice President of Marketing and Business Development at InvenSense. “The application goes beyond wearable sports as our solution can benefit any application that has high maneuverability and requires high speed motion analysis.”

The InvenSense ITG-3701 flexible programmable ranges of ±500 dps, ±1,000 dps, ±2,000 dps and ±4,000 dps, allows the OEM to pick the best motion range for any activity or context. The solution includes integrated self-test and offset temperature compensation, delivering ease of integration and consistent performance. Other industry-leading features include a 3x3x0.75mm plastic 16-pin QFN package, on-chip16-bit ADCs, outstanding rate noise performance of only 0.02 dps/√Hz, built-in FIFO, programmable digital filters, and programmable interrupts. These SoCs are available with I2C and high-speed SPI serial interfaces, along with a flexible operating range of 1.71V to 3.6V.

MEMSIC Inc., a sensing solution provider, today announced the availability of its MMC3524xPJ Three-Axis Magnetic Sensor.  This fully integrated device achieves a dramatic increase in performance over competing devices, particularly in the areas of stability over temperature and time, and insensitivity to external magnetic disturbance. In particular, the offset drift over temperature is <1.5mGauss, which is more than 100x better than the nearest competitor. Additionally, the device can withstand a magnetic disturbance of up to 100G without recalibration. This enhanced stability enables the elimination of the inconvenient and frequent “figure-8” user calibration, delivering a whole new user experience in mobile phones, tablets and wearable devices.

The MMC3524xPJ uses MEMSIC’s proprietary anisotropic magnetic resistive (AMR) technology to achieve its high performance.  With a full scale range of +/- 24 Gauss (+/- 2400 μTesla), and an RMS noise of 2mGauss (0.2uT), the device offers a dynamic range 2x – 5x greater than its competition. This results in a more accurate heading determination with less averaging. When combined with MEMSIC’s proprietary algorithms, this enables a heading accuracy of <1 degree, a necessary requirement to enabling Location Based Services in mobile devices.

Power consumption is also critical to mobile and wearable devices in order to extend battery life. At 50uA (10Hz rate), the MMC3524xPJ reduces current consumption by 5x compared with industry-leading products, and is one of the few devices to run from a single 1.8V supply. In addition, the MMC3524xPJ offers a sleep current of 5nA (max), which is 1000x lower than the competition.

“The magnetic sensors in all previous and current generation mobile phones and tablets require a frequent and cumbersome ‘figure 8’ recalibration in order to get an e-compass function with acceptable accuracy,” said Dr. Yang Zhao, MEMSIC CEO. “This is a real burden and annoyance to the user, especially with the tablets and larger phones. With our new MMC3524xPJ, we have virtually eliminated this burden, enabling a new level of user experience and paving the way for accurate pointing in a new generation of Location Based Services.”

Read more: Sensor hubs make big gains while enabling the future of sensing

The MMC3524xPJ is offered in an industry-standard 1.6 mm. x 1.6 mm. x 0.5 mm package and operates from a single 1.8 V or Dual 1.8V / 3V supplies, making it ideal for mobile applications such as electronic compassing in cellular phones and tablets, pedestrian navigation, gaming controls, wristwatches, in-vehicle GPS navigation, and other magnetic field measuring applications.