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The semiconductor industry today is faced with several substantial issues-not the least of which are the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost of these designs. IP integration is also a growing part of design costs. Semico’s new report SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts addresses these and many other design concerns while reporting that the average design cost for Basic SoCs across all geometries in 2017 was $1.7 million.

“Analysis of design activity for the three types of SoC profiled in this report shows that while design costs at new nodes continue to increase, the average design cost at each node is not increasing as quickly, giving room for designers to still accomplish their silicon solutions at reasonable costs if they are prudent in their design selection,” says Rich Wawrzyniak, Sr. Market Analyst for ASIC & SoC at Semico. “For each of the three types of SoC there is still considerable activity at the older nodes of 90nm, 65nm and 40nm. Costs at these geometries are much less than at 10nm and 7nm so even though these newer designs cost much more, the average for all SoCs has dropped due to the increase in new designs for Basic SoC.”

Key findings of the report include:

  • The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017.
  • The average design cost for all SoCs across all geometries is forecast to increase to $5.3M by 2023.
  • The number of ‘first-time-right’ designs has dropped at every process geometry since the 180nm node.
  • Silicon design costs at the 7nm node for an Advanced Performance Multicore SoC first-time effort are projected to be 23% higher than at the 10nm node.

In a unique, insightful look at this constantly evolving market, Semico Research’s new report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, examines the primary forces and integration pressures that are driving this market today in 135 pages, with 41 tables and 64 graphs. This study analyzes many important questions facing the semiconductor industry today including:

  • What is the current cost for a Complex System-on-a-Chip (SoC) design, and what will it be in the near future?
  • Is it possible to do SoC designs without maximizing the costs for these designs?
  • What is the incidence of ‘first-time-right’ for these designs today and in the near future?
  • How is the design cycle time for these designs changing?
  • How do complicated software applications impact the design costs?
  • How fast are IP integration costs rising, and how high will they go?
  • What strategies are designers using to cope with rising design costs?
  • What is the average silicon design cost today for each process geometry and SoC type, and how quickly is it rising?
  • What impact will EDA tools that include some artificial intelligence (AI) and machine learning (ML) functionality have on design costs for complex silicon?

Achronix Semiconductor Corporation, a developer of field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), today announced availability of an optimized High-Level Synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products.

The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor’s Catapult® HLS and Achronix’s ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve quality of results (QoR), it is suitable for any design targeting Achronix technology.

“The combination of Mentor’s powerful Catapult tools and Achronix’s embedded FPGA technology offer a truly unique value proposition for companies that require high performance FPGA technology in their SoC that can be configured using a proven C‑based design flow,” remarks Steve Mensor, Achronix’s vice president of marketing. “This combined solution is a great testament of a close working relationship between the engineering groups at Mentor and Achronix. Our initial target was 5G wireless, but the unique capabilities of the overall solution will be valuable across many market segments that require the fastest development time.”

“We are happy to welcome Achronix to the Mentor OpenDoor Program, and pleased to be an active member of the Achronix Partner Program. This open and collaborative partnership is very strategic and is already proving beneficial to our mutual customers,” notes Ellie Burns, director of marketing, Calypto Systems Division at Mentor. “Achronix eFPGA offers a tremendous ability to adapt to late changing and new requirements in a field programmable SoC. Coupled with Catapult HLS and the verification speed of C++, chip designers can now easily go from algorithm change to new low-power, high-performance hardware in days rather than weeks or months.”

The Catapult to Achronix Flow

The Catapult HLS to Speedcore embedded FPGA technology flow gives designers the ability to make algorithmic changes in late stages of IP development and to optimize the algorithm and the digital micro-architecture. The integrated verification environment allows reuse of the software tests for generated register transfer level (RTL) code, reducing the need for dedicated RTL test benches by more than 80%.

Achronix ACE design tools support Catapult’s RTL constructs and primitives. Currently Achronix libraries for its Speedcore eFPGA products and for its Speedster standalone FPGAs are integrated into the flow.

The Achronix high-performance and high-density FPGA technology can be used for diverse hardware acceleration applications in data center compute, networking and storage; 5G wireless infrastructure, network acceleration; advanced driver assistance systems (ADAS) and autonomous vehicles.

Availability

Early versions of the design and development environment are available now.

United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a global semiconductor foundry, and Avalanche Technology, Inc., the next generation STT-MRAM (Spin Transfer Torque Magnetic RAM) leader, today announced that they have entered a partnership for joint development and production of MRAM to replace embedded flash. UMC will also make this technology available to other companies through licensing with Avalanche Technology Inc.

Under the terms of the agreement, UMC will provide embedded non-volatile MRAM blocks based on UMC’s 28nm CMOS manufacturing process. This will enable customers to integrate low latency, very high performance and low power embedded MRAM memory blocks into MCUs and SoCs, targeting the Internet of Things, wearable, consumer, industrial and automotive electronics markets.

The two companies are also considering to expand the cooperation beyond 28nm, as Avalanche Technology’s CMOS compatibility and scalability to advanced process nodes enables integration of unified memory (non-volatile as well as SRAM) blocks into next generation highly integrated MCUs and SoCs. This allows system designers to maintain the same architecture and software ecosystem without a redesign.

“We’re excited to team with a world leader in semiconductor manufacturing such as UMC to bring this outstanding technology to market,” said Petro Estakhri, CEO and co-founder of Avalanche Technology.

“UMC is continuously introducing enhanced process offerings to bring added competitive benefits to our customers,” said G C Hung, vice president of Advanced Technology Development at UMC. “With embedded NVM becoming more prevalent in today’s IC designs, we have developed a strong portfolio of robust eNVM process solutions for high growth sectors such as emerging consumer and automotive applications. We are happy to cooperate with Avalanche Technology for 28nm MRAM, and we look forward to ramping this process to production for UMC customers.”

Samsung Electronics Co., Ltd. today announced that it has begun mass producing the industry’s first 4-bit (QLC, quad-level cell) 4-terabyte (TB) SATA solid-state drive (SSD) for consumers.

Based on 1-terabit (Tb)* V-NAND with outstanding performance equivalent to the company’s 3-bit design, Samsung’s QLC SSD is expected to bring a new level of efficiency to consumer SSDs.

“Samsung’s new 4-bit SATA SSD will herald a massive move to terabyte-SSDs for consumers,” said Jaesoo Han, executive vice president of memory sales & marketing at Samsung Electronics. “As we expand our lineup across consumer segments and to the enterprise, 4-bit terabyte-SSD products will rapidly spread throughout the entire market.”

With its new 1Tb 4-bit V-NAND chip, Samsung will be able to efficiently produce a 128GB memory card for smartphones that will lead the charge toward higher capacities for high-performance memory storage.

Typically, as data stored within a memory cell increases from three bits to four, the chip capacity per unit area would rise and the electrical charge (used to determine information from a sensor) would decrease by as much as 50 percent, making it considerably more difficult to maintain a device’s desired performance and speed.

However, Samsung’s 4-bit 4TB QLC SATA SSD maintains its performance levels at the same level as a 3-bit SSD, by using a 3-bit SSD controller and TurboWrite technology, while increasing drive capacity through the use of 32 chips, all based on 64-layer fourth-generation 1Tb V-NAND.

The 4-bit QLC SSD enables a sequential read speed of 540 MB/s and a sequential write speed of 520 MB/s, and comes with a three-year warranty.

Samsung plans to introduce several 4-bit consumer SSDs later this year with 1TB, 2TB, and 4TB capacities in the widely used 2.5-inch form factor.

Since introducing the 32-gigabyte (GB) 1-bit SSD in 2006, which ushered in the PC SSD era, to today’s 4TB 4-bit SSD, Samsung continues to drive new thresholds for each multi-bit generation.**

In addition, the company expects to provide M.2 NVMe SSDs for the enterprise this year and begin mass production of 4-bit fifth-generation V-NAND. This will considerably expand its SSD lineup to meet the growing demand for faster, more reliable performance across a wide span of applications, such as next generation data centers, enterprise servers, and enterprise storage.

* 1Tb (128GB) x 32 = 4TB (4,096GB)

** Samsung’s mass production history of SSDs in bits per cell

Year Bit Nodes Chip Capacity Drive Capacity
2006 1-bit SLC (single-level cell) 70nm-class 4Gb 32GB
2010 2-bit MLC (multi-level cell) 30nm-class 32Gb 512GB
2012 3-bit TLC (triple-level cell) 20nm-class 64Gb

500GB
2018 4-bit QLC (quad-level cell) 4th-gen V-NAND 1Tb 4 TB

The term energy harvesting, also known as power scavenging, is used to describe the creation of energy derived from a variety of external sources such as solar power, thermal energy, wind energy, kinetic energy or electromagnetic sources. Energy harvesters accumulate the wasted energy in a system, such as heat given off by motors or semiconductors, or the vibrations of motors or other moving objects. The basic technologies for generating energy are: mechanical vibration (kinetic energy), thermoelectric, solar (photovoltaic), and RF/Inductive.  A new research report from Semico Research Energy Harvesting: Reaping the Abundant Market, estimates that the semiconductor content for energy harvesting solutions will explode to $3.4 billion by 2022.

“While there is a great deal of interest in the different types of energy harvesting devices or energy generators, the greater opportunity for the semiconductor industry is the overall solution which includes power conversion, power management, microcontrollers, radios and MEMS sensors,” says Joanne Itow, Semico’s Manager of Manufacturing Research. “The advent of IoT with remote monitoring and data collection has also prompted more interest in energy harvesting as a viable solution to maintain WSNs (Wireless Sensor Networks).”

Key findings of the report include:

  • The number of devices with an energy harvesting solution will reach 509 million units by 2022.
  • Consumer devices (including toys) with energy harvesting accounted for 8 million units in 2017.
  • Bridges are expected to be a large user of energy harvesting in the infrastructure sector by 2022.
  • Energy harvesting devices in all buildings is expected to have a CAGR of 20.7% by 2022.

In its recent report “Energy Harvesting: Reaping the Abundant Market” (MP112-18), Semico Research examines the market opportunity for energy harvesting outside of large solar installations and commercial power generation. A broad range of markets will employ energy harvesting to either replace batteries or extend battery life. These applications cover wireless sensor nodes (WSN) for bridges, infrastructure, building automation and controls, home automation (including lighting, security and environmental), automotive applications, cell phones, wearables and other consumer electronics. The report is 98 pages long and includes 13 tables and 37 figures.

Companies cited in the report include:

Analog Devices, Microchip (Atmel), CHERRY/ZF, Cymbet, Cypress, EnOcean, e-peas, Analog Devices/Linear Technology, Maxim Integrated, Microchip Technology, Powercast, Renesas, Semtech, Silicon Labs, Silicon Reef, STMicroelectronics, Texas Instruments, Ilika, Imprint Energy, Sakti3, Solid Power, Apple, Laird, microGen, Micropelt, Perpetuum, Piezo Systems, Sanyo, Thermo Life, Thermogen Technologies, EH Solution Providers, LORD Microstrain®, National Instruments, Nikola Labs, Phase IV Engineering, Resensys, Soundpower Corp., Eta Compute, Mentor Graphics, and X-FAB.

By Iris Tsou

The march to greater precision, efficiency and safety – the lifeblood of high-technology manufacturing facilities – has taken on a new urgency as emerging applications such artificial intelligence (AI), the Internet of Things (IoT) and Industry 4.0 give new meaning to smart factories. Facing fiercer competition and ever more sophisticated fabrication processes, semiconductor fabs are under intense pressure to keep pace with new technologies as they work to upgrade. Nowhere are the stakes higher than in Taiwan, where high-tech manufacturing contributes mightily to the region’s GDP growth.

To help Taiwan fabs confront the challenges and opportunities of designing smarter factories, SEMI and its High-Tech Facility Committee hosted the High-Tech Facility Workshop in June. SEMICON Taiwan 2018 High-Tech Facility Pavilion exhibitors gathered to explore how they can build smarter factories by deploying smart surveillance and disaster prevention technologies along with smart communications systems that better use manufacturing data to drive new safety and product quality efficiencies.

During the workshop, SEMI High-Tech Facility Committee representatives shared strides it has made upgrading overseas facilities and developing standards to help establish smart factories in Taiwan.

SEMICON Taiwan – 5-7 September at Taipei’s Nangang Exhibition Center – is also an important event for advancing smart manufacturing in Taiwan. Nearly 30 leading global manufacturers will exhibit at the SEMICON Taiwan High-Tech Facility Pavilion. The venue covers operational aspects of semiconductor manufacturing vital to becoming smarter including energy savings, nano-contamination control, facility information modeling, precision instrumentation and control, fire protection, mechatronics, and automation control. The pavilion will also feature a series of theme events offering a comprehensive overview of topics including the latest practices for integrating smart facility capabilities from the perspective of an advanced fab designer.

At the TechXPOT stage, High-Tech Facility Pavilion exhibitors will also demonstrate the latest technology breakthroughs and cutting-edge smart factor solutions.

The September 6th High-Tech Facility International Forum at SEMICON Taiwan will again gather factory experts and thought leaders from industry and academia to examine “Effective Ways to Make a Facility Smart.“ Experts from industry heavyweights in the fields of wafer foundry, LCD, memory and semiconductor packaging including TSMC, UMC, Innolux, ASE, Micron Taiwan, Winbond and VIS will offer insights into key areas of high-tech facilities including facility electricity, machinery, water management, vaporization and automation systems. On the same day as the forum, the High-Tech Facility Get-Together and High-Tech Facility VIP Dinner will bring together industry elites, academic professionals, and government officials to explore partnership opportunities.

SEMI Taiwan and the High-Tech Facility Committee share HTF market trends information, technology updates and standards with SEMI members and exhibitors.

Founded in 2013, the High-Tech Facility Committee now has 85 corporate members. Dedicated to accelerating industry collaboration through the integration of Taiwan industrial, government and academic resources, the committee each year holds several group meetings focusing on topics including energy savings, earthquake and fire protection, nano-contamination control, and precision instrumentation and control to advance critical technologies and facilitate standardization. The committee also aims to help the industry become more competitive faster by promoting technology standards that boost productivity and reduce production costs.

Please visit www.semi.org and www.semicontaiwan.org for more information about SEMI’s high-tech facility initiatives.

Iris Tsou is a marketing specialist at SEMI Taiwan. 

Originally published on the SEMI blog.

Xperi Corporation announced a partnership with global semiconductor foundry, UMC. This strategic partnership will enable the companies to support the growing demand for Invensas ZiBond and Invensas DBI 3D semiconductor technologies.

Together, Xperi and UMC will further optimize and commercialize the ZiBond and DBI technologies for a wide range of semiconductor devices including image sensors, radio frequency (RF), MEMS, display drivers, touch controllers, SoC, analog, power and mixed-signal devices. Wafer to wafer (W2W) and die to wafer (D2W) bonding and 3D interconnect implementations will be employed to address the requirements of a variety of applications within the mobile, consumer, automotive, communication, industrial and Internet of Things (IoT) industries.

“As a world-leading semiconductor foundry, we are committed to delivering leading-edge solutions to our customers,” said Wenchi Ting, vice president of specialty technologies at UMC. “By partnering with Xperi and the Invensas team, true pioneers in direct and hybrid bonding technologies, we continue to be well-positioned to meet our customers’ evolving requirements for advanced wafer bonding technologies.”

“We are excited to join forces with UMC, a premier global foundry engaged in every major sector of the electronics industry, to expand the production base for our ZiBond and DBI bonding and 3D interconnect platforms,” said Craig Mitchell, president, Invensas. “We look forward to working together to proliferate these enabling technologies into a wide range of high volume semiconductor applications.”

ZiBond is a low temperature homogenous direct bonding technology that forms strong bonds between semiconductor wafers or die with same or different coefficients of thermal expansion. This technology is used in image sensors, MEMS and various RF front-end devices.

DBI is a low temperature hybrid direct bonding technology that allows semiconductor wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect. This technology is suited for various semiconductor devices such as image sensors, DRAM, MEMS and RF devices.

Products employing these technologies are found in smartphones, tablets, laptops, cameras, televisions and gaming consoles, as well as in industrial, automotive and IoT electronic devices.

Toshiba Memory Corporation today announced that it consummated the merger with K. K. Pangea which is its parent company on August 1, 2018. The company name after the merger is Toshiba Memory Corporation. Today the company also introduces the executive officer system to improve the efficiency of business execution and strengthen the corporate governance. The outline of Toshiba Memory and the list of its directors, executive officers and statutory auditors as of August 1, 2018 are as follows.

1. Outline of Toshiba Memory Corporation
Name Toshiba Memory Corporation
Address 1-1 Shibaura 1-chome, Minato-ku, Tokyo

Name and Title of
Representative

 Naruke Yasuo

Representative Director, President and Chief Executive Officer
Capital

473,400,025,000 yen

Major Shareholders and
Shareholding Ratios

 BCPE Pangea Cayman, L.P. 49.9%

Toshiba Corporation 40.2%

Hoya Corporation 9.9%

*Based on ownership of voting rights
2. List of directors, executive officers and statutory auditors as of August 1, 2018
– Director
Representative Director Yasuo Naruke
Director Yuji Sugimoto
Director David Gross-Loh
Director Masashi Suekane
Director Hiroshi Suzuki
– Executive Officer
President and Chief Executive Officer Yasuo Naruke

Executive Vice President and Executive Officer (Chief
Operating Officer and Vice President of Memory Division)

 Tomoharu Watanabe

Executive Vice President and Executive Officer (Chief
Technology Officer)

 Nobuo Hayasaka
Managing Executive Officer (Chief Financial Officer ) Hideki Hanazawa

Managing Executive Officer (Chief Production Officer and
General Manager, Yokkaichi Operations)

 Tomoharu Matsushita
Managing Executive Officer (Chief Marketing Officer) Naohisa Sano
Managing Executive Officer (Vice President of SSD Division) Masashi Yokotsuka
Executive Officer (Chief Strategy Officer) Shinichi Hashimoto
Executive Officer (Chief Information and Security Officer) Akio Oka
Executive Officer (General Manager, Legal Affairs Division) Takahiro Asakura

Executive Officer (General Manager, Human Resources and
Administration Division)

 Kyota Okishiro
– Statutory Auditor
Statutory Auditor Yurio Ogawa
Statutory Auditor Shunsuke Nakahama
Statutory Auditor Isao Morita

Toshiba Memory Corporation is dedicated to the development, production and sales of flash memory and SSDs. In April 2017, Toshiba Memory was spun off from Toshiba Corporation, the company that invented NAND flash memory in 1987. Toshiba Memory pioneer cutting-edge memory solutions and services that enrich people’s lives and expand society’s horizons.

Avnet (Nasdaq: AVT), a global technology company, has been named a global distribution partner for Microsemi Corporation, a wholly owned subsidiary of Microchip Technology, Inc. As an extension of Avnet’s multiyear relationship with Microchip Technology, Inc. (Nasdaq: MCHP), Avnet customers now have immediate access to the complete Microsemi portfolio of semiconductor and system solutions for aerospace and defense, communications, data center and industrial markets. Microchip completed its acquisition of Microsemi earlier this year.

“As our customers increasingly turn to us for secure solutions to help them bring their industrial, aerospace and defense products to market faster, Microsemi is the ideal fit to our product line card,” said Lynn Torrel, senior vice president of global supplier and customer management, Avnet. “Avnet is experienced and knowledgeable in the full Microsemi portfolio, and we’re ready to support our customers and drive growth for Microsemi’s target industries. The extension of our partnership with Microchip underscores our focus and commitment to providing our supplier partners with the highest level of expertise and services to improve their businesses.”

Microsemi is a leading provider of semiconductor solutions differentiated by power, security, reliability and performance. As part of the expansion of Avnet’s Microchip franchise, Avnet will now distribute the full line of Microsemi products which includes: high performance analog and mixed signal, enterprise storage and communication solutions, programmable solutions, power management, timing and ASIC offerings — as well as custom design capabilities and services.

SEMI today announced its support for calls on the Trump administration yesterday by nearly 50 members of Congress to remove tariffs on U.S. semiconductor products imported from China. In a bipartisan letterto Ambassador Robert Lighthizer, U.S. Trade Representative (USTR), the members of the House of Representatives – led by Reps. Pete Sessions (R-TX) and Zoe Lofgren (D-CA), the House co-chairs of the Congressional Semiconductor Caucus – stressed the importance of semiconductors in the modern economy and argued that the duties will do nothing to address concerns regarding China’s trade practices.

SEMI fully supports the Congressional recommendation and believes that the proposed tariffs will ultimately reduce semiconductor-related exports, limit technology innovation, introduce significant uncertainty in the semiconductor supply chain and cost U.S. companies an estimated more than $500 million annually. The tariffs also threaten to raise prices of semiconductor products and put thousands of high-paying and high skill jobs at risk. Last week, SEMI testified before a U.S. government interagency panel weighing the merits of the tariffs, urging the Trump administration to eliminate tariffs on semiconductor products.