Tag Archives: letter-pulse-business

To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep. ALLVIA’s new TQV solution significantly improves the performance of 3D-ICs by creating IC interconnects with lower parasitic capacitance than can be achieved with the earlier generation of through-silicon via (TSV) technology.

he company had been outsourcing the production of via holes in the fused silica (quartz) that it uses, but its newly added capability brings all via-drilling operations in-house, expanding ALLVIA’s intellectual property and reducing the cost of production. The company will continue to apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating to fabricate finished interposer products.

Sergey Savastiouk, CEO of ALLVIA, said, “Performing our own via drilling in fused silica allows us to improve turnaround times and production volumes for our customers while also delivering better quality using our state-of-the-art technology for copper plating, chemical mechanical polishing and deep via thin-film deposition.”

In addition to providing via foundry services, ALLVIA applies its technology in manufacturing and selling ultra-thin quartz interposers that form the electrical connections between a silicon chip and a printed circuit board.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has started construction work for the next expansion phase of its corporate headquarters. The new building will house EVG’s “Manufacturing III” facility, which will more than double the floor space for the final assembly of EVG’s systems.

“With our innovative manufacturing solutions for the high-tech industry as well as new biomedical applications, we operate in very dynamic markets with great future prospects,” stated Dr. Werner Thallner, executive operations and financial director at EV Group. “In light of the high capacity utilization in all areas of our existing facilities, as well as the positive market outlook, we decided to implement our plans for building our Manufacturing III facility this year. This will support our long-term growth targets at our corporate headquarters in St. Florian am Inn.”

EVG Manufacturing III Photo 1

The new Manufacturing III building, adjacent to the new test room site that was opened just a few months ago, will be built next to the river Inn. The ultramodern building will provide approximately 4,800 square meters of additional space in total, which will benefit not only manufacturing but other departments as well. In addition to an expansion of warehouse space, a new delivery area with a dedicated packaging site designed for cleanroom equipment will be created, along with an airfreight security zone and new truck loading docks for the shipment of the completed systems to EVG’s worldwide customers.

The construction of the new Manufacturing III building is set to be completed in early 2019.

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes

Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology

Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility

Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes. The corresponding process design kits (PDKs) are now available for download.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, the layout vs. schematic (LVS) function in PVS and LDE Electrical Analyzer.

Cadence digital and signoff features available for the 7nm process are also available for the 5nm and 7nm+ process. Some of these features include cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing. These capabilities can enable customers to successfully design mobile and HPC systems with improved power, performance and area (PPA) while reducing iterations and achieving their cost and performance objectives.

In addition, Cadence has delivered new enhancements focused on EUV support at key layers and associated new design rules that specifically support the 5nm and 7nm+ processes. Some of the other newest enhancements for the 7nm+ process include cell pin support, Self-Heating Effect (SHE) and heatsink support.

Specifically for the 5nm process, Cadence digital and signoff tools offer high-resistance resistor support, router compliance for new rules and new extraction support including additional resistor layer modeling and other middle end-of-line (MEOL) features.

5nm and 7nm+ Custom/Analog Tool Certification

The certified custom/analog tools include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF, and Spectre Circuit Simulation, as well as the Virtuoso® product suite, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment.

By using the latest capabilities and design methodologies included with the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies, while maintaining a similar effort and cycle time via the advanced capabilities in the Virtuoso and Spectre tools.

Cadence delivered several custom/analog enhancements specifically to support the TSMC 5nm and 7nm+ process technologies. For example, Cadence introduced an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet their power, multiple patterning, density and EM requirements. In addition, Cadence introduced universal poly grid snapping, asymmetric coloring support and voltage-dependent rule support for power/ground rails specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

The Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimizations and signoff.

“Using the latest design rules and PDKs, our customers have started designing complex SoCs on our most advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through the continuation of our collaboration with Cadence, we’ve certified their tools and flows for 5nm and 7nm+ designs, which can enable our customers to achieve their design goals within a fast, predictable timeline.”

“Over the past few years, Cadence has taken on a broader role in facilitating advanced-node adoption due to the optimizations and performance improvements across our digital and signoff and custom/analog tool suites,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “We’ve expanded our collaboration with TSMC by developing tools and flows that support their 5nm and 7nm+ process technologies, and our latest TSMC certifications are enabling us to support customers using the most advanced process nodes.”

Cyient Limited (“Cyient”), a global provider of engineering, manufacturing, geospatial, networks, and operations management services, today announced that its step down subsidiary Cyient Europe Ltd. has acquired AnSem N.V., a fabless, custom analog and mixed-signal application-specific integrated circuits (ASICs) design company. AnSem specializes in advanced analog, radio frequency, and mixed-signal integrated circuit design and provides custom ASICs for clients around the world across key industries, including automotive, medical, industrial, smart home, and smart grid, with long-life applications of five to ten years.

Incorporated in 1998 as a spin-off of the university of Leuven and with the support of imec – the research and innovation hub in nanoelectronics and digital technologies, AnSem has a strong team of technical and domain experts and has established itself as a well-known name in the field of analog and mixed-signal ASICs. Headquartered in Leuven, Belgium, AnSem has been certified as an ISO 9001:2015 company with a strong focus on solving complex challenges. Through its proven history of 100% first-time-functional designs, AnSem not only provides significant cost savings, but also time-to-market benefits, making this Cyient’s center of excellence. AnSem has revenue of ~$10 Million and 20%+ operating margin.

“AnSem’s leading-edge, custom mixed-signal analog integrated circuit (IC) capability allows Cyient to offer turnkey ICs, starting from concept circuit to final production. Through this acquisition, Cyient can help its clients develop smart analog sensors to capture data, while leveraging our IoT and analytics solutions to provide actionable insights,” said Suman Narayan, Senior Vice President for Semiconductor, IoT, and Analytics at Cyient.

“We are excited to become a part of the Cyient family and expand our capabilities to a larger customer base,” said AnSem’s CEO and Co-founder, Stefan Gogaert. “Over the years, AnSem has built an impeccable record of custom analog ASIC solutions delivery, a long-term customer base, and an unparalleled capability to develop, validate, and verify complex solutions. Thanks to this acquisition, our ability to deliver the volume of ASICs that our customers need to stay ahead of the competition will become even stronger. It also will enable us to be in the leading position that we were already aiming for.”

“Innovation is an integral part of imec‘s culture, and throughout the years, we have continuously supported regional start-up activities related to microelectronics and nanoelectronics. AnSem is one of the success stories that has grown to become a profitable company in analog, RF and mixed-signal design with an international customer base,” said Ludo Deferm, Executive Vice President at imec and member of the Board of Directors of AnSem. “We are delighted with the acquisition of AnSem by Cyient. This is a confirmation of AnSem’s business value and the strength of the eco-system around imec. We are hopeful that this acquisition is the beginning of a close collaboration between Cyient and imec, as well as with other Flemish companies.”

Cyient expects this transaction to be EPS accretive.

Synopsys, Inc. (Nasdaq: SNPS) today announced certification of the Synopsys Design Platform with TSMC’s latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology. With several test chips taped out and production designs currently under development by multiple customers, this certification by TSMC enables a wide range of designs from high-performance computing and high-density to low-power mobile applications using the Synopsys Design Platform.

This certification is a milestone for TSMC’s extreme ultraviolet lithography (EUV) process that enables significant area savings while maintaining high performance when compared to non-EUV process nodes.

The Synopsys Design Platform, anchored by Design Compiler Graphical synthesis and IC Compiler™ II place-and-route tools, has been enhanced to take full advantage of TSMC’s 7-nm FinFET Plus for high-performance designs. Design Compiler Graphical is capable of automatically inserting via pillar structures to boost performance and prevent signal electromigration (EM) violations, and can pass the information to IC Compiler II for further optimization. It also automatically applies non-default rules (NDR) during synthesis and performs layer-aware optimization to improve design performance. These optimizations, including IC Compiler II bus routing, continue throughout the place-and-route flow to meet stringent delay-matching requirements of high-speed network.

PrimeTime® timing analysis advanced waveform propagation (AWP) and parametric on-chip variation (POCV) technologies have been optimized to address increased waveform distortion and non-Gaussian variation effects of higher performance and lower voltage operation. In addition, PrimeTime’s physically-aware signoff has been expanded to support via-pillars.

Synopsys has enhanced the Design Platform to perform physical implementation, parasitic extraction, physical verification, and timing analysis to support TSMC’s WoW technology. The physical implementation flow with IC Compiler II provides full support for wafer staking designs, from initial die floorplan preparation to placement and assignment of bumps to implementation of die routing. Verification is done by IC Validator for DRC/LVS checks, and Synopsys’ StarRC tool performs parasitic extraction.

“Ongoing collaboration with Synopsys and early customer engagements on TSMC’s 7-nanometer FinFET Plus process technology are delivering differentiated platform solutions that help our mutual customers bring innovative new products to market faster,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”

“Our collaboration with TSMC on their mass-production 7-nanometer FinFET Plus process allows companies to confidently begin designing their increasingly large SoC and multi-die chips with the highly-differentiated Synopsys Design Platform,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification on TSMC’s 7-nanometer FinFET Plus process enables our customers to benefit from significant power, performance, and area improvements of an advanced EUV process, while accelerating time-to-market for their differentiated products.”

Intel today announced that Jim Keller will join Intel as a senior vice president. He will lead the company’s silicon engineering, which encompasses system-on-chip (SoC) development and integration.

“Jim is one of the most respected microarchitecture design visionaries in the industry, and the latest example of top technical talent to join Intel,” said Dr. Murthy Renduchintala, Intel’s chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG). “We have embarked on exciting initiatives to fundamentally change the way we build the silicon as we enter the world of heterogeneous process and architectures. Jim joining us will help accelerate this transformation.”

Keller brings to Intel more than 20 years of experience in x86 and ARM-based microarchitecture design across a broad range of platforms, including PCs, servers, mobile devices and cars.

“I had a great experience working at Tesla, learned a lot, and look forward to all the great technology coming from Tesla in the future. My lifelong passion has been developing the world’s best silicon products,” Keller said. “The world will be a very different place in the next decade as a result of where computing is headed. I am excited to join the Intel team to build the future of CPUs, GPUs, accelerators and other products for the data-centric computing era.”

Keller, 59, joins Intel from Tesla, where he most recently served as vice president of Autopilot and Low Voltage Hardware. Prior to Tesla, he served as corporate vice president and chief cores architect at AMD, where he led the development of the Zen* architecture. Previously, Keller was vice president of Engineering and chief architect at P.A. Semi, which was acquired by Apple Inc. in 2008. He led Apple’s custom low-power mobile chip efforts with the original A4 processor that powered the iPhone 4*, as well as the subsequent A5 processor.

He will officially start in his new role at Intel on April 30.

Siemens Corporation today announced that Barbara Humpton has been appointed CEO for the United States, effective June 1, 2018. Humpton (57) is currently CEO of Siemens Government Technologies, Inc. (SGT), a Federally-compliant U.S. organization structured to help address national imperatives in energy, infrastructure, automation and marine platforms.

“Barbara has broad knowledge of Siemens’ entire portfolio that will serve us well as we continue to grow the U.S. business,” said Lisa Davis, CEO of Siemens Corporation and Americas Region and Member of the Siemens AG Managing Board.

Humpton joined Siemens Government Technologies in 2011 as Senior Vice President for Business Development and was appointed to lead the company’s approach to the federal market in 2015. Prior to joining Siemens, Humpton held senior leadership positions at Lockheed Martin and Booz Allen Hamilton, where she was a Vice President at both firms.

“I am honored to work with the 50,000 Siemens employees in the U.S. to address the market’s needs in electrification, automation and digitalization. It’s an exciting time to be at Siemens as we develop products and services that are shaping the future,” said Humpton.

Siemens has been in the U.S. for more than 160 years and has invested $35 billion in America in the last 15 years alone. With 50,000 U.S. employees and more than 60 manufacturing sites, Siemens in the U.S. is using its global leadership in engineering and technology innovation to meet America’s toughest challenges, delivering solutions for industry, hospitals, utilities, cities, and manufacturers: from efficient power generation, to digital factories and oil and gas fields, to medical diagnostics, to locomotives, to next-generation software used in every phase of product development.

To receive expert insights sign up for Siemens’ U.S. Executive Pulse leadership blog. Follow Siemens USA on Facebook and Twitter.

Siemens AG (Berlin and Munich) is a global technology powerhouse that has stood for engineering excellence, innovation, quality, reliability and internationality for 170 years.

GLOBALFOUNDRIES today announced that Arbe Robotics has selected GF’s 22FDX® process for its groundbreaking patented imaging radar that will achieve fully automated system capabilities and enable safer driving experiences for autonomous vehicles.

Arbe Robotics’ radar is the first in the world to show real-time 1 degree resolution and provide the required enhancements for sensors and ADAS technologies. Arbe’s goal is to build a sensing system with high resolution and zero false alarms, so vehicles will be able to make decisions relying exclusively on the data provided by the radar. Leveraging GF’s 22FDX FD-SOI technology, the new chipset is increasing the amount of transmitting and receiving channels on a chip and allowing for better integration to Arbe’s proprietary processor.

The rise of autonomous driving is changing the automobile semiconductor market, which is expected to grow to an estimated $54 billion by 2023. This is driven by a need for new technologies that promise to enhance the driving experience, such as 360-degree surround view monitoring, which requires high resolution and long-range capabilities. GF’s 22FDX process provides the superior RF performance, power consumption, low noise, and high digital density to increase range and improve resolution for these applications.

As the first company to demonstrate ultra-high-resolution at a wide field of view, Arbe Robotics’ radar technology can detect pedestrians and obstacles at a range of 300 meters, in any weather and lighting conditions. The processor creates a full 3D shape of the objects and their velocity, and classifies targets using their radar signature.

“Arbe Robotics’ imaging radar is optimized for providing a real-time 4D picture of the environment at ultra high resolution,” said Kobi Marenko, CEO of Arbe Robotics. “The collaboration with GF is a significant step towards archiving the high-performance level required for autonomous driving safety. With over a decade of automotive industry experience, GF’s 22FDX delivers a performance on-demand, energy-efficient solution for our current and future radar technology needs.”

“The trend of autonomous driving is progressing rapidly, and with it is the need for high-resolution radar. The future will rely on a mix of real-time maps, advanced navigation software, and live data from vehicle sensors,” said Mark Granger, vice president of automotive at GF. “That’s why GF is pleased Arbe Robotics has chosen our 22FDX platform, together bringing valuable attributes that support the explosive growth of the autonomous driving industry.”

GF’s 22FDX platform is a part of the company’s AutoPro™ solutions, which provides customers with additional access to manufacturing services that support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0 to minimize certification efforts and speed time-to-market.

North America-based manufacturers of semiconductor equipment posted $2.42 billion in billings worldwide in March 2018 (three-month average basis), according to the March Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 0.4 percent higher than the final February 2018 level of $2.41 billion, and is 16.7 percent higher than the March 2017 billings level of $2.08 billion.

“March 2018 monthly billings for North American equipment manufacturers remain at robust levels,” said Ajit Manocha, president and CEO of SEMI. “We are seeing sustained strength in the global semiconductor equipment market, aligning with our expectation for a fourth consecutive year of spending growth.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
October 2017
$2,019.3
23.9%
November 2017
$2,052.3
27.2%
December 2017
$2,398.4
28.3%
January 2018
$2,370.1
27.5%
February 2018 (final)
$2,417.8
22.5%
March 2018 (prelim)
$2,426.9
16.7%

Source: SEMI (www.semi.org), April 2018
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ).