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Analog Devices, Inc. (NASDAQ: ADI) today announced the completion of its acquisition of Linear Technology Corporation.

“The combination of Analog Devices and Linear Technology creates an analog industry powerhouse,” said Vincent Roche, ADI President and Chief Executive Officer. “Together, we are capable of solving more of our customers’ biggest and most complex challenges at the intersection of the physical and digital domains. We expect that this combination will create tremendous value for our customers, our employees, and our shareholders for many years to come.”

Election of Robert H. Swanson to ADI Board of Directors

ADI also announced that Robert H. Swanson, former Executive Chairman of Linear Technology, has been elected to the ADI Board of Directors, effective immediately after the closing of the acquisition.

“We are very excited to welcome Bob Swanson to our Board,” said Ray Stata, ADI Chairman of the Board. “Bob’s decades of analog semiconductor expertise will add considerable value to ADI’s Board of Directors.”

Mr. Swanson, a founder of Linear Technology, has served as Executive Chairman of the Linear Technology board of directors since January 2005. Prior to that time, he served as Chairman and Chief Executive Officer of Linear Technology since its incorporation in 1981.

As a result of the acquisition, Linear Technology’s shares of common stock have been delisted from the NASDAQ Global Select Market effective as of the close of trading today.

Credit Suisse Securities (USA) LLC acted as ADI’s exclusive financial advisor and Wachtell, Lipton, Rosen & Katz and WilmerHale acted as ADI’s legal counsel in connection with the transaction.

Contribution from Linear Technology to ADI’s 2nd fiscal quarter of 2017

ADI expects Linear Technology to contribute between $160 million to $170 million in revenue to ADI’s second fiscal quarter of 2017. This revenue range includes a reduction of approximately $30 million related to a purchase accounting adjustment for Linear’s North America distributor deferred revenue where revenue is recognized on a sell-through basis, and represents ADI’s current best view of Linear’s business performance through the end of ADI’s second fiscal quarter of 2017.

ADI also expects its non-GAAP interest and other interest expense to be approximately $60 million in the second quarter of fiscal 2017, approximately $70 million in the third quarter of fiscal 2017, and approximately $60 million per quarter thereafter.

In the first full quarter after the combination, ADI expects its weighted average diluted sharecount to be approximately 375 million and for the Company’s non-GAAP tax rate to be approximately 15%.

With respect to the forward-looking information presented on a non-GAAP basis, ADI is unable to provide a quantitative reconciliation to GAAP because the items that would be included or excluded are difficult to predict and estimate and are primarily dependent on future events, including costs relating to the acquisition of Linear.

Applied Materials, Inc. today announced Thomas J. Iannotti as chairman of the Board of Directors effective immediately. Mr. Iannotti succeeds Willem P. Roelandts, who has retired from the board. Mr. Iannotti joined Applied’s board in 2005. Prior to being named chairman, he served as chair of the board’s Human Resources and Compensation Committee and was a member of the Corporate Governance and Nominating Committee.

A veteran of the electronics industry for more than three decades, Mr. Iannotti is known for his global business, industry and operational expertise. He spent nine years as an executive at Hewlett-Packard Company, including Senior Vice President and General Manager, Enterprise Services from 2009 to 2011. Prior to Hewlett-Packard, Mr. Iannotti worked at Digital Equipment Corporation, a vendor of computer systems and software, and at Compaq Computer Corporation, a supplier of personal computing systems, after its acquisition of Digital Equipment Corporation.

“As a member of the Applied board, I have been inspired by the company’s ability to push the boundaries of technology and create innovations that drive the semiconductor and display industries forward,” said Mr. Iannotti. “I am honored to serve as chairman and would like to thank Wim Roelandts for his many contributions to Applied and the semiconductor industry during his remarkable career.”

“Tom brings deep knowledge of Applied, as well as strong industry and governance experience, to lead the board during one of the most exciting periods of innovation and growth in our company’s history,” said Gary Dickerson, president and CEO. “On behalf of everyone at Applied Materials, I thank Wim for his longtime service as a member of the board and for his leadership as chairman.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced the availability of a key technology in virtual prototyping which enables architecture performance requirements to be easily shared through the supply chain. The latest release of its Platform Architect solution introduces new Task Graph Generator (TGG) technology, which automatically extracts key performance characteristics from software applications to enable architecture exploration to optimize performance and power for next generation multicore system-on-chips (SoCs). TGG enables system architecture teams to more easily share accurate application workload models with their semiconductor suppliers, enabling much more efficient collaboration in the supply chain.

“To address growing software content, the use of multicore architectures in automotive electronic systems is increasing,” said Takashi Abe, project manager, Basis Electronics R&D Division at Denso. “Using the TGG capability in Platform Architect, we are able to capture the key characteristics of our existing software and derive the performance of next generation multicore architectures with high accuracy. By applying this approach early in the planning phase, we are able to ensure that system specifications will meet the demanding performance requirements of these applications.”

Using Platform Architect, semiconductor suppliers can define the architecture specification for next generation SoCs based on the software application requirements from their system customers. System designers can map a software workload model generated by TGG, called a task graph, to the processing resources in the SoC. This allows them to explore, analyze and optimize the performance and power of next generation multicore SoC architectures very early in the development cycle. And, because task graphs are abstract workload models and not the actual software, systems design teams can more easily share them with their semiconductor suppliers as executable specifications, benefiting collaboration in the supply chain.

TGG is application profiling technology that takes software execution traces as its input. By running the application program of interest on an existing system, designers can record their input using a supported TGG format, including:

  • OS-level traces for programs executing on any Linux, Android, and QNX based system, including existing hardware devices
  • Function-level traces for programs executing on x86 based systems (Windows or Linux), using the Pin instrumentation tool from Intel, and on ARM-based systems using Synopsys Virtualizer Development Kit (VDK) virtual prototypes or ARM® DS-5 Development Studio

TGG analyzes the execution trace to extract the processing and communication requirements of the application of interest, including task level parallelism and dependencies, processing cycles per task, and read/write memory accesses, to generate the resulting task graph workload model for performance analysis and benchmarking of new architectures in Platform Architect.

“Delivering the right balance of performance and energy efficiency is critical to avoid under- and over-design,” said Eshel Haritan, vice president, virtual prototyping R&D for the Synopsys Verification Group. “With Task Graph Generator in Platform Architect, system designers gain a realistic, system-level benchmark view of critical SoC applications, enabling system design teams to explore and optimize the performance and power of their new architecture months before final hardware and software are available, reducing risk and improving results.”

Kateeva today announced that it is expanding its Silicon Valley headquarters. The company has leased an adjacent building at its Newark campus, adding 75,000 sq. ft. that is zoned for manufacturing and business operations. This brings Kateeva’s total campus footprint to 150,000 sq.ft. Kateeva moved to its current location in early 2015 to facilitate production ramp-up of its YIELDjet inkjet printing manufacturing equipment for the global flat panel display industry. Since then, headcount has nearly tripled to 330 people, and orders for YIELDjet systems have soared. With the new building, Kateeva’s doubles its manufacturing footprint, providing ample space to accelerate production.

Leading flat panel display manufacturers use Kateeva’s precision deposition equipment for cost-effective mass production of Organic Light Emitting Diode (OLED) displays. OLED technology is behind some of today’s most popular smartphones and tablets. Already, OLED screens curve around edges to enable unique form factors. Soon, when tablets, notebooks and smartphones can bend, roll and even fold without breaking, it will be thanks to OLED technology. OLED technology enables the production of displays on plastic (entirely free of glass), making them flexible and paper-thin.

Kateeva’s YIELDjet FLEX system for OLED TFE mass production

Kateeva’s YIELDjet FLEX system for OLED TFE mass production

Kateeva’s first product, the YIELDjet FLEX system, enabled a rapid transition from glass encapsulation to Thin Film Encapsulation (TFE) in new OLED production lines. The “freedom from glass” technology leap was the gateway to flexible displays. Each Kateeva inkjet printer is highly customized and built to extremely exacting specifications. Measuring approximately 2,000 sq.ft., the tool contains thousands of precision parts, and is differentiated by myriad innovations that are protected by 200 issued and pending patents. With the system, customers can achieve dramatically higher TFE yields and lower mass-production costs than what was previously possible with other deposition techniques. On an OLED mass-production line, Kateeva printers work in concert with tools from other leading equipment companies to process the panels.

Kateeva’s tools are designed and engineered in Newark, so the expansion will support the company’s growing R&D team. In addition, since Kateeva manufactures a majority of its products and components in Newark, the expansion will also support a large increase in its U.S. manufacturing capacity.

Kateeva’s President and Co-founder, Dr. Conor Madigan noted: “Kateeva’s manufacturing strategy utilizes a balance of production in Asia, as well as the U.S. This dual-region strategy generates optimum efficiencies and will continue as we grow. For now, our most complex and customized products will be built at our Newark facility where we can leverage our adjacent manufacturing and engineering teams to maintain highest quality while also satisfying our customers’ aggressive delivery timelines. This is far more difficult to achieve when our manufacturing and engineering teams are separated and remote. Building these products in the U.S. also helps us safeguard the intellectual property that differentiates our technology solution.”

Madigan listed other advantages of Kateeva’s newly expanded Newark HQ: “By obtaining an adjacent building we can maintain the operating efficiencies of a single site,” he said. “Also, in Newark we’re next door to several international airports, which is imperative for a manufacturer of capital equipment bound for production fabs in Asia. Finally, our location situates us ideally to draw talent from all regions in and around Silicon Valley.”

ClassOne Technology, manufacturer of wet processing equipment for 200mm and smaller wafers, announced that Scientech Corporation of Taipei, Taiwan, will become the company’s new representative for China, Taiwan and Southeast Asia, starting immediately.

“Asia is an extremely active and important region for us,” said Byron Exarcos, President of the ClassOne Group. “We wanted a respected and thoroughly experienced sales and support operation there, and Scientech filled the bill perfectly. They have all the necessary infrastructure and well-established field service teams, having served the industry for over three and a half decades — including many years representing Semitool. We’re proud and delighted to now have them on the ClassOne team.”

“We’re very impressed by the rapid success ClassOne has been achieving, bringing high-performance wet processing solutions to the emerging markets — with more than 100 tools already installed across the U.S. and Europe,” said M.T. Hsu, President of Scientech Corporation. “It’s great to represent products that are in high demand, and we’re looking forward to helping expand ClassOne’s presence in Asia.”

Scientech Corporation was established in 1979 and has headquarters in Taipei, Taiwan, with five additional offices across Taiwan and Shanghai. Scientech will provide full sales, installation, service, parts, process development assistance and technical support for all ClassOne Technology equipment — including the Solstice family of electroplating systems and the Trident® families of Spin Rinse Dryers and Spray Solvent Tools.

ClassOne stated that the company’s mission is to provide advanced wet processing performance at an affordable price for users of 200mm and smaller substrates. Many of these users are in budget-limited emerging markets producing a range of devices such as MEMS, LEDs, RF, power and sensors. ClassOne’s pricing is often less than half that of similarly configured 300mm systems outfitted for 200mm from the large manufacturers — which is why ClassOne tools have been described as delivering “Advanced wet processing for the rest of us.”

The Semiconductor Industry Association (SIA) today announced the addition of two leading U.S. semiconductor companies, Skyworks Solutions, Inc. (NASDAQ:  SWKS) and Western Digital Corporation (NASDAQ: WDC), as SIA members. Skyworks Executive Chairman and Chairman of the Board David Aldrich and Western Digital CEO Steve Milligan are expected to be elected to the SIA board of directors at the association’s next board meeting on March 8. SIA previously announced the heads of two additional new SIA member companies, IDT President & CEO Greg Waters and Marvell President & CEO Matt Murphy, are also expected to be elected to the SIA board tomorrow. Additionally, GLOBALFOUNDRIES, Inc. CEO Sanjay Jha will replace Ajit Manocha on the SIA board.

“The addition of Skyworks and Western Digital as SIA members shows growing momentum for collaboration among key semiconductor leaders to shape public policies that impact our industry,” said John Neuffer, SIA President and CEO. “Each new SIA member adds their voice to the industry’s collective call for initiatives that foster growth and innovation. These include making the U.S. tax system globally competitive, investing in university-based basic research, expanding access to global markets, and strengthening America’s tech workforce.”

Aldrich has served as Chairman of the Board at Skyworks since May 2014. Prior to his appointment as Executive Chairman in May 2016, he served as CEO since the company was formed in 2002 via a merger between Alpha Industries and Conexant Systems’ wireless business. Before the creation of Skyworks, he served as President and CEO of Alpha Industries, a position he held since April 2000. He joined Alpha Industries in 1995 as Vice President and Chief Financial Officer and held various management positions in the ensuing years, including president and Chief Operating Officer. Prior to this, he held senior management positions at Adams-Russell and M/A-COM. Mr. Aldrich received a bachelor’s of arts in political science from Providence College in 1979 and a master’s in business administration from the University of Rhode Island in 1981.

“It is a true pleasure to represent Skyworks on the SIA board of directors at an exciting and pivotal time for our industry,” said Aldrich. “I look forward to working in concert with my colleagues to advance the semiconductor industry’s interests in Washington, D.C. and in capitals around the world.”

Milligan re-joined Western Digital as President in March 2012 and was appointed CEO effective Jan. 2, 2013. Immediately prior to returning to Western Digital, Milligan was President and CEO of Hitachi Global Storage Technologies (Hitachi GST). During his tenure, Milligan led Hitachi GST through a financial and operational turnaround culminating in Western Digital’s acquisition of Hitachi GST in March 2012. Prior to joining Hitachi GST in 2007, Milligan was Western Digital’s Senior Vice President and Chief Financial Officer. He originally joined Western Digital in 2002 as Vice President, Finance. Milligan holds a bachelor’s degree in accounting from the Ohio State University.

“The IT landscape is transforming as rapidly as it ever has, and the semiconductor industry plays a critical role in defining its course,” said Milligan. “Industry participants must work together in support of our common goals, and I look forward to collaborating with other industry leaders through SIA to make meaningful progress on issues of great importance to us all.”

Cypress Semiconductor Corp. (Nasdaq:  CY) today announced it has sold the subsidiary that owns its semiconductor wafer fabrication facility in Bloomington, Minnesota to SkyWater Technology Foundry for $30 million. Backed by Minnesota-based holding company Oxbow Industries, LLC, SkyWater Technology has purchased the capital stock of the subsidiary and will operate the fab as a standalone business that will manufacture wafers for Cypress and for other semiconductor manufacturers. The transaction allows Cypress to reduce its manufacturing footprint and cost structure while increasing the utilization of its Fab 25 in Austin, Texas, in line with the company’s plan to improve gross margins. Seattle-based ATREG, Inc. acted as Cypress’ advisor in this operational fab sale.

“This transaction demonstrates our commitment to reshape Cypress and improve gross margin, in line with our long-term financial model,” said Hassane El-Khoury, Cypress President and CEO. “The sale of Fab 4 in Minnesota allows us to reduce our manufacturing costs as we exit the fab while using the proceeds to pay down debt. We will also be able to improve the utilization and efficiency of Fab 25 in Texas, into which we have been transitioning products over the last 18 months. We believe this agreement represents another milestone in our path to achieving higher gross margins.

“In addition to looking at a potential deal’s impact on Cypress’ bottom line, we set out to ensure uninterrupted supply for our customers,” continued El-Khoury. “This agreement allows Cypress to maintain uninterrupted wafer supply for our products manufactured at the fab, with no disruptions for our customers, and it gives our former employees in Minnesota the opportunity to help the new business flourish and continue the fab’s tradition of quality U.S.-based manufacturing.”

“Given the proven history of efficiency at Fab 4, the expertise and dedication of its workforce and its established success in delivering specialized wafers on time to a diverse customer base, the SkyWater management team sees a strong foundation for growing a standalone business,” said Dr. Scott Nelson, Chief Technology Officer of SkyWater Technology Foundry. “We are committed to continuing the fab’s support of Cypress and its customers with superior quality and on-time delivery.”

Technavio analysts forecast the global carbon nanotube (CNT) market to grow at a staggering CAGR of almost 22% during the forecast period, according to their latest report.

The research study covers the present scenario and growth prospects of the global CNT market for 2017-2021. To calculate the market size, the report considers the revenue generated from the sales of CNTs worldwide.

The production capacities of CNTs will expand due to their growing demand. Factors such as the need to enhance the efficiency of electronic and semiconductor products, high use of CNTs in the aerospace and defense sectors, and the need to increase the efficiency of energy-sector-related devices are driving the market.

Technavio’s sample reports are free of charge and contain multiple sections of the report including the market size and forecast, drivers, challenges, trends, and more.

Technavio hardware and semiconductor analysts highlight the following three factors that are contributing to the growth of the global CNT market:

  • Advantages due to physical properties
  • Potential to replace other materials
  • Rise in production capacities

Advantages due to physical properties

The structure of CNTs is closely related to graphite, which is traditionally made by stacking sheets of carbon on top of another. These sheets can easily slide over each other. CNTs are made by rolling these sheets into a cylinder, with their edges joined. This structure offers extraordinary electrical, mechanical, optical, thermal, and chemical properties to CNTs.

Sunil Kumar Singh, a lead embedded systems analyst at Technavio, says, “Being a carbon-based product, CNTs are not vulnerable to environmental or physical degradation issues. Due to this advantage, CNTs are in high demand and are used in multiple applications such as medicine, aerospace and defense, electronics, automotive, energy, construction, and sports.”

Potential to replace other materials

CNTs have the potential to replace the key materials in some industries such as semiconductor and energy. Research centers are developing CNTs that can be used in solar cells as an alternative to silicon, which is the key material used in producing electricity from solar energy. By using CNTs instead of silicon, the conversion efficiency of solar cells can be enhanced.

“CNTs have the potential to replace indium-tin-coated films, which are fragile and expensive. These films are used in liquid crystal displays, solar cells, organic light-emitting diodes, touchscreens, and high-strength materials like bulletproof vests and hydrogen fuel cells used to power cars,” adds Sunil.

Rise in production capacities

Production capacity for CNTS for 2015 was 4,567 metric tons globally. MWCNT dominates this market space due to its low production cost and high-scalability. Whereas, SWCNT still has issues with scaling up the volume produced and reduced the cost. Techniques available for CNT production such as substrate-free growth and substrate-bound growth while deploying vapor-solid-solid (VSS) and vapor-liquid-solid (VLS) are widely adopted for catalyst-based synthesis.

Many CNT vendors are investing heavily in new production facilities to meet the growing demand from sectors such as consumer goods, electrical and electronics, energy, healthcare, automobile, and aerospace and defense. Among countries, China has increased the production of CNTs backed by high government funding for nanomaterials.

Semiconductor manufacturing thought leaders will convene at the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2017) on May 15-18 in Saratoga Springs, New York. The conference will feature 35 hours of technical presentations and over 100 experts addressing all aspects of advanced semiconductor manufacturing. This year’s event features a panel discussion on “The Next Big Thing: Technology Drivers for Next-Gen Manufacturing − Where will the Road take Us?” and a tutorial on Piezoelectric MEMS by Professor Gianluca Piazza, director of Nanofabrication Facility, Carnegie Mellon University.

SEMI‘s ASMC continues to provide a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  The conference is co-chaired by Delphine LeCunff of STMicroelectronics and Russell Dover of Lam Research.  ASMC 2017 offers keynotes by Roberto Rapp, VP of Manufacturing at Robert Bosch GmbH; William Miller, VP of Engineering of Qualcomm; and Robert Maire, president of Semiconductor Advisors.

The topical areas that ASMC 2017 will address include:

  • 3D and Power Technologies
  • Advanced Equipment and Materials Processes
  • Advanced Metrology
  • Advanced Patterning
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Yield Management; Defect Inspection
  • Equipment Reliability and Productivity Enhancement
  • Factory Optimization

ASMC includes an interactive poster session and reception, which provides an ideal opportunity for networking between presenters and conference attendees.

The new ‘Women in Semiconductors‘ program takes place on May 15 in conjunction with ASMC 2017.  Sponsored by Applied Materials, GLOBALFOUNDRIES, IBM, Nikon and TEL, the program will focus on “The Power of Talk: Getting a Seat at the Table.”  Registration is complimentary for ASMC attendees.

ASMC 2017 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT). Corporate sponsors include: BisTEL, Edwards, GreeneTweed, KLA-Tencor, Mellor Consulting Group, Nikon, and Valqua America.

Registration for the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is available at www.semi.org/asmc.  For more information, contact Margaret Kindling at [email protected] or phone 1.202.393.5552. Qualified members of the media are invited to contact Deborah Geiger (SEMI Public Relations) at [email protected] for media registration information.

Today, FlexTech, a SEMI Strategic Association Partner, announced the agenda for 2017FLEX Japan, the first flexible hybrid electronics (FHE) conference in Tokyo on April 11-12. More than two hundred attendees are expected to participate from the international FHE community and adjacent industry sectors including semiconductor, sensors, and printed electronics industries. Japanese-English simultaneous translation will be available in all sessions of the conference. The event is based on the same format as the 15 year-old FLEX Conference events in the U.S., Europe, and Southeast Asia.  Registration is now open for 2017FLEX Japan.

FHE is the leading technical approach to design and manufacture devices for fast growth markets including IoT, environmental sensing, wearable applications, flexible displays and other conformable and low profile applications. 2017FLEX Japan includes four sessions on critical areas for FHE success:

  • FHE / Printed Electronics – addresses latest technical developments on flexible electronic components including, substrates, printed communication, processing, power and displays
  • IoT Applications – covers new applications for FHE in home security, retail and distribution, and industrial IoT
  • Sensors – provides updates on integrating sensors into FHE systems
  • Smart Textiles – focuses on design of stretchable, twistable FHE components

The four sessions will feature 16 technologists and experts from Japan, Americas, Asia and Europe representing organizations and academia active in the FHE area, including:

  • Tohoku University: Masayoshi Esashi, professor, Micro System Integration Center
  • AIST: Toshihide Kamata, director, Flexible Electronics Research Center
  • Google: Kelly Dobson, research leader, Advanced Technology and Projects Group
  • SECOM: Tsuneo Komatsuzaki, managing executive officer, director of Intelligent System Laboratory
  • Cornell University: Juan Hinestroza, associate professor of Fiber Science, Department of Fiber Science and Apparel Design
  • U.S.A. Air Force Research Laboratory: Michael F. Durstock, chief, Soft Matter Material Branch

The two-day program also includes a table top exhibition and a reception to facilitate business developments and technology collaboration.

To learn more about the event, visit 2017FLEX Japan website at: www.semi.org/jp/node/73811/