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DSI announced today that ON Semiconductor has selected DSI’s Digital Supply Chain Platform (DSCP) to increase stock accuracy and improve worker productivity in its inventory processes across the global supply chain.

ON Semiconductor is a leading producer of semiconductors globally. The company chose the DSI DSCP for its unique ability to expand upon base ERP system functionality and work on- or offline through a certified, validated integration with its Oracle E-Business Suite (EBS) system. ON Semiconductor will deploy DSI’s mobile-first supply chain apps personalized by location and user, integrated with the company’s backend systems and business processes.

DSI will enable ON Semiconductor to manage parts used and product use-by dates in real time. The DSCP will automate the data capture process of moving materials while creating built-in measures that ensure the right chemicals are used on equipment. DSI’s automated validation of materials is expected to reduce costs associated with applying incorrect or expired materials.

Additionally, ON Semiconductor will gain efficiency and accuracy by filling gaps in functionality within its ERP system. The DSCP will enable ON Semiconductor’s employees to capture multiple pieces of data in a single scan and immediately update the backend system. The ability to extract multiple pieces of data in a different manner for each specific supplier will also help ON Semiconductor to speed the receiving process.

The speed with which the DSI platform scans, interprets and records the information will enable ON Semiconductor to have a single solution to improve efficiency across all its global operations, scanning 400% faster than the current solution. With this implementation, DSI will replace the company’s current solution, which was unable to perform at the required speed.

“The ability to perform whether online or disconnected was a key factor in selecting DSI,” said Fred Le Roy, Operations Manager, ON Semiconductor. “Having an app that continues to work offline protects the quality of our data and lets our personnel work efficiently in any environment.”

The speed and accuracy ON Semiconductor will be able to gain through the DSI platform will deliver benefits to production quality and efficiency as well as operational health and safety. The DSI solution enables mobile barcode scanners to work equally efficiently connected and disconnected. Switching seamlessly between both states ensures 100% data accuracy.

“Our customers choose DSI for a personalized user experience in enterprise-grade mobile apps that perform anywhere, on any device,” said Mark Goode, Chief Revenue Officer, DSI. “We look forward to working with ON Semiconductor to continue improving visibility and efficiency across its global supply chain with the Digital Supply Chain Platform.”

Solid particles in the abatement exhaust must be properly managed, and in some cases, substantially reduced from the gas stream before it is released into the environment.

BY CHRIS JONES, Edwards Vacuum, Ltd., Clevedon, U.K.

Many semiconductor manufacturing processes create solid particles in the process exhaust. Like other exhaust contaminants, these must be properly managed, and in many cases, removed from the stream before it is released into the environment. The permitted release levels vary for particles of different sizes and compositions, depending on their toxicity or potential to damage the environment. Regulations governing particle releases are evolving rapidly. However, the management of particulate flows in process exhaust is also important due to its potential impact on the process itself. Left unmanaged, particulate accumulations can result in shut downs for unplanned maintenance, excessive and premature wear and costly repairs, all of which directly affect the profitability of the manufacturing operation.

Solids may be formed in the exhaust stream of a semiconductor manufacturing process from a number of sources. One important source, though not the focus of this discussion, is the condensation of process gases in vacuum pump exhausts. If not controlled with a thermal management system (e.g. Smart TMS, Edwards) that maintains the pipe surfaces at a sufficiently high temperature, this condensation can quickly accumulate and force a halt to the manufacturing process. This article will discuss issues further downstream in the abatement process, where toxic volatile compounds are converted to more benign forms, some of which form solid particles that must then be removed from the exhaust gases. Many of these solids are oxides formed when gases, such as tungsten hexaflu- oride, silane, organo- and halo- silanes and others, are exposed to heat, air, and water. The particles are typically amorphous, i.e. non-crystalline. Many abatement processes use combustion to supply the heat needed to decompose toxic compounds and chemically convert them to a more harmless form. The particles thus formed have varying sizes and may be hydrophilic (formed from halosilanes), hydrophobic (formed from organsilanes) or mixed (mixed chlorides or silicon, aluminum and boron, for example), depending on the species combusted and the nature of the combustion process. Particle sizes can range from tens of nanometers to tens of microns. As shown in FIGURE 1, the size of the particles depends on, among other factors, the length of the combustion flame. Longer flames maintain the components at high temperature for a longer periods and result in the formation of larger particles.

FIGURE 1. A longer flame maintains the combusting components at higher temperature for a longer time and results in the formation of larger particles.

FIGURE 1. A longer flame maintains the combusting components at higher temperature for a longer time and results in the formation of larger particles.

The behavior of particles once released into the environment varies depending on their sizes. Coarse particles, with diameters ranging from 2.5μm to 10μm, result largely from processes such as erosion, agriculture, or mining and include crustal dust, pollens, fungal spores, biological debris and sea salt. Because of their large size, these particles persist in the atmosphere for only a few hours or days. Fine particles, which range from 2.5μm to 0.1μm and include the particles of concern in semiconductor manufacturing exhaust, may be the direct result of a combustion processes or may also be formed by photochemical reactions between volatile organic compounds (VOC) and oxides in the presence of sunlight. Fine particles can stay suspended in ambient air for days to weeks. Ultrafine particles, less than 0.1μm, are generated by high temperature combustion or formed from the nucleation of atmospheric gases. Ultrafine particles are quickly removed from the atmosphere (minutes to hours) via diffusion to surfaces or coagulation, adsorption and condensing into fine particles.

Regulatory environment

Regulations governing the release of particles into the atmosphere are developing quickly worldwide as scientists expand their knowledge of the particles’ impacts on health and the environment. In addition to regulations governing emissions by particle size, there are specific regulations regarding especially harmful species, such as heavy metals, carcinogens and toxics. For example, the presence of an adsorbed species, like hydrofluoric acid (HF), on oxide particles increases the toxicity of the parent material.

In 2013 the United States Environmental Protection Agency specified an average daily limit of 150μg/m3 for coarse particles and 35μg/m3 for fine particles, and an average annual limit of 12μg/m3 for fine particles (down from 15μg/m3 in 2006). China, as of 2012, imposed limits based on both particle size and type, with permitted daily levels for coarse particles of 50μg/m3 and 150μg/m3 for type I and type II, respectively and 35μg/m3 and 75μg/m3, respectively for fine particles. China also limits annual averages for both sizes and types. The European Commission, the World Health Organization and the Australian National Environmental Council, among others, all specify their own limits. It is clearly incumbent on manufacturers to know and satisfy their local regulations. [1]

Health considerations

The health of employees in manufacturing facilities and people living near manufacturing operations is clearly a high priority for our industry. Epidemiological studies have provided plausible evidence that exposure to particulate material (PM) can impact health in a number of ways, including pulmonary and systemic inflammation, oxidative stress response, protein modification, stimulation of the autonomic nervous system, exaggerated allergic reactions, pro-coagulation activity, and suppression of immune response in the lungs.

Some studies have provided good news as well, specifically, that the amorphous silica particles produced during the abatement of gases used in semiconductor manufacturing have much less impact on lung function than the crystalline silica particles more often encountered in mining and building industries. These studies looked specifically at the effects of pure silica particles, an important caveat. Silica and other dusts that may have acids, such as HF, adsorbed on the particle surface constitute substantially greater health risks than the simple oxide. Other particulate oxides also represent serious health challenges. These include oxides of antimony, arsenic, barium, chromium, cobalt, nickel, phosphorus, tellurium and selenium.

Abatement performance

Just as condensed material deposited in the vacuum lines can shut down the production process, the accumulation of combustion-generated particulates can degrade the performance of the whole facility. In a typical point-of-use (POU) abatement system, after combustion the exhaust gases pass through a series of operations designed to remove particulates and other by-products. In the example shown in FIGURE 2 these include a water weir, quench tanks, a packed-bed scrubber and an atomized spray. Atomizing spray systems, in particular, have been shown to improve solids removal performance from 50 to 75 percent. Blockages can occur at the damper, in duct spurs leading from the abatement to the main duct, in the main duct, before or within the scrubber. In addition to blockages, failure to remove particulate at the primary abatement unit can also lead to environmental discharges and visible plumes at stacks. Any blockage will result in a process shutdown for system maintenance, lasting from a few hours to an entire day.

FIGURE 2. The accumulation of combustion generated particulates can degrade abatement system performance.

FIGURE 2. The accumulation of combustion generated particulates can degrade abatement system performance.

Mitigation options

A number of approaches exist for removing particulates downstream of the abatement system. One solution does not fit all and it is important to pick the one that best addresses the specific challenges. FIGURE 3 shows performance characteristics for various technologies. For example, highly toxic particles may require much higher removal rates than less harmful particles.

FIGURE 3. Performance characteristics for various particle removal technologies downstream of the abatement system. Courtesy: Waste-to-Energy Research and Technology Council (greyed out area not relevant to solids).

FIGURE 3. Performance characteristics for various particle removal technologies downstream of the abatement system. Courtesy: Waste-to-Energy Research and Technology Council (greyed out area not relevant to solids).

Edwards’ standard solution (FIGURE 4) for POU removal of fine particles is a wet electrostatic precipitator (WESP). A WESP uses electrostatic forces to remove particles. It requires power, water and pneumatics and can remove up to 95 percent of silica particles at flow rates of 1m3/ min, 85% at 2m3/min. WESP technology can be scaled to handle an entire facility. In one example, Edwards partnered in the installation of a large scale dual WESP integrated with a packed-bed wet scrubber and designed it to meet the specific challenges of arsenic abatement. The system ultimately demonstrated a 99 percent removal rate to meet the stringent requirements of the Chinese government for this highly toxic substance.

FIGURE 4. POU WESP uses electrostatic forces to remove particulates from the exhaust stream. It can remove up to 95 percent of silica particles at a flow rate of 1m3/min.

FIGURE 4. POU WESP uses electrostatic forces to remove particulates from the exhaust stream. It can remove up to 95 percent of silica particles at a flow rate of 1m3/min.

Alternative technologies that may be appropriate, but have not been evaluated for use in the management of waste gases from semiconductor manufacturing, are the Rotoclone family (from AAF International). POU units handle flow rates of 30m3/min, removing >97 percent of 1μm particles and >99.8 percent of 10μm particles. Duct-based Rotoclones with flow rates up to 1250m3/ min remove as much as 86 percent of 1μm particles and 99 percent of 10μm particles. Rotoclones require power, water, pneumatics and a drain.

More conventionally, a Venturi scrubber can be configured for various flow and removal rates. As a rule, smaller units controlling a low concentration waste stream will be much more expensive per unit of volumetric flow than larger units cleaning high pollutant-load flows. Venturi scrubbers can handle mists and flammable or explosive dusts. They have relatively low maintenance requirements, are simple in design and easy to install. Their collection efficiency can be varied. They can cool hot gases and neutralize corrosive gases. They are susceptible to corrosion and must be protected from freezing. Treated gases may require reheating to avoid a visible water plume. The collected particulate material may be contaminated and not recyclable, requiring expensive disposal of the waste sludge.

Filtration is another alternative for particle removal. It is normally restricted to the management of dry dusts at flow rates of 5 to 250m3/min. Removal rates higher than 99.9 percent are achievable. We have seen a limited number of large filter installations for the removal of hydrophobic silica solids at relative humidities as high as 80 percent. It is not clear how the presence of hydrophilic powder might impact the performance of these facilities.

In cases of highly toxic particles, high efficiency air particle (HEPA) filters can provide very high removal rates, higher than 99.999 percent. However, HEPA filters are appropriate only for very low contaminant concentrations. Edwards has been partnering with third-party suppliers regarding HEPA filtration for highly toxic dusts such as those generated during arsine management. These solutions are often used for highly toxic materials so they are often designed with bag-in-bag-out capability to eliminate potential exposure of maintenance personnel to the removed contaminants. Typically, these critical installations are also designed as dual systems with auto turnover to allow continuous operation of one system while the redundant system is serviced. HEPA technology can scale from POU to full facility.

Conclusion

All of these technologies are available now, but not all have been demonstrated in semicon- ductor manufacturing. Semiconductor manufacturers have long used POU WESPs and Venturi scrubbers and are very familiar with HEPA filtration systems, but primarily for particulate removal for air conditioning. Conventional filters are in operation on flat panel display exhausts (mainly on burner only dry abated CVD processes). Some of the technologies we have described, however, have not been proven in semiconductor applications, but are well developed and widely accepted in other industries. Rotoclone systems, for instance, are UL and CE certified, but have not been SEMI qualified. As semiconductor manufacturing processes continue to evolve, it will behove manufacturers to stay current on available technol- ogies and consider alternatives as performance and cost requirements dictate.

References

1. Review of the health impacts of emission sources, types and levels of particulate matter air pollution in ambient air in NSW; December, 2015; Produced for the NSW Environment Protection Authority and NSW Ministry of Health, Environmental Health Branch.

Analog Devices, Inc. (NASDAQ: ADI) today announced the acquisition of Innovasic Inc., a provider of Deterministic Ethernet semiconductor and software solutions. The acquisition adds a suite of multiprotocol Industrial Ethernet solutions and key enabling technologies to ADI’s Smart Automation Solutions portfolio for industrial automation and Industrial Internet of Things (IoT).

With the industrial automation market already transitioning from serial fieldbus to Ethernet connectivity, and with the simultaneous push toward a ubiquitous Industrial IoT, there is a clear need for highly reliable, real-time Ethernet connectivity for sensitive industrial automation applications. The acquisition of Innovasic will give ADI customers immediate access to a set of innovative solutions for today’s Industrial Ethernet applications while also creating a best-in-class roadmap for future connectivity needs like Industrial IoT. These solutions will complement ADI’s existing high-performance Industrial Automation solutions, including Software Configurable IO, Field Instruments, and efficient servo drives.

“In environments such as automotive manufacturing, where teams of robots are working in tandem in harsh and noisy conditions, our automation customers demand robust, synchronized, network technology,” said Kevin Carlin, General Manager of ADI’s Automation Business Unit. “These customers also strive to achieve the efficiency and cost improvements promised by wider deployment of Ethernet with the upcoming Industrial IoT. The IEEE has recognized that new standards will be required to enable Ethernet to meet the determinism demands for these emerging applications and is developing the new Time Sensitive Networks (TSN) standards. Innovasic technology not only addresses today’s Industrial Ethernet, but has also been demonstrated to address some of the early requirements of these new IEEE TSN standards. With this acquisition, ADI is now able to offer its customers a path forward from the sensor to the connected future of Industrial IoT.”

The Innovasic team will join ADI’s Industrial Automation Business Unit and operate as a key technology group, developing the company’s Deterministic Ethernet technology solutions and continuing to supply industrial customers with its portfolio of long life-cycle semiconductors. The team will be led by Jordon Woods, Innovasic’s co-founder and COO, and continue to be based in Albuquerque, New Mexico.

“We are excited to become part of Analog Devices and its ‘Smart Automation’ solution set,” said Woods. “Innovasic and ADI have both pursued solutions to customers’ most challenging technical problems while committing to maintain long product life cycles to meet the unique requirements of the industrial market. Together, we will be able to effectively and efficiently solve the communications needs of customers serving the most demanding industrial automation environments on the planet.”

The Global Semiconductor Alliance (GSA) announced the winner of the 2016 Dr. Morris Chang Exemplary Leadership Award: President and CEO of Cadence Design Systems, Inc. and Founder and Chairman of Walden International, Mr. Lip-Bu Tan. He will be presented with this achievement award during the GSA Awards Dinner Celebration on Thursday, December 8, 2016, at the Santa Clara Convention Center in Santa Clara, Calif.

“Lip-Bu Tan epitomizes what the Dr. Morris Chang Exemplary Leadership Award encompasses,” said Jodi Shelton, president of GSA. “We are honored to present this year’s award to someone who is a true global technology visionary that first helped pioneer the concept of venture capitalism worldwide and then lead Cadence Design Systems to the success, growth and strong customer focus that it enjoys today. Tan’s contribution to GSA and the entire semiconductor industry has and will continue to make a lasting impact.”

Established in 1999, the first GSA “Exemplary Leadership Award” was given to Dr. Morris Chang, chairman and chief executive officer of Taiwan Semiconductor Manufacturing Corporation (TSMC). Today, the Dr. Morris Chang Exemplary Leadership Award recognizes individuals for their exceptional contributions, exemplifying how their vision and global leadership have transformed and elevated the entire semiconductor industry.

“I am extremely honored and humbled to receive this award named after my close friend and role model Morris Chang, and which has been bestowed earlier on many amazing pioneers in our industry,” said Lip-Bu Tan. “I have learned so much from my peers in the global semiconductor industry and it has been my privilege to contribute in some way to their success through investments by Walden and collaboration by Cadence, leading to the delivery of some truly inspiring end products.”

Tan has served as President and CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. In 2015 and 2016, Cadence was named to FORTUNE’s list of the “100 Best Companies to Work For”. Tan founded Walden International in 1987 and currently serves as Chairman. Tan has been active in the venture capital industry for more than two decades. He specializes in cross border & early-stage technology investment. Prior to Walden International, he was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.

Tan is Co-Chairman of the Board of Directors of the Electronic System Design Alliance (ESD Alliance) and serves on the board of Global Semiconductor Association (GSA), as well as the boards of Ambarella Inc., Hewlett Packard Enterprise Co., and Semiconductor Manufacturing International Corp. He also serves on the Board of Trustees and the School of Engineering Dean’s Council at Carnegie Mellon University (CMU).

Tan holds an M.S. in Nuclear Engineering from Massachusetts Institute of Technology, an M.B.A. from the University of San Francisco, and a B.S. in Physics from Nanyang University in Singapore.

Each year the GSA recognizes companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. The celebration honors the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry. The Awards Dinner Celebration will start at 5:00 p.m. with a networking reception, followed by dinner at 6:15 p.m. To make reservations to attend the Awards Dinner, visit the event website.

Kateeva, the OLED production equipment developer, today announced the appointment of Mark R. Shaw, Ph.D. as Senior Vice President of Human Resources (HR). Previously, Shaw worked at Lam Research and Applied Materials. He joins Kateeva at a time of rapid growth. He’ll build a comprehensive HR infrastructure to support the company’s accelerating global business, with strategic initiatives to attract, inspire and reward top talent, world-wide.

Shaw has spent 25+ years driving transformational HR programs at multi-billion-dollar capital equipment companies with global operations, multiple product lines, and thousands of employees. Over time, he has led multi-national teams in shaping and executing HR solutions to support myriad corporate transactions and significant change events. This included: establishing HR organizations for multiple joint ventures in the US, Asia and Europe; developing comprehensive executive leadership and workforce strategies for new regional markets; unifying compensation programs across multiple geographies, and driving successful M&A integrations with practical change-management protocols.

“Few candidates know the business of leveraging people-power to support a fast-growing, global hardware company as thoroughly as Mark,” said Kateeva President and COO, Conor Madigan. “At Lam Research and Applied Materials, he navigated major events and complex global interactions, offering innovative and thoughtful HR solutions to maximize success outcomes for his employer and fellow employees. With our market trajectory already presenting similar growth events for Kateeva, we’re thrilled that Mark will lead the effort to build a talent-optimization infrastructure to help us expertly harness the opportunities.”

For Shaw, the new role is a unique opportunity to apply HR best-practices that made his previous employers rewarding workplaces. “In its short life, Kateeva has already achieved the near-impossible by commercializing a disruptive OLED-enabling technology that catapulted to market leadership in under two years. The same DNA behind that success will soon propel the company into new markets. For me, that means designing and implementing agile strategies that embolden the culture without sacrificing the entrepreneurial vibe that fueled the successes. I’m excited to accept the challenge.”

Shaw joined Kateeva from Lam Research where he was Vice President of HR for sales, service and manufacturing. He led organization and talent initiatives that included succession, employee development, sales capability, and field technical resources. Following Lam’s acquisition of Novellus Systems, he helped establish new organization structures and select new leaders. He also designed and implemented employee retention programs.

Previously, Shaw spent nearly 15 years at Applied Materials. He ended his tenure there as HR VP for the international sales and marketing organization, supporting 4000 regional employees in 15 countries.

Shaw holds a B.A. degree in speech from California State University at Hayward. He earned an M.A. degree in speech communication from San Francisco State University, and a Ph.D. degree in speech communication from Pennsylvania State University.

One of the mainstays of the System-on-a-Chip (SoC) market is the continued growth of the 3rd Party Semiconductor Intellectual Property (SIP) market. The products developed and marketed by the SIP market enable SoC designers to create amazing cutting-edge silicon solutions employed in every niche of today’s semiconductor market. A new Semico Research report, Licensing, Royalty and Service Revenues for 3rd Party SIP: A Market Analysis and Forecast for 2016, forecasts the market to exceed $8 billion by 2020. However, the ‘law of large numbers’ will assert itself, and the torrent of growth over the past 10 years will start to slow.

“The number of SIP blocks in all types of SoCs continues to climb, and the number of SoCs that have SIP blocks also continues to increase each year, a sure sign of a healthy market,” said Rich Wawrzyniak, Principal Analyst for ASIC & SoC at Semico Research Corp. “It is then appropriate to focus on the individual market segments instead of only on the total market revenue to discern where the strongest growth lies,” said Wawrzyniak.

Key findings of the report include:

  • The CPU IP market will account for 31.3% of total market revenues by 2020;
  • A licensable programmable fabric is entering the market from several companies bringing new capabilities and functionality to SoC designers;
  • The Asia Pacific IP market will have a CAGR of 13.1% through 2020;
  • New embeddable memory architectures are entering the market as licensable SIP, and for the first time they are supported by major silicon foundries. MRAM, STTRAM and ReRAM are poised to debut;
  • The China IP market is forecast to reach $1.4 billion by 2020.

This report includes the SIP market broken down by geographical region (Americas, Europe, Japan, Asia Pacific, and China) and provides a forecast for each region for Licensing, Royalty and Service revenues.

Aura Semiconductor, a provider of high performance analog mixed signal solutions, today announced that it has completed Series A round of equity investment from Bay Area based WRV Capital.

Aura has innovative semiconductor technology related to the Internet of Things (IoT) Radios, Timing and Portable Audio markets. Aura’s products bring significant differentiation with emphasis on high performance, low area and reduced power consumption.

“We have developed state of the art solutions across multiple verticals that are sampling with customers worldwide,” said Srinath Sridharan, CEO of Aura. “We stand to benefit immensely from WRV’s unmatched semiconductor sector knowledge and relationships to accelerate our growth.”

“We are excited to support Aura in all their product verticals,” said Lip-Bu Tan, Founder Partner of WRV Capital. “Their accomplished management team is tackling compelling market opportunities, with differentiated products that have clear benefits to end customers. We look forward to helping them scale globally.”

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence reference flow using a quad-core design with the ARM Cortex-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.

The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy. The tools in the design flow include:

  • Innovus Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization
  • Genus Synthesis Solution: Delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation
  • Quantus QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-coloring; and a built-in 3D extraction capability, Quantus Field Solver (FS)
  • Conformal Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels
  • Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
  • Tempus Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation
  • Voltus IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff
  • Litho Physical Analyzer: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
  • Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.
  • LDE Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analog design convergence
  • Modus Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimize production test cost

“Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”

“Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its Custom Compiler tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process. This included providing and validating a Custom Compiler process design kit (PDK) in the industry-standard iPDK format. The kit is available on request from Samsung.

The newly developed Samsung 10LPP iPDK includes all technology information needed to create schematics and layout for customer designs using the Custom Compiler tool with Samsung’s 10LPP process. This comprehensive kit includes support for the groundbreaking Custom Compiler visually-assisted automation flow. Custom Compiler features enabled by the kit include full coloring for triple-patterning, fast placement of FinFET device arrays with the Symbolic Editor, in-design resistance and capacitance reporting during layout, and high-performance in-design design rule checking (DRC).

“We worked with Synopsys to include Custom Compiler support for Samsung’s foundry process offerings,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “This new 10LPP iPDK adds to our existing portfolio of iPDKs that are available for Synopsys Custom Compiler users.”

Unified with Synopsys circuit simulation, physical verification and digital implementation tools, Custom Compiler technology provides Samsung 10LPP process users with a comprehensive custom design solution that reduces FinFET layout time.

“Custom Compiler users include leading-edge customers that demand support for the latest process technologies,” said Bijan Kiani, vice president of product marketing at Synopsys. “Samsung and Synopsys worked together to enable Custom Compiler for Samsung’s 10LPP process, which can shorten layout time from days to hours.”

ams AG (SIX: AMS), a provider of high performance sensors and analog ICs, a provider of high performance sensors and analog ICs, has announced its fast and cost-efficient IC prototyping service, known as Multi-Project Wafer (MPW) or shuttle run, with an updated schedule for 2017. The prototyping service, which combines several IC designs from different customers onto a single wafer, offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among all shuttle participants.

ams’ best in class MPW service offers the whole range of 180nm and 0.35μm specialty processes including the recently introduced 180nm CMOS technology (“aC18”). The aC18 process supports a large number of 1.8V and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterised passives including various capacitors. Area-optimised high-density and low-power digital libraries with gate densities up to 152kGates/mm², updated digital and analog I/O libraries with up to 6 metal layers as well as ESD protection cells with up to 8kV HBM level complete the offering. ams’ aC18 process is ideally suited for sensor and sensor interface devices in a wide variety of applications. All 2017 MPW runs in aC18 technology will be manufactured in ams’ state of the art 200mm fabrication facility in Austria ensuring very low defect densities and high yields.

In addition to the four aC18 MPW runs, ams will also offer four MPW runs in its advanced 180nm High-Voltage CMOS (aH18) technology supporting 1.8V, 5V, 20V and 50V devices. For its 0.35μm specialty processes a total of 14 runs are offered in 2017. ams’ 0.35μm High-Voltage CMOS process family, optimised for high-voltage designs in automotive and industrial applications, supports 20V, 50V and 120V devices as well as truly voltage scalable transistors. The advanced High-Voltage CMOS process with embedded EEPROM functionality as well as the 0.35μm SiGe-BiCMOS technology S35 are fully compatible with the base CMOS process and complete ams’ MPW service portfolio.

Overall, ams will offer almost 150 MPW start dates in 2017, enabled by co-operations with worldwide partner organisations such as CMPEuropracticeFraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies.

The complete schedule for 2017 has now been released and detailed start dates per process are available on the web atwww.ams.com/MPW.

To take advantage of the MPW service, ams’ foundry customers deliver their completed GDSII-data on specific dates and receive untested packaged samples or dies within a short lead-time of typically 8 weeks for CMOS and 12 weeks for High-Voltage CMOS, SiGe-BiCMOS and Embedded Flash processes.

All process technologies are supported by the well-known hitkit, ams’ industry benchmark process design kit based on Cadence, Mentor Graphics or Keysight ADS design environments. The hitkit comes complete with fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog and RF devices, physical verification rule sets for Assura and Calibre, as well as precisely characterised circuit simulation models enable rapid design starts of complex high performance mixed-signal ICs. In addition to standard prototype services, ams also offers advanced analog IP blocks, a memory (RAM/ROM) generation service and packaging services in ceramic or plastic.

Learn more about the comprehensive service and technology portfolio of Full Service Foundry at www.ams.com/foundry.