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A new approach in Fault Detection and Classification (FDC) allows engineers to uncover issues more thoroughly and accurately by taking advantage of full sensor traces.

By Tom Ho and Stewart Chalmers, BISTel, Santa Clara, CA

Traditional FDC systems collect data from production equipment, summarize it, and compare it to control limits that were previously set up by engineers. Software alarms are triggered when any of the summarized data fall outside of the control limits. While this method has been effective and widely deployed, it does create a few challenges for the engineers:

  • The use of summary data means that (1) subtle changes in the process may not be noticed and (2) the unmonitored section of the process will be overlooked by a typical FDC system. These subtle changes or the missed anomalies in unmonitored section may result in critical problems.
  • Modeling control limits for fault detection is a manual process, prone to human error and process drift. With hundreds of thousandssensors in a complex manufacturing process, the task of modeling control limits is extremely time consuming and requires a deep understanding of the particular manufacturing process on the part of the engineer. Non-optimized control limits result in misdetection: false alarms or missed alarms.
  • As equipment ages, processes change. Meticulously set control limit ranges must be adjusted, requiring engineers to constantly monitor equipment and sensor data to avoid false alarms or missed real alarm.

Full sensor trace detection

A new approach, Dynamic Fault Detection (DFD) was developed to address the shortcomings of traditional FDC systems and save both production time and engineer time. DFD takes advantage of the full trace from each and every sensor to detect any issues during a manufacturing process. By analyzing each trace in its entirety, and running them through intelligent software, the system is able to comprehensively identify potential issues and errors as they occur. As the Adaptive Intelligence behind Dynamic Fault Detection learns each unique production environment, it will be able to identify process anomalies in real time without the need for manual adjustment from engineers. Great savings can be realized by early detection, increased engineer productivity, and containment of malfunctions.

DFD’s strength is its ability to analyze full trace data. As shown in FIGURE 1, there are many subtle details on a trace, such as spikes, shifts, and ramp rate changes, which are typically ignored or go undetected by a traditional FDC systems, because they only examine a segment of the trace- summary data. By analyzing the full trace using DFD, these details can easily be identified to provide a more thorough analysis than ever before.

Figure 1

Dynamic referencing

Unlike traditional FDC deployments, DFD does not require control limit modeling. The novel solution adapts machine learning techniques to take advantage of neighboring traces as references, so control limits are dynamically defined in real time.  Not only does this substantially reduce set up and deployment time of a fault detection system, it also eliminates the need for an engineer to continuously maintain the model. Since the analysis is done in real time, the model evolves and adapts to any process shifts as new reference traces are added.

DFD has multiple reference configurations available for engineers to choose from to fine tune detection accuracy. For example, DFD can 1) use traces within a wafer lot as reference, 2) use traces from the last N wafers as reference, 3) use “golden” traces as reference, or 4) a combination of the above.

As more sensors are added to the Internet of Things network of a production plant, DFD can integrate their data into its decision-making process.

Optimized alarming

Thousands of process alarms inundate engineers each day, only a small percentage of which are valid. In today’s FDC systems, one of the main causes for false alarms is improperly configured Statistical Process Control (SPC) limits. Also, typical FDC may generate one alarm for each limit violation resulting in many alarms for each wafer process. DFD implementations require no control limits, greatly reducing the potential for false alarms.  In addition, DFD is designed to only issues one alarm per wafer, further streamlining the alarming system and providing better focus for the engineers.

Dynamic fault detection use cases

The following examples illustrate actual use cases to show the benefits of utilizing DFD for fault detection.

Use case #1– End Point Abnormal Etching

In this example, both the upper and lower control limits in SPC were not set at the optimum levels, preventing the traditional FDC system from detecting several abnormally etched wafers (FIGURE 2).  No SPC alarms were issued to notify the engineer.

Figure 2

On the other hand, DFD full trace comparison easily detects the abnormality by comparing to neighboring traces (FIGURE 3).  This was accomplished without having to set up any control limits.

Figure 3

Use case #2 – Resist Bake Plate Temperature

The SPC chart in Figure 4 clearly shows that the Resist bake plate temperature pattern changed significantly; however, since the temperature range during the process never exceeded the control limits, SPC did not issue any alarms.

Figure 4

When the same parameter was analyzed using DFD, the temperature profile abnormality was easily identified, and the software notified an engineer (FIGURE 5).

Figure 5

Use case #3 – Full Trace Coverage

Engineers select only a segment of sensor trace data to monitor because setting up SPC limits is so arduous. In this specific case, the SPC system was set up to monitor only the He_Flow parameter in recipe step 3 and step 4.  Since no unusual events occurred during those steps in the process, no SPC alarms were triggered.

However, in that same production run, a DFD alarm was issued for one of the wafers. Upon examination of the trace summary chart shown in FIGURE 6, it is clear that while the parameter behaved normally during recipe step 3 and step 4, there was a noticeable issue from one of the wafers during recipe step 1 and step 2.  The trace in red represents the offending trace versus the rest of the (normal) population in blue. DFD full trace analysis caught the abnormality.

Figure 6

Use case #4 – DFD Alarm Accuracy

When setting up SPC limits in a conventional FDC system, the method of calculation taken by an engineer can yield vastly different results. In this example, the engineer used multiple SPC approaches to monitor parameter Match_LoadCap in an etcher. When the control limits were set using Standard Deviation (FIGURE 7), a large number of false alarms were triggered.  On the other hand, zero alarms were triggered using the Meanapproach (FIGURE 8).

Figure 7

Figure 8

Using DFD full trace detection eliminates the discrepancy between calculation methods. In the above example, DFD was able to identify an issue with one of the wafers in recipe step 3 and trigger only one alarm.

Dynamic fault detection scope of use

DFD is designed to be used in production environments of many types, ranging from semiconductor manufacturing to automotive plants and everything in between. As long as the manufacturing equipment being monitored generates systematic and consistent trace patterns, such as gas flow, temperature, pressure, power etc., proper referencing can be established by the Adaptive Intelligence (AI) to identify abnormalities. Sensor traces from Process of Record (POR) runs may be used as starting references.

Conclusion

The DFD solution reduces risk in manufacturing by protecting against events that impact yield.  It also provides engineers with an innovative new tool that addresses several limitations of today’s traditional FDC systems.  As shown in TABLE 1, the solution greatly reduces the time required for deployment and maintenance, while providing a more thorough and accurate detection of issues.

 

TABLE 1
FDC

(Per Recipe/Tool Type)

 DFD

(Per Recipe/Tool Type)
FDC model creation 1 – 2 weeks < 1 day
FDC model validation and fine tuning 2 – 3 weeks < 1 week
Model Maintenance Ongoing Minimal
Typical Alarm Rate 100-500/chamber-day < 50/chamber-day
% Coverage of Number of Sensors 50-60% 100% as default
Trace Segment Coverage 20-40% 100%
Adaptive to Systematic Behavior Changes No Yes

 

 

TOM HO is President of BISTel America where he leads global product engineer and development efforts for BISTel.  [email protected].   STEWART CHALMERS is President & CEO of Hill + Kincaid, a technical marketing firm. [email protected]. 

When chemists from the Institute of Physical Chemistry of the Polish Academy of Sciences in Warsaw were starting work on yet another material designed for the efficient production of nanocrystalline zinc oxide, they didn’t expect any surprises. They were greatly astonished when the electrical properties of the changing material turned out to be extremely exotic.

The exotic transformations causes that one of the precursors of zinc oxide, initially an insulator, at approx. 300 degrees Celsius goes to a state with electrical properties typical of metals, and at ~400 degrees Celsius it becomes a semiconductor. Credit: IPC PAS

The single source precursor (SSP) approach is widely regarded as one of the most promising of the various strategies employed for the preparation of semiconductor nanocrystalline materials. However, one of the key obstacles hampering both the rational design of SSPs and their controlled transformation to the desired nanomaterials with highly controlled physicochemical properties is the scarcity of mechanistic insights during the transformation process. Scientists from the Institute of Physical Chemistry of the Polish Academy of Sciences (IPC PAS) and the Faculty of Chemistry of Warsaw University of Technology (WUT) have revealed that in the thermal decomposition process of a pre-organized zinc alkoxide precursor the nucleation and growth of the semiconducting zinc oxide (ZnO) phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states. Up to now, these types of clusters have not been considered either as intermediate structures on the path to the semiconductor ZnO phase or as a potential species accounting for the various defect states of ZnO nanocrystals.

“We discovered that one of the groups of ZnO precursors that have been studied for decades, zinc alkoxide compounds, undergo previously unobserved physicochemical transformations upon thermal decomposition. Originally, the starting compound is an insulator, when heated it rapidly transforms into a material with conductor-like properties, and a further increase in temperature equally rapidly leads to its conversion into a semiconductor,” says Dr. Kamil Soko?owski (IPC PAS).

The design and preparation of well-defined nanomaterials in a controlled manner remains a tremendous challenge and is acknowledged to be the biggest obstacle for the exploitation of many nanoscale phenomena. Professor Lewiski’s (IPC PAS, PW) group has for many years been engaged in the development of effective methods of producing nanocrystalline forms of zinc oxide, a semiconductor with wide applications in electronics, industrial catalysis, photovoltaics and photocatalysis. One of the studied approaches is based on the single source precursors. The precursor molecules contain all components of the target material in their structure and only temperature is required to trigger the chemical transformation.

“We dealt with a group of chemical compounds with the general formula RZnOR, as single source pre-designed ZnO precursors. A common feature of their structure is the presence of the cubic [Zn4O4] core with alternating zinc and oxygen atoms terminated by organic groups R. When the precursor is heated, the organic parts are degraded, and the inorganic cores self-assemble, forming the final form of the nanomaterial,” explains Dr. Soko?owski.

The tested precursor had the properties of an insulator, with an energy gap of about five electronvolts. When heated, it eventually transformed into a semiconductor with an energy gap of approximately 3 eV.

“An exceptional result of our research was the discovery that at a temperature close to 300 degrees Celsius the compound suddenly transforms into almost gap-less electronic state, showing electrical properties rather more typical of metals. When the temperature rises to approximately 400 degrees, the energy gap suddenly expands to a width characteristic of semiconductor materials. Ultimately, thanks to the combination of advanced synchrotron experiments with quantum-chemical calculations, we have established all the details of these unique transformations,” says Dr. Adam Kubas (IPC PAS), who carried out the quantum-chemical calculations.

The spectroscopic measurements were carried out using methods developed by Dr. Jakub Szlachetko (Institute of Nuclear Physics PAS, Cracow) and Dr. Jacinto Sa (IPC PAS and Uppsala University) at the Swiss Light Source synchrotron facility at the Paul Scherrer Institute in Villigen, Switzerland. The material was heated in a reaction chamber, and then its electron structure was sampled using an X-ray synchrotron beam. The set-up allowed for real-time monitoring of the transformations taking place.

This detailed in situ study of the decomposition process of the zinc alkoxide precursor, supported by computer simulations, revealed that any nucleation or growth of a semiconducting ZnO phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states.

“In this process homolytic cleavage of the R-Zn bond is responsible for the initial thermal decomposition process. Computer simulations revealed that the intermediate radical clusters tend to dimerise though an uncommon bimetallic Zn-Zn-bond formation. The following homolytic O-R bond cleavage then leads to sub-nano ZnO clusters which further self-organise to the ZnO nanocrystalline phase,” says Dr. Kubas.

Up to now, the radical zinc oxo clusters formed have not been considered either as intermediate structures on the way to the semiconductor ZnO phase or as potential species accounting for various defect states of ZnO nanocrystals. In a broader context, a deeper understanding of the origin and character of the defects is crucial for structure-property relationships in semiconducting materials.

The research, funded by the National Science Centre and the TEAM grant of the Foundation for Polish Science co-financed by the European Union, will contribute to the development of more precise methods of controlling the properties of nanocrystalline zinc oxide. So far, with greater or lesser success, these properties have been explained with the help of various types of material defects. For obvious reasons, however, the analyses have not taken into account the possibility of forming the specific radical zinc-oxo clusters discovered by the Warsaw-based scientists in the material.

Since the 2003 discovery of the single-atom-thick carbon material known as graphene, there has been significant interest in other types of 2-D materials as well.

These materials could be stacked together like Lego bricks to form a range of devices with different functions, including operating as semiconductors. In this way, they could be used to create ultra-thin, flexible, transparent and wearable electronic devices.

However, separating a bulk crystal material into 2-D flakes for use in electronics has proven difficult to do on a commercial scale.

The existing process, in which individual flakes are split off from the bulk crystals by repeatedly stamping the crystals onto an adhesive tape, is unreliable and time-consuming, requiring many hours to harvest enough material and form a device.

Now researchers in the Department of Mechanical Engineering at MIT have developed a technique to harvest 2-inch diameter wafers of 2-D material within just a few minutes. They can then be stacked together to form an electronic device within an hour.

The technique, which they describe in a paper published in the journal Science, could open up the possibility of commercializing electronic devices based on a variety of 2-D materials, according to Jeehwan Kim, an associate professor in the Department of Mechanical Engineering, who led the research.

The paper’s co-first authors were Sanghoon Bae, who was involved in flexible device fabrication, and Jaewoo Shim, who worked on the stacking of the 2-D material monolayers. Both are postdocs in Kim’s group.

The paper’s co-authors also included students and postdocs from within Kim’s group, as well as collaborators at Georgia Tech, the University of Texas, Yonsei University in South Korea, and the University of Virginia. Sang-Hoon Bae, Jaewoo Shim, Wei Kong, and Doyoon Lee in Kim’s research group equally contributed to this work.

“We have shown that we can do monolayer-by-monolayer isolation of 2-D materials at the wafer scale,” Kim says. “Secondly, we have demonstrated a way to easily stack up these wafer-scale monolayers of 2-D material.”

The researchers first grew a thick stack of 2-D material on top of a sapphire wafer. They then applied a 600-nanometer-thick nickel film to the top of the stack.

Since 2-D materials adhere much more strongly to nickel than to sapphire, lifting off this film allowed the researchers to separate the entire stack from the wafer.

What’s more, the adhesion between the nickel and the individual layers of 2-D material is also greater than that between each of the layers themselves.

As a result, when a second nickel film was then added to the bottom of the stack, the researchers were able to peel off individual, single-atom thick monolayers of 2-D material.

That is because peeling off the first nickel film generates cracks in the material that propagate right through to the bottom of the stack, Kim says.

Once the first monolayer collected by the nickel film has been transferred to a substrate, the process can be repeated for each layer.

“We use very simple mechanics, and by using this controlled crack propagation concept we are able to isolate monolayer 2-D material at the wafer scale,” he says.

The universal technique can be used with a range of different 2-D materials, including hexagonal boron nitride, tungsten disulfide, and molybdenum disulfide.

In this way it can be used to produce different types of monolayer 2-D materials, such as semiconductors, metals, and insulators, which can then be stacked together to form the 2-D heterostructures needed for an electronic device.

“If you fabricate electronic and photonic devices using 2-D materials, the devices will be just a few monolayers thick,” Kim says. “They will be extremely flexible, and can be stamped on to anything,” he says.

The process is fast and low-cost, making it suitable for commercial operations, he adds.

The researchers have also demonstrated the technique by successfully fabricating arrays of field-effect transistors at the wafer scale, with a thickness of just a few atoms.

“The work has a lot of potential to bring 2-D materials and their heterostructures towards real-world applications,” says Philip Kim, a professor of physics at Harvard University, who was not involved in the research.

The researchers are now planning to apply the technique to develop a range of electronic devices, including a nonvolatile memory array and flexible devices that can be worn on the skin.

They are also interested in applying the technique to develop devices for use in the “internet of things,” Kim says.

“All you need to do is grow these thick 2-D materials, then isolate them in monolayers and stack them up. So it is extremely cheap — much cheaper than the existing semiconductor process. This means it will bring laboratory-level 2-D materials into manufacturing for commercialization,” Kim says.

“That makes it perfect for IoT networks, because if you were to use conventional semiconductors for the sensing systems it would be expensive.”

A paper published in Nature Communications by Sufei Shi, assistant professor of chemical and biological engineering at Rensselaer, increases our understanding of how light interacts with atomically thin semiconductors and creates unique excitonic complex particles, multiple electrons, and holes strongly bound together. These particles possess a new quantum degree of freedom, called “valley spin.” The “valley spin” is similar to the spin of electrons, which has been extensively used in information storage such as hard drives and is also a promising candidate for quantum computing.

Research on Light-Matter Interaction Could Lead to Improved Electronic and Optoelectronic Devices. Credit: Rensselaer Polytechnic Institute

The paper, titled “Revealing the biexciton and trion-exciton complexes in BN encapsulated WSe2,” was published in the Sept. 13, 2018, edition of Nature Communications. Results of this research could lead to novel applications in electronic and optoelectronic devices, such as solar energy harvesting, new types of lasers, and quantum sensing.

Shi’s research focuses on low dimensional quantum materials and their quantum effects, with a particular interest in materials with strong light-matter interactions. These materials include graphene, transitional metal dichacogenides (TMDs), such as tungsten diselenide (WSe2), and topological insulators.

TMDs represent a new class of atomically thin semiconductors with superior optical and optoelectronic properties. Optical excitation on the two-dimensional single-layer TMDs will generate a strongly bound electron-hole pair called an exciton, instead of freely moving electrons and holes as in traditional bulk semiconductors. This is due to the giant binding energy in monolayer TMDs, which is orders of magnitude larger than that of conventional semiconductors. As a result, the exciton can survive at room temperature and can thus be used for application of excitonic devices.

As the density of the exciton increases, more electrons and holes pair together, forming four-particle and even five-particle excitonic complexes. An understanding of the many-particle excitonic complexes not only gives rise to a fundamental understanding of the light-matter interaction in two dimensions, it also leads to novel applications, since the many-particle excitonic complexes maintain the “valley spin” properties better than the exciton. However, despite recent developments in the understanding of excitons and trions in TMDs, said Shi, an unambiguous measure of the biexciton-binding energy has remained elusive.

“Now, for the first time, we have revealed the true biexciton state, a unique four-particle complex responding to light,” said Shi. “We also revealed the nature of the charged biexciton, a five-particle complex.”

At Rensselaer, Shi’s team has developed a way to build an extremely clean sample to reveal this unique light-matter interaction. The device was built by stacking multiple atomically thin materials together, including graphene, boron nitride (BN), and WSe2, through van der Waals (vdW) interaction, representing the state-of-the-art fabrication technique of two-dimensional materials.

This work was performed in collaboration with the National High Magnetic Field Laboratory in Tallahasee, Florida, and researchers at the National Institute for Materials Science in Japan, as well as with Shengbai Zhang, the Kodosky Constellation Professor in the Department of Physics, Applied Physics, and Astronomy at Rensselaer, whose work played a critical role in developing a theoretical understanding of the biexciton.

The results of this research could potentially lead to robust many-particle optical physics, and illustrate possible novel applications based on 2D semiconductors, Shi said. Shi has received funding from the Air Force Office of Scientific Research. Zhang was supported by the Department of Energy, Office of Science.

The vast majority of computing devices today are made from silicon, the second most abundant element on Earth, after oxygen. Silicon can be found in various forms in rocks, clay, sand, and soil. And while it is not the best semiconducting material that exists on the planet, it is by far the most readily available. As such, silicon is the dominant material used in most electronic devices, including sensors, solar cells, and the integrated circuits within our computers and smartphones.

Now MIT engineers have developed a technique to fabricate ultrathin semiconducting films made from a host of exotic materials other than silicon. To demonstrate their technique, the researchers fabricated flexible films made from gallium arsenide, gallium nitride, and lithium fluoride — materials that exhibit better performance than silicon but until now have been prohibitively expensive to produce in functional devices.

MIT researchers have devised a way to grow single crystal GaN thin film on a GaN substrate through two-dimensional materials. The GaN thin film is then exfoliated by a flexible substrate, showing the rainbow color that comes from thin film interference. This technology will pave the way to flexible electronics and the reuse of the wafers. Credit: Wei Kong and Kuan Qiao

The new technique, researchers say, provides a cost-effective method to fabricate flexible electronics made from any combination of semiconducting elements, that could perform better than current silicon-based devices.

“We’ve opened up a way to make flexible electronics with so many different material systems, other than silicon,” says Jeehwan Kim, the Class of 1947 Career Development Associate Professor in the departments of Mechanical Engineering and Materials Science and Engineering. Kim envisions the technique can be used to manufacture low-cost, high-performance devices such as flexible solar cells, and wearable computers and sensors.

Details of the new technique are reported today in Nature Materials. In addition to Kim, the paper’s MIT co-authors include Wei Kong, Huashan Li, Kuan Qiao, Yunjo Kim, Kyusang Lee, Doyoon Lee, Tom Osadchy, Richard Molnar, Yang Yu, Sang-hoon Bae, Yang Shao-Horn, and Jeffrey Grossman, along with researchers from Sun Yat-Sen University, the University of Virginia, the University of Texas at Dallas, the U.S. Naval Research Laboratory, Ohio State University, and Georgia Tech.

Now you see it, now you don’t

In 2017, Kim and his colleagues devised a method to produce “copies” of expensive semiconducting materials using graphene — an atomically thin sheet of carbon atoms arranged in a hexagonal, chicken-wire pattern. They found that when they stacked graphene on top of a pure, expensive wafer of semiconducting material such as gallium arsenide, then flowed atoms of gallium and arsenide over the stack, the atoms appeared to interact in some way with the underlying atomic layer, as if the intermediate graphene were invisible or transparent. As a result, the atoms assembled into the precise, single-crystalline pattern of the underlying semiconducting wafer, forming an exact copy that could then easily be peeled away from the graphene layer.

The technique, which they call “remote epitaxy,” provided an affordable way to fabricate multiple films of gallium arsenide, using just one expensive underlying wafer.

Soon after they reported their first results, the team wondered whether their technique could be used to copy other semiconducting materials. They tried applying remote epitaxy to silicon, and also germanium — two inexpensive semiconductors — but found that when they flowed these atoms over graphene they failed to interact with their respective underlying layers. It was as if graphene, previously transparent, became suddenly opaque, preventing atoms of silicon and germanium from “seeing” the atoms on the other side.

As it happens, silicon and germanium are two elements that exist within the same group of the periodic table of elements. Specifically, the two elements belong in group four, a class of materials that are ionically neutral, meaning they have no polarity.

“This gave us a hint,” says Kim.

Perhaps, the team reasoned, atoms can only interact with each other through graphene if they have some ionic charge. For instance, in the case of gallium arsenide, gallium has a negative charge at the interface, compared with arsenic’s positive charge. This charge difference, or polarity, may have helped the atoms to interact through graphene as if it were transparent, and to copy the underlying atomic pattern.

“We found that the interaction through graphene is determined by the polarity of the atoms. For the strongest ionically bonded materials, they interact even through three layers of graphene,” Kim says. “It’s similar to the way two magnets can attract, even through a thin sheet of paper.”

Opposites attract

The researchers tested their hypothesis by using remote epitaxy to copy semiconducting materials with various degrees of polarity, from neutral silicon and germanium, to slightly polarized gallium arsenide, and finally, highly polarized lithium fluoride — a better, more expensive semiconductor than silicon.

They found that the greater the degree of polarity, the stronger the atomic interaction, even, in some cases, through multiple sheets of graphene. Each film they were able to produce was flexible and merely tens to hundreds of nanometers thick.

The material through which the atoms interact also matters, the team found. In addition to graphene, they experimented with an intermediate layer of hexagonal boron nitride (hBN), a material that resembles graphene’s atomic pattern and has a similar Teflon-like quality, enabling overlying materials to easily peel off once they are copied.

However, hBN is made of oppositely charged boron and nitrogen atoms, which generate a polarity within the material itself. In their experiments, the researchers found that any atoms flowing over hBN, even if they were highly polarized themselves, were unable to interact with their underlying wafers completely, suggesting that the polarity of both the atoms of interest and the intermediate material determines whether the atoms will interact and form a copy of the original semiconducting wafer.

“Now we really understand there are rules of atomic interaction through graphene,” Kim says.

With this new understanding, he says, researchers can now simply look at the periodic table and pick two elements of opposite charge. Once they acquire or fabricate a main wafer made from the same elements, they can then apply the team’s remote epitaxy techniques to fabricate multiple, exact copies of the original wafer.

“People have mostly used silicon wafers because they’re cheap,” Kim says. “Now our method opens up a way to use higher-performing, nonsilicon materials. You can just purchase one expensive wafer and copy it over and over again, and keep reusing the wafer. And now the material library for this technique is totally expanded.”

Kim envisions that remote epitaxy can now be used to fabricate ultrathin, flexible films from a wide variety of previously exotic, semiconducting materials — as long as the materials are made from atoms with a degree of polarity. Such ultrathin films could potentially be stacked, one on top of the other, to produce tiny, flexible, multifunctional devices, such as wearable sensors, flexible solar cells, and even, in the distant future, “cellphones that attach to your skin.”

“In smart cities, where we might want to put small computers everywhere, we would need low power, highly sensitive computing and sensing devices, made from better materials,” Kim says. “This [study] unlocks the pathway to those devices.”

Mentor, a Siemens business, today announced it has qualified complete solutions from its Calibre® nmPlatform™, Analog FastSPICE™ (AFS)™ Platform, Eldo® Platform and Nitro-SoC place and route system for GLOBALFOUNDRIES’ 22FDX Fully-Depleted Silicon-On-Insulator (FD-SOI) integrated circuit (IC) manufacturing processes. GF and Mentor have mutually developed an advanced, first-of-its-kind automated fill flow that ensures analog devices are able to leverage the full performance of these new processes in emerging markets such as ADAS/autonomous driving, IoT, 5G communications, cloud computing and artificial intelligence.

“Mentor is pleased to be taking another step in our longstanding relationship with GF to deliver to our mutual customers solutions that help develop industry innovations,” said Ravi Subramanian, vice president and general manager, IC Verification Solutions, Mentor, a Siemens business. “The combined expertise of GF and Mentor gives designers the ability to develop innovative ICs for a broad number of applications.”

“Mentor has an extremely long history of partnership with GF, as Calibre’s first customer ever,” said Richard Trihy, senior director, Design Enablement at GF. “That partnership continues today with not only additional design kit certifications, but flows that help accelerate design fill efforts at a time when market windows are increasingly shorter.”

Mentor Calibre nmPlatform for GF’s 22FDX

Mentor has made enhancements across its Calibre nmPlatform for GF’s 22FDX process. One of the most significant of these is an industry-first, automated fill flow targeting both analog and radio frequency (RF) IP blocks and full chips. The new fill flow automates a task that previously required fabless design teams to manually develop custom scripts to perform fill effectively. The new flow combines Calibre PERC™, Calibre Pattern Matching and Calibre YieldEnhancer tool capabilities to create both net-aware and orientation-aware filling that results in consistent analog and RF performance independent of where the blocks are placed in the chip.

In addition, Mentor enhanced the Calibre nmDRC™ and Calibre nmLVS™ tools for GF’s 22FDX process. Mentor worked with GF to ensure appropriate coverage, and the two companies are collaborating to continuously optimize the Calibre design kits for runtime performance. At the same time, GF and Mentor worked together to make advanced process requirements transparent to mutual customers within the Calibre design rule checking (DRC) and multi-patterning software.

The Calibre xACTTM parasitic extraction tool is available for GF’s 22FDX process, allowing customers to efficiently balance the needs of high accuracy of critical structures along with high performance required for full chip signoff.

The Calibre PERC reliability platform is a verification solution for both IP and full-chip reliability analysis. Point-to-point and ESD current density reliability checks are critical for today’s complex, dense chip designs, but completing these checks on very large 22FDX designs requires scalability. GF and Mentor collaborated to enable a Calibre PERC solution leveraging a new multi-CPU run capability that allows mutual customers to more quickly find and resolve ESD reliability concerns in their designs.

The Calibre YieldEnhancer tool is certified for GF’s 22FDX processes. Mentor and GF are also jointly delivering enhanced use models that optimize fill runtimes, minimize shape removal caused by an engineering change order (ECO), and ensure consistency across all layers, intellectual property (IP) blocks and full-chip system-on-chips (SoCs) using fill-as-you-go methodologies.

Mentor AFS Platform and Eldo Platform for GF’s 22FDX

Mentor’s AFS Platform and Eldo Platform are supported in the GF 22FDX process. Mutual customers benefit from the AFS Platform (delivering fast, SPICE-accurate verification for the largest nanometer-scale circuits), and Eldo Platform (circuit verification for analog-centric circuits) to verify their chips designed for GF technologies.

Mentor Nitro SoC for GF 22FDX

Mentor’s Nitro SoC place and route system is certified for GF’s 22FDX process. In addition to support for 22FDX process rules, Mentor enhanced the Nitro SoC core engines to meet the new architecture requirements and design rules for this process. This enables Mentor to deliver an optimized digital implementation flow for the 22FDX node.

Synopsys, Inc. (Nasdaq: SNPS) today announced the Synopsys Design Platform fully supports TSMC’s wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS®) advanced packaging technologies. The design platform enablement, combined with the 3D-IC reference flow, enables customer deployments for high-performance, high-connectivity multi-die technology in mobile computing, network communication, consumer, and automotive electronics applications.

The platform-wide Synopsys solution includes multi-die and interposer layout capture, physical floorplanning, and implementation, as well as parasitic extraction and timing analysis coupled with physical verification. Key products and features of the Synopsys Design Platform supporting TSMC’s advanced WoW and CoWoS packaging technologies include:

  • IC Compiler™ II place-and-route: Supports multi-die floorplanning and implementation, including interposer and 3D stack-die generation, TSV placement and connectivity assignment, orthogonal multi-layer, 45-degree single-layer, and interface inter-die block generation for inter-die extraction and checking
  • StarRC™ extraction: Supports modeling of TSV and backside RDL metal extraction, silicon interposer extraction, and inter-die coupling capacitance extraction
  • IC Validator: Supports full-system DRC and LVS verification, inter-die DRC, and LVS checking of inter-die interface
  • PrimeTime® signoff analysis: Full-system static timing analysis, supports multi-die static timing analysis (STA)

“High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and flows to support the corresponding increase in design and verification complexity,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We extend our collaboration with Synopsys to deliver design solutions for TSMC’s CoWoS and WoW advanced packaging technologies. We look forward to our mutual customers benefiting from the enabled design solutions, boosting designer productivity and accelerating time-to-market.”

“Built through deep collaboration, the design solution and reference flow for TSMC’s WoW and CoWoS chip integration solutions will enable our mutual customers to achieve optimal quality of results,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “The Synopsys Design Platform and methodologies will allow designers to confidently meet their schedules for cost-effective, high-performance, and low-power multi-die solutions.”

Synopsys jointly highlighted the advances and collaborations of TSMC 2.5D and 3D technologies in a paper titled “Onwards and Upwards: How Xilinx is Leveraging TSMC’s Latest Integration and Packaging Technologies with Synopsys’ Platform-wide Solution for Next-generation Designs” at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on October 3, 2018 in Santa Clara, California.

Engineers at The Australian National University (ANU) have invented a semiconductor with organic and inorganic materials that can convert electricity into light very efficiently, and it is thin and flexible enough to help make devices such as mobile phones bendable.

The invention also opens the door to a new generation of high-performance electronic devices made with organic materials that will be biodegradable or that can be easily recycled, promising to help substantially reduce e-waste.

The huge volumes of e-waste generated by discarded electronic devices around the world is causing irreversible damage to the environment. Australia produces 200,000 tonnes of e-waste every year – only four per cent of this waste is recycled.

The organic component has the thickness of just one atom – made from just carbon and hydrogen – and forms part of the semiconductor that the ANU team developed. The inorganic component has the thickness of around two atoms. The hybrid structure can convert electricity into light efficiently for displays on mobile phones, televisions and other electronic devices.

Lead senior researcher Associate Professor Larry Lu said the invention was a major breakthrough in the field.

“For the first time, we have developed an ultra-thin electronics component with excellent semiconducting properties that is an organic-inorganic hybrid structure and thin and flexible enough for future technologies, such as bendable mobile phones and display screens,” said Associate Professor Lu from the ANU Research School of Engineering.

PhD researcher Ankur Sharma, who recently won the ANU 3-Minute Thesis competition, said experiments demonstrated the performance of their semiconductor would be much more efficient than conventional semiconductors made with inorganic materials such as silicon.

“We have the potential with this semiconductor to make mobile phones as powerful as today’s supercomputers,” said Mr Sharma from the ANU Research School of Engineering.

“The light emission from our semiconducting structure is very sharp, so it can be used for high-resolution displays and, since the materials are ultra-thin, they have the flexibility to be made into bendable screens and mobile phones in the near future.”

The team grew the organic semiconductor component molecule by molecule, in a similar way to 3D printing. The process is called chemical vapour deposition.

“We characterised the opto-electronic and electrical properties of our invention to confirm the tremendous potential of it to be used as a future semiconductor component,” Associate Professor Lu said.

“We are working on growing our semiconductor component on a large scale, so it can be commercialised in collaboration with prospective industry partners.”

The American Institute for Manufacturing Integrated Photonics (AIM Photonics) and Analog Photonics (AP) today announced the release of the AP SUNY Process Design Kit v2.5a (APSUNY_PDKv2.5a). In this latest release, Analog Photonics (AP) expanded the comprehensive set of Silicon Photonics Integrated Circuit (PIC) component libraries within SUNY Poly’s process capabilities to address the needs for O+C+L band applications. Combined with Multi-Project Wafer (MPW) runs, this updated PDK will give AIM Photonics’ members access to world-class silicon photonics components for the development of optical transceivers or systems used in all levels within data centers and high-performance computers.

The Silicon Photonics PDK includes design guide, design rule check deck, technology files, active and passive component documentation, abstracts, schematics, and compact models for the development of PICs.

The key features of the APSUNY_PDKv2.5a are:

  • O Band modulation, detection and coupling support.
  • C+L Band modulation, detection, filtering, switching, monitoring and coupling support.
  • Single-level and Multi-level modulation format support at 50Gbps, namely NRZ and PAM-4.
  •    Continued multi-vendor Electronics-Photonics-Design-Automation (EPDA) support with integrated EPDA PDK flow for hierarchical design and system-level simulation.

“We are thrilled to continue to expand the offerings of our state-of-the-art PDK to meet the needs of our more than 100 signed partners and other interested collaborators who can gain access to our unique capabilities. This also dovetails perfectly with our effort to efficiently process our Multi-Project Wafers (MPW’s) in the fab, with processing time decreasing from 130 days in 2016 to fewer than 90 days as we simultaneously add additional mask levels and functionality and continue to achieve world-class quality,” said Dr. Michael Liehr, AIM Photonics CEO and SUNY Poly Executive Vice President for Innovation and Technology.

The combined APSUNY_PDKv2.5a and MPW offering provides unmatched access to PIC systems for companies who desire a reduction in the time to market, product development risk, and investment.  By incorporating the design, verification, and process development within the PDK, interested organizations can rapidly modify their designs while reducing cost.

“The IEEE standards and multi-source-agreements (MSAs) for communications compatibility are key for our PDK component library. These standards require optical components to operate at O band (1260nm-to-1360nm), C band (1530nm-to-1565nm) and L band (1565nm-to-1625nm). With the PDKv2.5a component library, we are enabling components that cover all these bands in a single fabrication flow, and we look forward to the advancement of this library while innovating to meet industry needs,” said Director of PDK Development at Analog Photonics, Dr. Erman Timurdogan.

In the near future, the PDK will be empowered by laser and CMOS integration with an interposer, a capability that will be made possible at AIM Photonics’ Test, Assembly, and Packaging (TAP) facility, located in Rochester, NY. Additional releases of the AP SUNY Process Design Kit are planned over the next several years each quarter, with improved statistical models, optical components, and PIC systems.

“We are seeing customers take advantage of our repeatedly characterized and proven devices in the APSUNY PDK. With this valuable resource, which is validated on our 300mm advanced  semiconductor toolset, customers are able to rapidly address global standards, shrink their design sizes, and most importantly, reduce their time to market,” said AIM Photonics Design Center Offering Director Barton Bergman.

AIM Photonics is leveraging SUNY Poly’s state-of-the-art facilities for three total full-build/passive MPW runs that incorporate the PDK updates, with an interposer MPW run anticipated later in 2018. To ensure space for all interested parties, AIM Photonics is accepting reservations for these MPW runs. Those interested in participating in any of the AIM Photonics 2018 MPW silicon photonics runs should contact Chandra Cotter at [email protected] in order to guarantee a spot on these exciting new silicon photonics offerings. Interested parties can also sign up for the 2018 runs by visiting the initiative’s website at the following link: http://www.aimphotonics.com/mpw-schedule/

PDK and MPW fab access is solely available through the AIM Photonics MPW aggregator, MOSIS. Please contact MOSIS for access to the most current PDK version release at the following link: www.mosis.com/vendors/view/AIM.

A team of semiconductor researchers based in France has used a boron nitride separation layer to grow indium gallium nitride (InGaN) solar cells that were then lifted off their original sapphire substrate and placed onto a glass substrate.

Ph.D. Student Taha Ayari measures the photovoltaic performance of the InGaN solar cells with a solar simulator. (Credit: Ougazzaden laboratory)

By combining the InGaN cells with photovoltaic (PV) cells made from materials such as silicon or gallium arsenide, the new lift-off technique could facilitate fabrication of higher efficiency hybrid PV devices able to capture a broader spectrum of light. Such hybrid structures could theoretically boost solar cell efficiency as high as 30 percent for an InGaN/Si tandem device.

The technique is the third major application for the hexagonal boron nitride lift-off technique, which was developed by a team of researchers from the Georgia Institute of Technology, the French National Center for Scientific Research (CNRS), and Institut Lafayette in Metz, France. Earlier applications targeted sensors and light-emitting diodes (LEDs).

“By putting these structures together with photovoltaic cells made of silicon or a III-V material, we can cover the visible spectrum with the silicon and utilize the blue and UV light with indium gallium nitride to gather light more efficiently,” said Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and a professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE). “The boron nitride layer doesn’t impact the quality of the indium gallium nitride grown on it, and we were able to lift off the InGaN solar cells without cracking them.”

The research was published August 15 in the journal ACS Photonics. It was supported by the French National Research Agency under the GANEX Laboratory of Excellence project and the French PIA project “Lorraine Université d’Excellence.”

The technique could lead to production of solar cells with improved efficiency and lower cost for a broad range of terrestrial and space applications. “This demonstration of transferred InGaN-based solar cells on foreign substrates while increasing performance represents a major advance toward lightweight, low cost, and high efficiency photovoltaic applications,” the researchers wrote in their paper.

“Using this technique, we can process InGaN solar cells and put a dielectric layer on the bottom that will collect only the short wavelengths,” Ougazzaden explained. “The longer wavelengths can pass through it into the bottom cell. By using this approach we can optimize each surface separately.”

The researchers began the process by growing monolayers of boron nitride on two-inch sapphire wafers using an MOVPE process at approximately 1,300 degrees Celsius. The boron nitride surface coating is only a few nanometers thick, and produces crystalline structures that have strong planar surface connections, but weak vertical connections.

The InGaN attaches to the boron nitride with weak van der Waals forces, allowing the solar cells to be grown across the wafer and removed without damage. So far, the cells have been removed from the sapphire manually, but Ougazzaden believes the transfer process could be automated to drive down the cost of the hybrid cells. “We can certainly do this on a large scale,” he said.

The InGaN structures are then placed onto the glass substrate with a backside reflector and enhanced performance is obtained. Beyond demonstrating placement atop an existing PV structure, the researchers hope to increase the amount of indium in their lift-off devices to boost light absorption and increase the number of quantum wells from five to 40 or 50.

“We have now demonstrated all the building blocks, but now we need to grow a real structure with more quantum wells,” Ougazzaden said. “We are just at the beginning of this new technology application, but it is very exciting.”

In addition to Ougazzaden, the research team includes Georgia Tech Ph.D. students Taha Ayari, Matthew Jordan, Xin Li and Saiful Alam; Chris Bishop and Simon Gautier from Institut Lafayette; Suresh Sundaram, a researcher at Georgia Tech Lorraine; Walid El Huni and Yacine Halfaya from CNRS; Paul Voss, an associate professor in the Georgia Tech School of ECE; and Jean Paul Salvestrini, a professor at Georgia Tech Lorraine and adjunct professor in the Georgia Tech School of ECE.

CITATION: Taha Ayari, et al., “Heterogeneous Integration of Thin-Film InGaN-Based Solar Cells on Foreign Substrates with Enhanced Performance,” (ACS Photonics 2018) https://pubs.acs.org/doi/abs/10.1021/acsphotonics.8b00663