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Myeloperoxidase – an enzyme naturally found in our lungs – can biodegrade pristine graphene, according to the latest discovery of Graphene Flagship partners in CNRS, University of Strasbourg (France), Karolinska Institute (Sweden) and University of Castilla-La Mancha (Spain). Among other projects, the Graphene Flagship designs flexible biomedical electronic devices that will interface with the human body. Such applications require graphene to be biodegradable, so it can be expelled from the body.

To test how graphene behaves within the body, researchers analysed how it was broken down with the addition of a common human enzyme – myeloperoxidase or MPO. If a foreign body or bacteria is detected, neutrophils surround it and secrete MPO, thereby destroying the threat. Previous work by Graphene Flagship partners found that MPO could successfully biodegrade graphene oxide.

However, the structure of non-functionalized graphene was thought to be more resistant to degradation. To test this, the team looked at the effects of MPO ex vivo on two graphene forms; single- and few-layer.

Alberto Bianco, researcher at Graphene Flagship Partner CNRS, explains: “We used two forms of graphene, single- and few-layer, prepared by two different methods in water. They were then taken and put in contact with myeloperoxidase in the presence of hydrogen peroxide. This peroxidase was able to degrade and oxidise them. This was really unexpected, because we thought that non-functionalized graphene was more resistant than graphene oxide.”

Rajendra Kurapati, first author on the study and researcher at Graphene Flagship Partner CNRS, remarks how “the results emphasize that highly dispersible graphene could be degraded in the body by the action of neutrophils. This would open the new avenue for developing graphene-based materials.”

With successful ex-vivo testing, in-vivo testing is the next stage. Bengt Fadeel, professor at Graphene Flagship Partner Karolinska Institute believes that “understanding whether graphene is biodegradable or not is important for biomedical and other applications of this material. The fact that cells of the immune system are capable of handling graphene is very promising.”

Prof. Maurizio Prato, the Graphene Flagship leader for its Health and Environment Work Package said that “the enzymatic degradation of graphene is a very important topic, because in principle, graphene dispersed in the atmosphere could produce some harm. Instead, if there are microorganisms able to degrade graphene and related materials, the persistence of these materials in our environment will be strongly decreased. These types of studies are needed.” “What is also needed is to investigate the nature of degradation products,” adds Prato. “Once graphene is digested by enzymes, it could produce harmful derivatives. We need to know the structure of these derivatives and study their impact on health and environment,” he concludes.

Prof. Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship, and chair of its management panel added: “The report of a successful avenue for graphene biodegradation is a very important step forward to ensure the safe use of this material in applications. The Graphene Flagship has put the investigation of the health and environment effects of graphene at the centre of its programme since the start. These results strengthen our innovation and technology roadmap.”

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced its new narrowband (NB) Internet-of-Things (IoT) solution, Exynos i S111.

The new NB-IoT solution offers extremely wide coverage, low-power operation, accurate location feedback and strong security, optimized for today’s real-time tracking applications such as safety wearables or smart meters. The solution includes a modem, processor, memory and Global Navigation Satellite System (GNSS) into a single chip design to enhance efficiency and flexibility for connected device manufacturers.

“IoT will be able to evolve to offer new features beyond the conventional household space with IoT-dedicated solutions that present a broad range of opportunities,” said Ben Hur, vice president of System LSI marketing at Samsung Electronics. “Exynos i S111’s highly secure and efficient communication capabilities will bring more exciting NB-IoT applications to life.”

As IoT grows to be a part of our everyday lives, some connected devices share useful information instantly in high volumes, but some transmit data in small nuggets over a long period of time. Popular radio connectivity systems such as Bluetooth and ZigBee are suitable for short-range scenarios within confined spaces such as in the home or a building, and broadband communications are commonly used for mobile devices that demand high data rates. On the other hand, NB-IoT supports applications that require reliable low-power communication and wide-range coverage for small-sized data.

To cover long distances with high reliability, as a standard, NB-IoT adopts a data retransmission mechanism that continuously transmits data until a successful transfer, or up to a set number of retransmits. With a high number of these retransmit sessions, the S111 is able to cover the distance of 10-kilometers (km) or more.

Exynos i S111 incorporates a modem capable of LTE Rel. 14 support that can transmit data at 127-kilobits-per-second (kbps) for downlink and 158kbps uplink, and can operate in standalone, in-band and guard-band deployments.

For long standby periods, the S111 utilizes power saving mode (PSM) and expanded discontinuous reception (eDRX), which keeps the device dormant for long periods of time of 10 years and more, depending on application and use-cases. Exynos i S111 also has an integrated Global Navigation Satellite System (GNSS) and supports Observed Time Difference of Arrival (OTDOA), a positioning technique using cellular towers, for highly accurate and seamless real-time tracking.

Transmitted data are kept secure and private with the S111, as the solution utilizes a separate Security Sub-System (SSS) hardware block along with a Physical Unclonable Function (PUF) that creates a unique identity for each chipset.

Following the successful launch of the company’s first IoT solution, Exynos i T200, in 2017, Samsung plans to continue expanding the ‘Exynos i’ lineup with offerings specially tailored for narrowband networks.

A new study by scientists at the National Institute of Standards and Technology (NIST) has uncovered a source of error in an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to become progressively more acute as chipmakers pack ever more features into ever smaller space.

The error occurs when measuring very small flows of exotic gas mixtures. Small gas flows occur during chemical vapor deposition (CVD), a process that occurs inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing as many as several billion transistors. CVD builds up complex 3D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process called plasma etching also uses small flows of exotic gases to produce tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be highly accurate to ensure that the deposited layers have the required dimensions. The potential impact is large because chips with incorrect layer depths must be discarded.

“Flow inaccuracies cause nonuniformities in critical features in wafers, directly causing yield reduction,” said Mohamed Saleem, Chief Technology Officer at Brooks Instrument, a U.S. company that manufactures MFCs among other precision measurement devices. “Factoring in the cost of running cleanrooms, the loss on a batch of wafers scrapped due to flow irregularities can run around $500,000 to $1,000,000. Add to that cost the process tool downtime required for troubleshooting, and it becomes prohibitively expensive.”

Modern nanofabrication facilities cost several billion dollars each, and it is generally not cost-effective for a company to constantly fine tune CVD and plasma etching. Instead, the facilities rely on accurate gas flows controlled by MFCs. Typically, MFCs are calibrated using the “rate of rise” (RoR) method, which makes a series of pressure and temperature measurements over time as gas fills a collection tank through the MFC.

“Concerns about the accuracy of that technique came to our attention recently when a major manufacturer of chip-fabrication equipment found that they were getting inconsistent results for flow rate from their instruments when they were calibrated on different RoR systems,” said John Wright of NIST’s Fluid Metrology Group, whose members conducted the error analysis.

Wright was particularly interested because for many years he had seen that RoR readings didn’t agree with results obtained with NIST’s “gold standard” pressure/volume/temperature/time system. He and colleagues developed a mathematical model of the RoR process and conducted detailed experiments. The conclusion: conventional RoR flow measurements can have significant errors because of erroneous temperature values. “The gas is heated by flow work as it is compressed in the collection tank, but that is not easily accounted for: it is difficult to measure the temperature of nearly stationary gas.”

Wright and colleagues found that without corrections for these temperature errors, RoR readings can be off by as much as 1 percent, and perhaps considerably more. That might not seem like a lot, but low uncertainty is critical to attaining uniformity and quality in the chip manufacturing process. And the challenge is growing. Current low-end flow rates in the semiconductor industry are in the range of one standard cubic centimeter (1 sccm)–about the volume of a sugar cube–per minute, but they will soon shrink by a factor of 10 to 0.1 sccm.

Precise flow measurement is a particularly serious concern for manufacturing processes that use etching of deposited layers to form trench-like features. In that case, the MFC is often open for no more than a few seconds.

“A tiny amount of variation in the flow rate has a profound effect on the etch rate and critical dimensions of the structures” in very large-scale integrated circuits, said Iqbal Shareef of Lam Research, a company headquartered in California that provides precision fabrication equipment to microchip manufacturers.

“So, we are extremely concerned about flow rates being accurate and consistent from chamber to chamber and wafer to wafer,” Shareef said. “Our industry is already headed toward very small flow rates.”

“We are talking about wafer uniformity today on the nanometer and even subnanometer scale,” Shareef said.

That’s very small. But it’s what the complexity of three-dimensional chip manufacturing increasingly demands. Not so long ago, “a 3D integrated circuit used to have four layers of metals,” said William White, Director of Advanced Technology at HORIBA Instruments Incorporated, a global firm that provides analytical and measurement systems. “Now companies are regularly going to 32 layers and sometimes to 64. Just this year I heard about 128.” And some of those chips have as many as 3,000 process steps.

“Each 300 mm wafer can cost up to $400, and contains 281 dies for a die size of 250 to 300 mm2,” Brooks’ Saleem said. “Each die in today’s high-end integrated circuits consists of about three to four billion transistors. Each wafer goes through 1 or 2 months of processing that includes multiple runs of separate individual processes,” including chemical vapor deposition, etch, lithography and ion implantation. All those processes use expensive chemicals and gases.

Many companies are already re-examining their practices in light of the NIST publication, which provides needed theoretical explanations for the source of RoR flow measurement errors. The theory guides designers of RoR collection tanks and demonstrates easy-to-apply correction methods. RoR theory shows that different temperature errors will occur for the different gases used in CVD processes. The NIST publication also provides a model uncertainty analysis that others can use to know what level of agreement to expect between MFCs calibrated on different RoR systems.

“NIST serves as a reliable reference for knowledge and measurement where industry can assess agreement between their systems,” Wright said. “As manufacturers’ measurement needs push to ever lower flows, so will NIST calibration standards.”

A team of researchers led by the University of Minnesota has developed a new material that could potentially improve the efficiency of computer processing and memory. The researchers have filed a patent on the material with support from the Semiconductor Research Corporation, and people in the semiconductor industry have already requested samples of the material.

The findings are published in Nature Materials, a peer-reviewed scientific journal published by Nature Publishing Group.

This cross-sectional transmission electron microscope image shows a sample used for the charge-to-spin conversion experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. Credit: Wang Group, University of Minnesota

“We used a quantum material that has attracted a lot of attention by the semiconductor industry in the past few years, but created it in unique way that resulted in a material with new physical and spin-electronic properties that could greatly improve computing and memory efficiency,” said lead researcher Jian-Ping Wang, a University of Minnesota Distinguished McKnight Professor and Robert F. Hartmann Chair in electrical engineering.

The new material is in a class of materials called “topological insulators,” which have been studied recently by physics and materials research communities and the semiconductor industry because of their unique spin-electronic transport and magnetic properties. Topological insulators are usually created using a single crystal growth process. Another common fabrication technique uses a process called Molecular Beam Epitaxy in which crystals are grown in a thin film. Both of these techniques cannot be easily scaled up for use in the semiconductor industry.

In this study, researchers started with bismuth selenide (Bi2Se3), a compound of bismuth and selenium. They then used a thin film deposition technique called “sputtering,” which is driven by the momentum exchange between the ions and atoms in the target materials due to collisions. While the sputtering technique is common in the semiconductor industry, this is the first time it has been used to create a topological insulator material that could be scaled up for semiconductor and magnetic industry applications.

However, the fact that the sputtering technique worked was not the most surprising part of the experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. After testing the new material, the researchers found it to be 18 times more efficient in computing processing and memory compared to current materials.

“As the size of the grains decreased, we experienced what we call ‘quantum confinement’ in which the electrons in the material act differently giving us more control over the electron behavior,” said study co-author Tony Low, a University of Minnesota assistant professor of electrical and computer engineering.

Researchers studied the material using the University of Minnesota’s unique high-resolution transmission electron microscopy (TEM), a microscopy technique in which a beam of electrons is transmitted through a specimen to form an image.

“Using our advanced aberration-corrected scanning TEM we managed to identify those nano-sized grains and their interfaces in the film,” said Andre Mkhoyan, a University of Minnesota associate professor of chemical engineering and materials science and electron microscopy expert.

Researchers say this is only the beginning and that this discovery could open the door to more advances in the semiconductor industry as well as related industries, such as magnetic random access memory (MRAM) technology.

“With the new physics of these materials could come many new applications,” said Mahendra DC (Dangi Chhetri), first author of the paper and a physics Ph.D. student in Professor Wang’s lab.

Wang agrees that this cutting-edge research could make a big impact.

“Using the sputtering process to fabricate a quantum material like a bismuth-selenide-based topological insulator is against the intuitive instincts of all researchers in the field and actually is not supported by any existing theory,” Wang said. “Four years ago, with a strong support from Semiconductor Research Corporation and the Defense Advanced Research Projects Agency, we started with a big idea to search for a practical pathway to grow and apply the topological insulator material for future computing and memory devices. Our surprising experimental discovery led to a new theory for topological insulator materials.

“Research is all about being patient and collaborating with team members. This time there was a big pay off,” Wang said.

SiFive, a provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.

ASIC Design Services’ CDL technology optimizes its CNN accelerator FPGA core for performance, logic resources, and low power – making CDL suitable for IoT edge and node applications. The CDL Coldbrew software stack performs quantization and compression of CNNs, design space exploration, and generates a solution optimized for performance, resources, and low power. Coldbrew is built on the Caffe deep learning framework, and provides a simple user interface to bridge the gap between high-level CNN specification and FPGA design.

“We are excited about the increased performance and energy efficiency offered by FPGAs,” said Tony Dal Maso, CEO of ASIC Design Services. “Today, we can achieve 100 Gops/s/Watt on a low-power FPGA solution. By partnering with SiFive we enable the global community of embedded designers to accelerate deep learning solutions on embedded platforms.”

The availability of ASIC Design Services’ CDL IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, ASIC Design Services and other DesignShare partners provide low- or no-cost IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Adding artificial intelligence and neural networks to edge devices is increasingly in demand,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With ASIC Design Services addition to the DesignShare ecosystem, we continue to expand the range of IP available to designers looking to bring prototype devices to life.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

This expansion is in response to our customer’s request to take advantage of the field-proven performance of the flexible high speed MRSI-HVM3 platform, for their other essential packaging applications in photonics manufacturing which are high volume and high mix by nature.

The new MRSI-HVM3P is the first major extension to the HVM3 family, equipped with inline conveyor for single fixture or multiple cassette inputs that can automatically transport large forms of carriers of the dies. This configuration is targeted at AOC or similar die-to-printed circuit board (PCB) applications, gold-box packaging, and CoC in fixture. The processes include eutectic, epoxy stamping, UV epoxy dispensing, and in-situ UV curing.

“With these extensions to our successful HVM3 platform, MRSI Systems is now able to offer flexible high volume die bonding solutions, not just for CoC, but also for PCB and box levels of packaging to our customers in photonics, sensors and other advanced technology fields,” said Dr. Yi Qian, Vice President of Product Management of MRSI Systems. “This is another demonstration of MRSI’s commitment to provide critical solutions promptly in response to our customers’ needs,” concluded Mr. Michael Chalsen, President of MRSI Systems.

Both MRSI-HVM3 and MRSI-HVM3P now carry the following options inherited from our long proven MRSI-M3 family:  localized heating, flip-chip bonding, and co-planarity bonding. These options are increasingly critical for new applications such as 400G transceivers and silicon photonics.

The MRSI-HVM3 product family delivers industry-leading speed, future-proof high precision (<3mm), and superior flexibility for true multi-process, multi-chip, high-volume production.

The launch of the MRSI-HVM3P builds on the success of our first configuration launched last year, the MRSI-HVM3 for CoC, Chip-on-Submount (CoS), and Chip-on-Baseplate (CoB) assembly using eutectic and/or epoxy stamping die bonding, which has proved to be the best-in-class die bonder with the leading speed, zero-time tool change between dies, and <3mm accuracy. The superior performance was enabled by dual head, dual stage, integrated “on-the-fly” tool changer, ultrafast eutectic stage, and multi-levels of parallel processing optimizations (see product launch press release August 14, 2017).

MRSI Systems is exhibiting at China International Optoelectronic Expo (CIOE) with our partner CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 5-8, 2018 and ECOC (Booth #577) in Rome, Italy, September 24-26, 2018.

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has launched a new series of next-generation 650V power MOSFETs that are intended for use in server power supplies in data centers, solar (PV) power conditioners, uninterruptible power systems (UPS) and other industrial applications.

The first device in the DTMOS VI series is the TK040N65Z, a 650V device that supports continuous drain currents (ID) up to 57A and 228A when pulsed (IDP). The new device offers an ultra-low drain-source on-resistance RDS(ON) of 0.04Ω (0.033Ω typ.) which reduces losses in power applications. The enhancement mode device is ideal for use in modern high-speed power supplies, due to the reduced capacitance in the design.

Power supply efficiency is improved as a result of reductions in the key performance index / figure-of-merit (FoM) – RDS(ON) x Qgd. The TK040N65Z shows a 40% improvement in this important metric over the previous DTMOS IV-H device, which represents a significant gain in power supply efficiency in the region of 0.36%[1] – as measured in a 2.5kW PFC circuit.

The new device is housed in an industry-standard TO-247 package, ensuring compatibility with legacy designs as well as suitability for new projects.

Toshiba will continue to expand their product lineup to meet market trends and help improve the efficiency of power supplies and systems.

The new device enters mass production today and shipments begin immediately.

A Princeton-led study has revealed an emergent electronic behavior on the surface of bismuth crystals that could lead to insights on the growing area of technology known as “valleytronics.”

The term refers to energy valleys that form in crystals and that can trap single electrons. These valleys potentially could be used to store information, greatly enhancing what is capable with modern electronic devices.

In the new study, researchers observed that electrons in bismuth prefer to crowd into one valley rather than distributing equally into the six available valleys. This behavior creates a type of electricity called ferroelectricity, which involves the separation of positive and negative charges onto opposite sides of a material. This study was made available online in May 2018 and published this month in Nature Physics.

The finding confirms a recent prediction that ferroelectricity arises naturally on the surface of bismuth when electrons collect in a single valley. These valleys are not literal pits in the crystal but rather are like pockets of low energy where electrons prefer to rest.

The researchers detected the electrons congregating in the valley using a technique called scanning tunneling microscopy, which involves moving an extremely fine needle back and forth across the surface of the crystal. They did this at temperatures hovering close to absolute zero and under a very strong magnetic field, up to 300,000 times greater than Earth’s magnetic field.

The behavior of these electrons is one that could be exploited in future technologies. Crystals consist of highly ordered, repeating units of atoms, and with this order comes precise electronic behaviors. Silicon’s electronic behaviors have driven modern advances in technology, but to extend our capabilities, researchers are exploring new materials. Valleytronics attempts to manipulate electrons to occupy certain energy pockets over others.

The existence of six valleys in bismuth raises the possibility of distributing information in six different states, where the presence or absence of an electron can be used to represent information. The finding that electrons prefer to cluster in a single valley is an example of “emergent behavior” in that the electrons act together to allow new behaviors to emerge that wouldn’t otherwise occur, according to Mallika Randeria, the first author on the study and a graduate student at Princeton working in the laboratory of Ali Yazdani, the Class of 1909 Professor of Physics.

“The idea that you can have behavior that emerges because of interactions between electrons is something that is very fundamental in physics,” Randeria said. Other examples of interaction-driven emergent behavior include superconductivity and magnetism.

Nordson SONOSCAN, a developer and producer of acoustic micro imaging (AMI) tools, announces its new Gen7™ laboratory style acoustic micro-imaging tool. The new Gen7 AMI tool enhances operator productivity and part throughput rate by providing greater versatility in transducer movement, faster scanning of samples, and faster processing of data.

Orders are now being taken for the Gen7 AMI tool, which, like its predecessors in the Nordson SONOSCANC-SAM® line, is designed for analytical work on small numbers of samples, although it can also screen modest quantities of components. Among its differentiating features:

  • 50% higher screening throughput from faster transducer motors.
  • Scan area significantly enlarged, so more parts can be scanned at one time.
  • Upward and downward range of Z movement of the transducer more than doubled to enable scanning of samples having a greater range of height variation.
  • Windows® 10 operating system and Sonolytics 2™ user interface have replaced Windows® 7 and Sonolytics™, respectively.
  • Intel’s i7 seventh generation chips make the system’s computer hardware 33% faster, giving, for example, quicker delivery of Digital Image Analysis.
  • Both monitors have high resolution 4K screens to reveal more detail.
  • Includes Waterplume™ technology, so a separate C-SAM tool is not needed to image IGBT modules.

Users will notice that frequently used menu items now appear in the User Interface, eliminating the need to open a menu. Other changes include easy access to the current timing mode in the A-Scan and the ability to Go To a TOF directly from the movement interface.

A team of engineers at the University of Delaware is developing next-generation smart textiles by creating flexible carbon nanotube composite coatings on a wide range of fibers, including cotton, nylon and wool. Their discovery is reported in the journal ACS Sensors where they demonstrate the ability to measure an exceptionally wide range of pressure – from the light touch of a fingertip to being driven over by a forklift.

Fabric coated with this sensing technology could be used in future “smart garments” where the sensors are slipped into the soles of shoes or stitched into clothing for detecting human motion.

Carbon nanotubes give this light, flexible, breathable fabric coating impressive sensing capability. When the material is squeezed, large electrical changes in the fabric are easily measured.

“As a sensor, it’s very sensitive to forces ranging from touch to tons,” said Erik Thostenson, an associate professor in the Departments of Mechanical Engineering and Materials Science and Engineering.

Nerve-like electrically conductive nanocomposite coatings are created on the fibers using electrophoretic deposition (EPD) of polyethyleneimine functionalized carbon nanotubes.

“The films act much like a dye that adds electrical sensing functionality,” said Thostenson. “The EPD process developed in my lab creates this very uniform nanocomposite coating that is strongly bonded to the surface of the fiber. The process is industrially scalable for future applications.”

Now, researchers can add these sensors to fabric in a way that is superior to current methods for making smart textiles. Existing techniques, such as plating fibers with metal or knitting fiber and metal strands together, can decrease the comfort and durability of fabrics, said Thostenson, who directs UD’s Multifunctional Composites Laboratory. The nanocomposite coating developed by Thostenson’s group is flexible and pleasant to the touch and has been tested on a range of natural and synthetic fibers, including Kevlar, wool, nylon, Spandex and polyester. The coatings are just 250 to 750 nanometers thick — about 0.25 to 0.75 percent as thick as a piece of paper — and would only add about a gram of weight to a typical shoe or garment. What’s more, the materials used to make the sensor coating are inexpensive and relatively eco-friendly, since they can be processed at room temperature with water as a solvent.

Exploring Future Applications

One potential application of the sensor-coated fabric is to measure forces on people’s feet as they walk. This data could help clinicians assess imbalances after injury or help to prevent injury in athletes. Specifically, Thostenson’s research group is collaborating with Jill Higginson, professor of mechanical engineering and director of the Neuromuscular Biomechanics Lab at UD, and her group as part of a pilot project funded by Delaware INBRE. Their goal is to see how these sensors, when embedded in footwear, compare to biomechanical lab techniques such as instrumented treadmills and motion capture.

During lab testing, people know they are being watched, but outside the lab, behavior may be different.

“One of our ideas is that we could utilize these novel textiles outside of a laboratory setting — walking down the street, at home, wherever,” said Thostenson.

Sagar Doshi, a doctoral student in mechanical engineering at UD, is the lead author on the paper. He worked on making the sensors, optimizing their sensitivity, testing their mechanical properties and integrating them into sandals and shoes. He has worn the sensors in preliminary tests, and so far, the sensors collect data that compares with that collected by a force plate, a laboratory device that typically costs thousands of dollars.

“Because the low-cost sensor is thin and flexible the possibility exists to create custom footwear and other garments with integrated electronics to store data during their day-to-day lives,” Doshi said. “This data could be analyzed later by researchers or therapists to assess performance and ultimately bring down the cost of healthcare.”

This technology could also be promising for sports medicine applications, post-surgical recovery, and for assessing movement disorders in pediatric populations.

“It can be challenging to collect movement data in children over a period of time and in a realistic context,” said Robert Akins, Director of the Center for Pediatric Clinical Research and Development at the Nemours – Alfred I. duPont Hospital for Children in Wilmington and affiliated professor of materials science and engineering, biomedical engineering and biological sciences at UD. “Thin, flexible, highly sensitive sensors like these could help physical therapists and doctors assess a child’s mobility remotely, meaning that clinicians could collect more data, and possibly better data, in a cost-effective way that requires fewer visits to the clinic than current methods do.”

Interdisciplinary collaboration is essential for the development of future applications, and at UD, engineers have a unique opportunity to work with faculty and students from the College of Health Sciences on UD’s Science, Technology and Advanced Research (STAR) Campus.

“As engineers, we develop new materials and sensors but we don’t always understand the key problems that doctors, physical therapists and patients are facing,” said Doshi. “We collaborate with them to work on the problems they are facing and either direct them to an existing solution or create an innovative solution to solve that problem.”

Thostenson’s research group also uses nanotube-based sensors for other applications, such as structural health monitoring.

“We’ve been working with carbon nanotubes and nanotube-based composite sensors for a long time,” said Thostenson, who is affiliated faculty at UD’s Center for Composite Materials (UD-CCM). Working with researchers in civil engineering his group has pioneered the development of flexible nanotube sensors to help detect cracks in bridges and other types of large-scale structures. “One of the things that has always intrigued me about composites is that we design them at varying lengths of scale, all the way from the macroscopic part geometries, an airplane or an airplane wing or part of a car, to the fabric structure or fiber level. Then, the nanoscale reinforcements like carbon nanotubes and graphene give us another level to tailor the material structural and functional properties. Although our research may be fundamental, there is always an eye towards applications. UD-CCM has a long history of translating fundamental research discoveries in the laboratory to commercial products through UD-CCM’s industrial consortium.”