Tag Archives: letter-pulse-tech

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the new SmartView® NT3 aligner, which is available on the company’s industry benchmark GEMINI® FB XT integrated fusion bonding system for high-volume manufacturing (HVM) applications. Developed specifically for fusion and hybrid wafer bonding, the SmartView NT3 aligner provides sub-50-nm wafer-to-wafer alignment accuracy — a 2-3X improvement — as well as significantly higher throughput (up to 20 wafers per hour) compared to the previous-generation platform.

With the new SmartView NT3 aligner, the GEMINI FB XT provides integrated device manufacturers, foundries and outsourced semiconductor assembly and test providers (OSATs) with wafer bonding performance that is unmatched in the industry and can meet their future 3D-IC packaging requirements. Applications enabled by the enhanced GEMINI FB XT include memory stacking, 3D systems on chip (SoC), backside illuminated CMOS image sensor stacking, and die partitioning.

The new SmartView® NT3 aligner on EV Group’s GEMINI® FB XT fusion bonder enables a 2-3X improvement in wafer-to-wafer alignment accuracy over EVG’s previous-generation aligner.

Wafer Bonding an Enabling Process for 3D Device Stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

“At imec, we believe in the power of 3D technology to create new opportunities and possibilities for the semiconductor industry, and we are devoting a great deal of energy into improving it,” stated Eric Beyne, imec fellow and program director 3D system integration. “One area of particular focus is wafer-to-wafer bonding, where we are achieving excellent results in part through our work with industry partners such as EV Group. Last year, we succeeded in reducing the distance between the chip connections, or pitch, in hybrid wafer-to-wafer bonding to 1.4 microns, which is four times smaller than the current standard pitch in the industry. This year we are working to reduce the pitch by at least half again.”

“EVG’s GEMINI FB XT fusion bonding system has consistently led the industry in not only meeting but exceeding performance requirements for advanced packaging applications, with key overlay accuracy milestones achieved with several industry partners within the last year alone,” stated Paul Lindner, executive technology director, EV Group. “With the new SmartView NT3 aligner specifically engineered for the direct bonding market and added to our widely adopted GEMINI FB XT fusion bonder, EVG once again redefines what is possible in wafer bonding — helping the industry to continue to push the envelope in enabling stacked devices with increasing density and performance, lower power consumption and smaller footprint.”

The GEMINI FB XT fusion bonder with new SmartView NT3 aligner is available for customer demonstrations and testing. More information on the product can be found on EVG’s website at https://www.evgroup.com/en/products/bonding/integrated_bonding/geminifb/.

EVG will showcase the GEMINI FB XT with new SmartView NT3 aligner, along with its complete suite of wafer bonding, lithography and resist processing solutions for advanced packaging applications, at SEMICON West, to be held July 10-12 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #623 in the South Hall.

In addition, Dr. Thomas Uhrmann, director of business development at EV Group, will highlight the GEMINI FB XT and other developments in wafer bonding in his presentation “Collective Bonding for Heterogeneous Integration in Advanced Packaging” at the Meet the Experts Theater Smart Manufacturing Pavilion at SEMICON West on Thursday, July 12 from 3:00-3:30 p.m. in the South Hall.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 7-nanometer (nm) Low Power Plus (LPP) process technology. The Cadence® tools were certified for the Process Design Kit (PDK) and foundation library on the 7LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling systems and semiconductor companies to accelerate the delivery of 7LPP designs.

The Cadence RTL-to-GDSII design flow that has been certified for the 7LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design.

The Cadence digital and signoff tools are available via a quick-start kit. The certified tools include the Innovus™ Implementation System, Genus™Synthesis Solution, Joules™ RTL Power Solution, Conformal® Equivalence Checking, Conformal Low Power, Modus™ DFT Software Solution, Voltus™IC Power Integrity Solution, Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, Cadence Physical Verification System (PVS), Cadence CMP Predictor (CCP) and Cadence Litho Physical Analyzer (LPA).

“Our 7LPP process provides the best power, performance and area that we have seen so far in advanced FinFET nodes, and we expect this will provide great benefits for our mutual customers’ next generation SoC designs,” said Ryan Sanghyun Lee, vice president of the Foundry Marketing at Samsung Electronics. “By working closely with Cadence, we have been able to ensure that our customers can get these benefits quickly and easily using the certified Cadence digital and signoff full flow.”

“Using our full RTL-to-GDSII reference flow, our customers can take advantage of the advanced-node innovation provided in the 7LPP process,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our ongoing collaboration with Samsung Foundry enables us to provide the tools our customers require to quickly complete the most complex designs.”

Alta Devices has today announced that its most recent single junction solar cell has been certified by NREL (National Renewable Energy Laboratory) as being 28.9% efficient. This certification confirms that Alta has set a new record and continues to hold the world record efficiency for this type of solar cell. This breakthrough, combined with the unique thinness and flexibility of Alta’s cells, redefines how solar technology can be used to empower autonomy in many applications.

“Alta Devices goal is to continue to lead the industry in solar technology and to enable a broad range of autonomous systems. We believe this is the best way to support the innovations of our customers,” said Jian Ding, Alta Devices CEO.

Autonomous systems are predicted to become a part of daily life – often operating without human intervention. However, every time an autonomous system or vehicle has to stop to refuel or recharge, it requires intervention and is no longer truly autonomous. Alta focuses on developing the world’s best solar technology specifically for autonomous power, allowing vehicles to seamlessly recharge while in motion.

Alta Devices has held continuous world records for solar efficiency for most of the last decade. Alta Devices Founders, Professor Harry Atwater of Caltech and Professor Eli Yablonovitch of the University of California Berkeley explained the significance of this record:

Prof. Atwater said, “Achieving a new record for this class of devices is a landmark because a 1-sun, 1-junction cell is the archetypal solar cell. The fact that Alta is breaking its own record is also significant since many other teams have been actively attempting to break this record.”

Elaborating on the fundamental technical understanding that has driven this achievement, Professor Yablonovitch said, “Alta has the first solar cell based on Internal Luminescence Extraction, which has enabled Alta to remain ahead of others. This scientific principle will be in all future high efficiency solar cells.”

The company has recently launched its Gen4 AnyLight™ commercial technology, demonstrating a significant weight reduction from the previous version, resulting in an improved power to weight ratio of 160 percent. This is critical for tomorrow’s autonomous UAVs (unmanned aerial vehicles), electric vehicles, and sensors. It can be used to generate substantial power over small surfaces without compromising design criteria.

As silicon-based semiconductors reach their performance limits, gallium nitride (GaN) is becoming the next go-to material to advance light-emitting diode (LED) technologies, high-frequency transistors and photovoltaic devices. Holding GaN back, however, is its high numbers of defects.

This material degradation is due to dislocations — when atoms become displaced in the crystal lattice structure. When multiple dislocations simultaneously move from shear force, bonds along the lattice planes stretch and eventually break. As the atoms rearrange themselves to reform their bonds, some planes stay intact while others become permanently deformed, with only half planes in place. If the shear force is great enough, the dislocation will end up along the edge of the material.

As silicon-based semiconductors reach performance limits, gallium nitride is becoming the next go-to material for several technologies. Holding GaN back, however, is its high numbers of defects. Better understanding how GaN defects form at the atomic level could improve the performance of the devices made using this material. Researchers have taken a significant step by examining and determining six core configurations of the GaN lattice. They present their findings in the Journal of Applied Physics. This image shoes the distribution of stresses per atom (a) and (b) of a-edge dislocations along the <1-100> direction in wurtzite GaN. Credit: Physics Department, Aristotle University of Thessaloniki

Layering GaN on substrates of different materials makes the problem that much worse because the lattice structures typically don’t align. This is why expanding our understanding of how GaN defects form at the atomic level could improve the performance of the devices made using this material.

A team of researchers has taken a significant step toward this goal by examining and determining six core configurations of the GaN lattice. They presented their findings in the Journal of Applied Physics, from AIP Publishing.

“The goal is to identify, process and characterize these dislocations to fully understand the impact of defects in GaN so we can find specific ways to optimize this material,” said Joseph Kioseoglou, a researcher at the Aristotle University of Thessaloniki and an author of the paper.

There are also problems that are intrinsic to the properties of GaN that result in unwanted effects like color shifts in the emission of GaN-based LEDs. According to Kioseoglou, this could potentially could be addressed by exploiting different growth orientations.

The researchers used computational analysis via molecular dynamics and density functional theory simulations to determine the structural and electronic properties of a-type basal edge dislocations along the <1-100> direction in GaN. Dislocations along this direction are common in semipolar growth orientations.

The study was based on three models with different core configurations. The first consisted of three nitrogen (N) atoms and one gallium (Ga) atom for the Ga polarity; the second had four N atoms and two Ga atoms; the third contained two N atoms and two Ga core-associated atoms. Molecular dynamic calculations were performed using approximately 15,000 atoms for each configuration.

The researchers found that the N polarity configurations exhibited significantly more states in the bandgap compared to the Ga polarity ones, with the N polar configurations presenting smaller bandgap values.

“There is a connection between the smaller bandgap values and the great number of states inside them,” said Kioseoglou. “These findings potentially demonstrate the role of nitrogen as a major contributor to dislocation-related effects in GaN-based devices.”

Researchers at Tokyo Institute of Technology have developed flexible terahertz imagers based on chemically “tunable” carbon nanotube materials. The findings expand the scope of terahertz applications to include wrap-around, wearable technologies as well as large-area photonic devices.

Carbon nanotubes (CNTs) are beginning to take the electronics world by storm, and now their use in terahertz (THz) technologies has taken a big step forward.

The CNT THz imager enabled clear, non-destructive visualization of a metal paper clip inside an envelope. Credit: ACS Applied Nano Materials

Due to their excellent conductivity and unique physical properties, CNTs are an attractive option for next-generation electronic devices. One of the most promising developments is their application in THz devices. Increasingly, THz imagers are emerging as a safe and viable alternative to conventional imaging systems across a wide range of applications, from airport security, food inspection and art authentication to medical and environmental sensing technologies.

The demand for THz detectors that can deliver real-time imaging for a broad range of industrial applications has spurred research into low-cost, flexible THz imaging systems. Yukio Kawano of the Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology (Tokyo Tech), is a world-renowned expert in this field. In 2016, for example, he announced the development of wearable terahertz technologies based on multiarrayed carbon nanotubes.

Kawano and his team have since been investigating THz detection performance for various types of CNT materials, in recognition of the fact that there is plenty of room for improvement to meet the needs of industrial-scale applications.

Now, they report the development of flexible THz imagers for CNT films that can be fine-tuned to maximize THz detector performance.

Publishing their findings in ACS Applied Nano Materials, the new THz imagers are based on chemically adjustable semiconducting CNT films.

By making use of a technology known as ionic liquid gating[1], the researchers demonstrated that they could obtain a high degree of control over key factors related to THz detector performance for a CNT film with a thickness of 30 micrometers. This level of thickness was important to ensure that the imagers would maintain their free-standing shape and flexibility, as shown in Figure 1.

“Additionally,” the team says, “we developed gate-free Fermi-level[2] tuning based on variable-concentration dopant solutions and fabricated a Fermi-level-tuned p?n junction[3] CNT THz imager.” In experiments using this new type of imager, the researchers achieved successful visualization of a metal paper clip inside a standard envelope (see Figure 2.)

The bendability of the new THz imager and the possibility of even further fine-tuning will expand the range of CNT-based devices that could be developed in the near future.

Moreover, low-cost fabrication methods such as inkjet coating could make large-area THz imaging devices more readily available.

GLOBALFOUNDRIES today announced that Socionext Inc. will manufacture the third and latest generation of its graphics display controllers, the SC1701, on GF’s 55nm Low Power Extended (55LPx) process technology with embedded non-volatile memory (SuperFlash®). The 55LPx platform enables several new features in Socionext’s SC1701 series including enhanced diagnostic and security protection capabilities, cyclic redundancy code (CRC) checks, picture freeze detection, and multi window signature unit for advanced in-vehicle display systems. The shipping of the SC1701 from Socionext will start at the end of July.

In recent years, the number of in-vehicle electronic systems has risen exponentially with increasing requirements for multiple content-rich displays. Socionext’s SC1701 controller integrates a variety of system component features along with APIX®3 technology and automotive safety functions to meet the increasing demand for high speed video and data connectivity and stringent safety requirements. The device supports display resolution up to one U-HD (4K) or two F-HD (2K) at 30bpp, and capable of receiving two separate video streams over a single link by utilizing the VESA® display stream compression (DSC) method. Moreover, the SC1701 offers video content protection through built-in HDCP decryption technology that enables a richer user experience.

“The SC1701 display controller is designed to support high performance computing within a vehicle, with one of the most innovative evolutions in automotive system architectures,” said Koichi Yamashita, senior vice president and head of IoT and Graphics Solution Business Unit at Socionext. “GF’s automotive grade 1 qualified 55LPx platform, with its low power logic and highly reliable embedded non-volatile memory, was ideal for our product.”

GF’s 55LPx platform, with SST’s SuperFlash® memory technology, provides a fast path-to-product solution, and is fully qualified for consumer, industrial and automotive grade 1 applications. The implementation of SuperFlash® on 55LPx provides a small bitcell size, increased fast read speed along with superior data retention and endurance.

“GF is excited to be working with Socionext, who is a leader in state-of-the-art SoC technology,” said Dave Eggleston, vice president of embedded memory at GF. “Socionext joins our rapidly growing client base for GF’s 55LPx platform, which offers a combination of superior low power logic, embedded non-volatile memory, extensive IP, and superior reliability for the industrial and automotive grade 1 system-on-chip markets.”

The 55LPx-enabled platform is in volume production at GF’s 300mm line in Singapore. In addition to the SC1701, Socionext is currently developing several products on the technology, joining On Semiconductor, Silicon Mobility and Fudan Microelectronics, who are currently optimizing their chip designs with GF’s 55LPx platform for wearable IoT and automotive products.

Process design kits and an extensive offering of silicon proven IP are available now. For more information on GF’s mainstream CMOS solutions, contact your GF sales representative or go to globalfoundries.com.

An international collaborative research group including Tokyo Institute of Technology, Universite PARIS DIDEROT and CNRS has discovered that CO2 is selectively reduced to CO[1] when a photocatalyst[2] composed of an organic semiconductor material and an iron complex is exposed to visible light. They have made clear that it is possible to convert CO2, the major factor of global warming, into a valuable carbon resource using visible light as the energy source, even with a photocatalyst composed of only commonly occurring elements.

This is CO2 reduction using a photocatalyst combining carbon nitride and an iron compl. Credit: Osamu Ishitani

In recent years, technologies to reduce CO2into a resource using metal complexes and semiconductors as photocatalysts are being developed worldwide. If this technology called artificial photosynthesis can be applied, scientists would be able to convert CO2, which is considered the major factor of global warming and is being treated as a villain, into a valuable carbon resource using sunlight as the energy source.

Complexes and inorganic semiconductors containing precious and rare metals such as ruthenium, rhenium, and tantalum have been used in highly active photocatalysts reported so far. However, considering the tremendous amount of CO2, there was a need to create new photocatalysts made only with elements widely available on Earth.

Professor Osamu Ishitani, Associate Professor Kazuhiko Maeda, research staff Ryo Kuriki and others of Tokyo Tech, with the support of JST (Japan Science and Technology Agency)’s Strategic Basic Research Programs (CREST Establishment of Molecular Technology towards the Creation of New Functions) for international collaborative research projects, performed collaborative research with the research group of Professor Marc Robert of Universite PARIS DIDEROT and CNRS. As a result, by fusing carbon nitride, an organic semiconductor, with a complex made of iron and organic materials and using it as a photocatalyst, they succeeded in turning CO2 into a resource at high efficiency under the condition of exposure to visible light at ordinary temperature and pressure.

By combining the organic semiconductor carbon nitride[3], made of carbon and nitrogen, with an iron complex and using it as a photocatalyst, they found that they could reduce carbon dioxide (CO2) to carbon monoxide (CO) at high efficiency. This photocatalytic reaction progresses when exposed to visible light, which is the major component in the wavelength band of sunlight. The carbon nitride absorbs visible light and drives the migration of electrons from the reducing agent to the iron complex, the catalyst. The iron complex uses that electrons to reduce CO2 to CO. The turnover number[4], the external quantum efficiency[5], and the selectivity[6] of CO2 reduction–performance indicators for the formation of CO–reached 155, 4.2%, and 99%, respectively. These values are almost the same as when precious metal or rare metal complexes are used, and about ten times more than photocatalysts reported so far using base metals or organic molecules.

This research was the first to demonstrate that CO2 can be reduced into a resource efficiently using sunlight as the energy source, even by using materials which exist abundantly on Earth, such as carbon, nitrogen, and iron. Tasks remaining are to further improve their function as a photocatalyst and to succeed in fusing them with oxidation photocatalysts which can use water, which exists abundantly on Earth and is inexpensive, as a reducing agent.

TowerJazz, the global specialty foundry, today announced a ramp for its radio frequency silicon-on-insulator (RF SOI) 65nm process in its 300mm Uozu, Japan fab. TowerJazz has signed a contract with long-term partner, SOITEC, a semiconductor materials supplier to guarantee a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a very tight SOI wafer market.

With best in class metrics, TowerJazz’s 65nm RF SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals.

According to Mobile Experts, LLC, a market research firm for mobile communications, the mobile RF front-end market is estimated to reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz’s breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards which will boost data rates and provide further content growth opportunities in the coming years.

TowerJazz is also proud to announce its relationship with Maxscend, a provider of RF components and IoT integrated circuits, ramping in this new technology.

“We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Zhihan Xu, Maxscend Chief Executive Officer.

“We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF SOI partnership.  TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings,” said Paul Boudre, SOITEC Chief Executive Officer.

“We are thrilled about our continued partnership with Maxscend as they bring breakthrough products to market, manufactured using our latest 300mm 65nm RF SOI platform. Also, we are very pleased with our SOITEC partnership to secure tens of thousands of 300mm RF SOI wafers to feed the strong demand in our 300mm Japan factory,” said Russell Ellwanger, TowerJazz Chief Executive Officer.

For more information on TowerJazz’s 65nm RF SOI technology, please visit: http://www.towerjazz.com/sige-bicmos_rf-cmos.html.

Optimum Semiconductor Technologies, Inc., a fabless semiconductor company providing highly-integrated Systems on Chips (SoCs) for China’s thriving electronics markets, announced the GP8300 SoC. The GP8300 dramatically reduces chip cost, area, and power consumption for image recognition and object detection in a broad range of products such as self-driving cars, autonomous vehicles, smart cameras and other IoT edge devices.

Created in 28nm technology, the GP8300 includes four 2GHz ‘Unity’ CPU cores from General Processor Technologies (GPT) interconnected with a cache coherent memory supporting Heterogeneous Systems Architecture (HSA) processing for a common programming framework. The GP8300 also integrates four of GPT’s new 2GHz Variable Length Vector DSP (VLVm1) cores for signal processing applications. Within the chip, the out-of-order CPUs execute control code while very long vectors process data. In addition to these generalized compute units, the chip also integrates two 1GHz AI accelerators from GPT.

“The GP8300 brings together several of GPT’s innovative IP cores with underlying embedded artificial intelligence (eAI) algorithms in a highly-integrated design targeting a wide range of exciting applications,” said Gary Nacer, President and COO of Optimum. “The new SoC is one of the first CNN accelerators in China, and it provides the right combination of high performance, low power consumption, and the cost efficiency that our customers need as they create innovative new products.”

Building on the success of OST’s innovative SB3500 multithreaded heterogeneous computing platform for low-power software defined radio (SDR), the GP8300 represents a new architecture that achieves deep integration of eAI, edge computing, and communications on a single chip. OST provides support for CaffeNet-based training and tools for automatic fixed-point conversion and compression for inference.

A team headed by the TUM physicists Alexander Holleitner and Reinhard Kienberger has succeeded for the first time in generating ultrashort electric pulses on a chip using metal antennas only a few nanometers in size, then running the signals a few millimeters above the surface and reading them in again a controlled manner.

Classical electronics allows frequencies up to around 100 gigahertz. Optoelectronics uses electromagnetic phenomena starting at 10 terahertz. This range in between is referred to as the terahertz gap, since components for signal generation, conversion and detection have been extremely difficult to implement.

The TUM physicists Alexander Holleitner and Reinhard Kienberger succeeded in generating electric pulses in the frequency range up to 10 terahertz using tiny, so-called plasmonic antennas and run them over a chip. Researchers call antennas plasmonic if, because of their shape, they amplify the light intensity at the metal surfaces.

Asymmetric antennas

The shape of the antennas is important. They are asymmetrical: One side of the nanometer-sized metal structures is more pointed than the other. When a lens-focused laser pulse excites the antennas, they emit more electrons on their pointed side than on the opposite flat ones. An electric current flows between the contacts – but only as long as the antennas are excited with the laser light.

“In photoemission, the light pulse causes electrons to be emitted from the metal into the vacuum,” explains Christoph Karnetzky, lead author of the Nature work. “All the lighting effects are stronger on the sharp side, including the photoemission that we use to generate a small amount of current.”

Ultrashort terahertz signals

The light pulses lasted only a few femtoseconds. Correspondingly short were the electrical pulses in the antennas. Technically, the structure is particularly interesting because the nano-antennas can be integrated into terahertz circuits a mere several millimeters across.

In this way, a femtosecond laser pulse with a frequency of 200 terahertz could generate an ultra-short terahertz signal with a frequency of up to 10 terahertz in the circuits on the chip, according to Karnetzky.

The researchers used sapphire as the chip material because it cannot be stimulated optically and, thus, causes no interference. With an eye on future applications, they used 1.5-micron wavelength lasers deployed in traditional internet fiber-optic cables.

An amazing discovery

Holleitner and his colleagues made yet another amazing discovery: Both the electrical and the terahertz pulses were non-linearly dependent on the excitation power of the laser used. This indicates that the photoemission in the antennas is triggered by the absorption of multiple photons per light pulse.

“Such fast, nonlinear on-chip pulses did not exist hitherto,” says Alexander Holleitner. Utilizing this effect he hopes to discover even faster tunnel emission effects in the antennas and to use them for chip applications.